Abstract: Wireless power transfer systems and methods for focusing wireless power transfer arrays are disclosed. One embodiment includes a wireless power generating unit (GU) including a processing system configured to focus the RF power sources by: sending control signals to the control circuitry to perform a plurality of sweeps using each of a plurality of different basis masks; receiving a message from a RU containing a report based upon received power measurements made by the RU; and sending control signals to focus the RF power sources based on the received message from the RU. Furthermore, each sweep includes performing a phase sweep across a phase sweep range at a plurality of phase step increments with respect to a first group of RF power sources identified in a basis mask, where the first group of RF power sources comprises a plurality of RF power sources.

Abstract: Provided is an optical probe, and a Raman spectroscopy system using such, including excitation and detection optics coupled to a sampling optics via a beam splitter, in confocal arrangement with a sample focal plane of the sampling optics. The detection optics is arranged to receive Raman signal from the sample focal plane and direct it onto a tip of a detection optical fiber. The optical probe may further include a positioning device mechanically coupled to the sampling optics and configured to control a position of the sample focal plane. In the Raman spectroscopy system a light source is coupled to the excitation optics via an excitation optical fiber, and a spectrometer is coupled to a detection optics via a detection optical fiber. Provided is further a method for measuring Raman signal depth profile in a sample, wherein sample's Raman spectra is measured and stored at different focal plane positions.

Abstract: An artificial neuron including: a membrane capacitor; an input of an external synaptic excitation in current, the membrane capacitor integrating the input current; a negative-feedback impulse circuit, supplied by a power supply at a negative voltage between ?200 mV and 0 mV and at a positive voltage between 0 mV and +200 mV, including: a bridge based on pMOS and nMOS transistors in series and linked by a midpoint to the membrane capacitor, the midpoint defining the output of the artificial neuron, at least one delay capacitor between the gate and the source of one of the transistors of the bridge, at least two CMOS inverters between the membrane capacitor and the gates of the transistors of the bridge.

Abstract: The present technology relates to an amplifier and a signal processing circuit that can reduce deterioration of signal quality. A voltage-to-time converter (VTC) integrates error information included in an output pulse width modulation (PWM) signal that is a PWM signal to be output to an outside of a device, so as to convert the error information into error time information. A delay unit generates a plurality of delayed signals using an input PWM signal that is a PWM signal input from the outside of the device. A signal selection unit selects a delayed signal according to the error time information from the plurality of delayed signals and outputs the output PWM signal. The present disclosure can be applied to, for example, an audio player.

Abstract: Power consumption is reduced in a solid-state imaging element including a differential input circuit for each pixel. The solid-state imaging element includes a current source circuit, a pair of differential transistors, and a digital signal generating unit. The current source circuit in the solid-state imaging element supplies a predetermined constant current in a case where a predetermined enable signal is input. The pair of differential transistors generates a differential amplified signal using the constant current, the differential amplified signal being obtained by amplifying a difference between an analog signal generated by a pixel circuit and a predetermined reference signal. The digital signal generating unit generates a digital signal from the differential amplified signal.

Abstract: A dynamic voltage-to-delay device may have voltage lines for receiving input signals during reset phases, and a current source, connected to the first and second voltage lines, for increasing voltages on the voltage lines during active phases. The voltage-to-delay device may also have comparators, connected to the voltage lines, for generating first and second output signals during the active phases when the voltages on the voltage lines reach a threshold voltage, such that a delay between the output signals is representative of a difference between voltages of the input signals. The voltage-to-delay device may have at least two current sources. The comparators may have a tail node to which a voltage is applied during a reset phase, and a current source for reducing the voltage at the tail node, and thereby reducing a threshold voltage during an active phase.

Abstract: A simulation method and a corresponding medium storing processor-executable code for detecting a high impedance net within an electronic circuit comprising a plurality of transistors is presented. The simulation method includes the step of connecting programmable resistors between two terminals of each transistor. Subsequently, voltage fluctuations are determined at the first terminals of a first group of transistors, where the voltage fluctuations are caused by connecting the programmable resistors. By connecting current sources with the first terminals of the first group of transistors, a potentially hazardous high impedance net may be detected within the electronic circuit.

Abstract: Circuits and systems for generating counter signals are provided herein. A circuit may comprise a shift register having a series of flip-flops. Each of the flip-flops of the series may be coupled to a clock. The shift register may generate a borrowing clock signal using an output of a flip-flop of the shift register, and a transition of the borrowing clock signal may be advanced by a number of clock cycles based on a position of the flip-flop of the shift register. The circuit may further comprise a clock divider circuit having a number of divide-by-N counters and a number of flip-flops. A divide-by-N counter may be coupled to a flip-flop of the shift register, and a flip-flop of the clock divider circuit may be coupled to one of the divide-by-N counters and to the clock.

Abstract: A clock multiplier is provided. The clock multiplier includes a delay line, an output clock generator, and a delay controller. The delay line receives an input clock and delays the input clock according to a selection signal group with multiple bits to provide a plurality of delayed clocks and a feedback clock. The output clock generator performs a logic operation on the input clock and a portion of the delayed clocks to generate an output clock. A frequency of the output clock is an integer multiple of a frequency of the input clock. The delay controller adjusts the selection signal group according to a timing difference between the input clock and the feedback clock, so that a transition point of the feedback clock approaches a transition point of the input clock.

Abstract: The embodiments of the present disclosure relate to a device for temperature detection, including a delay unit including an odd number of inverters coupled end to end, a switching transistor having a control electrode coupled to an output end of the delay unit, a first electrode coupled to an operating voltage node of the device, and a second electrode coupled to an input end of the delay unit, a first capacitor having a first end coupled to the input end of the delay unit, and a second end coupled to the first electrode of the switching transistor or a ground node of the device, and a temperature sensitive transistor having a control electrode coupled to a bias voltage end of the device, a first electrode coupled to the input end of the delay unit, and a second electrode coupled to the ground node of the device.

Abstract: Wireless power transfer systems and methods for focusing wireless power transfer arrays are disclosed. One embodiment includes a wireless power generating unit (GU) including a processing system configured to focus the RF power sources by: sending control signals to the control circuitry to perform a plurality of sweeps using each of a plurality of different basis masks; receiving a message from a RU containing a report based upon received power measurements made by the RU; and sending control signals to focus the RF power sources based on the received message from the RU. Furthermore, each sweep includes performing a phase sweep across a phase sweep range at a plurality of phase step increments with respect to a first group of RF power sources identified in a basis mask, where the first group of RF power sources comprises a plurality of RF power sources.

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

Abstract: Detecting the health of a phase-lock loop (PLL) generating a feedback clock signal based on a reference clock signal, includes providing, by a delay line, the feedback clock signal to a plurality of latches clocked by the reference clock signal; providing, based on an output of the plurality of latches, an input to a plurality of sticky latches, the input indicating whether an edge of the feedback clock signal was detected; determining, based on a number of asserted sticky latches of the plurality of sticky latches, a phase error metric; comparing the phase error metric to a threshold; and outputting, based on the comparison, an indication of a lock state.

Abstract: A duty cycle correction system corrects for duty cycle distortion by measuring average time interval durations of consecutive intervals of an input signal. The system generates complementary ramp signals that have cross-points indicating midpoints of the intervals, and detects those cross-points. An output circuit of the duty cycle correction system generates an output signal that performs rising and falling transitions in response to the detected cross-points.

Abstract: A memory circuit includes, a latch circuit that includes a first node, a second node, a first inverter having an input coupled to the first node and an output coupled to the second node, and a second inverter having an input coupled to the second node and an output coupled to the first node, a writing circuit that includes a first transistor coupled to the first node and a second transistor coupled to the second node and executes writing to the latch circuit using the first transistor and the second transistor, a command circuit detects the execution of the writing to the latch circuit and output a command signal to increase the potential of the second node before the termination of the writing of a low level to the first node, and a potential control circuit increases the potential of the second node based on the command signal.

Abstract: A transmitter includes a predriver circuit configured to perform a first equalization process to compensate jitter caused by the predriver circuit. The predriver circuit includes a first path having a first driving strength and configured to generate a first path output signal by applying a first delay to a predriver input signal. The predriver circuit includes a second path having a second driving strength less than the first driving strength and configured to generate a second path output signal by applying a second delay to the predriver input signal. A summing node is configured to combine the first path output signal and the second path output signal to provide a summing node output signal. A driver circuit coupled to the predriver circuit is configured to generate a driver output signal based on the summing node output signal and drive the driver output signal to a receiver through a channel.

Abstract: In pipelined analog-to-digital converters (ADCs), a passive switched capacitor (PSWC) circuit can be used in a multiplying analog-to-digital converter (MDAC), which generates an analog output being fed to a subsequent stage. Complementary analog input signals are sampled respectively onto first and second capacitors, which are stacked to provide gain. The first capacitor is positioned between a first input switch and an output node of the PSWC circuit, and the second capacitor is positioned between the second input switch and a digital-to-analog converter (DAC) output. The topology advantageously isolates common modes of the complementary analog input signals, the DAC output, and the output of the PSWC circuit. As a result, the topology offers more degrees of freedom in the overall circuit design when stages having the MDAC are cascaded, resulting in pipelined ADCs with a more elegant design with lower noise and lower power consumption.

Abstract: A reverberator based on a room response modal analysis is adapted to produce distortion, pitch and time manipulation effects, as well as gated and iterated reverberation. An example “modal reverberator” is a parallel collection of resonant filters, with resonance frequencies and dampings tuned to the modal frequencies and decay times of the space or object being simulated. In one example, the resonant filters are implemented as cascades of heterodyning, smoothing, and modulation steps, forming a type of analysis/synthesis architecture. By applying memoryless nonlinearities to the modulating sinusoids, distortion effects are produced, including distortion without intermodulation products. By using different frequencies for the heterodyning and associated modulation operations, pitch manipulation effects are generated, including pitch shifting and spectral “inversion.” By resampling the smoothing filter output, the signal time axis is stretched without introducing pitch changes.

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

Abstract: In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.

Abstract: It is presented a lock device comprising: a controller configured to determine whether to open the lock device, wherein the controller is configured to provide an open signal when the lock device it to be opened, the open signal being a pulsating signal; a motor controllable to set the lock device in an open state or a closed state; and a motor driver connected between the controller and the motor, the motor driver comprising a capacitor providing a capacitive coupling between the controller and the motor, the motor driver being configured to provide a motor control signal to the motor to set the lock device in an open state only when a duty cycle of the open signal is less than a threshold duty cycle.

Abstract: The present invention relates to a method for synthesizing a speech signal; comprising obtaining a speech sequence input signal comprising semantic content corresponding to a speaker's utterance; analyzing the input speech sequence signal to obtain a first sequence of feature vectors for the input speech sequence signal; synthesizing a second sequence of feature vectors different from and based on the first sequence of feature vectors; generating an excitation signal and filtering the excitation signal based on the second sequence of feature vectors to obtain a synthesized speech signal wherein the semantic content is obfuscated.

Abstract: A digital control oscillator circuit includes: a ring oscillator having delay elements delaying a pulse signal; a counter circuit counting the circulation number of the pulse signal; a rough period generation unit acquiring a period setting value as a magnification ratio for a reference clock, and counting the reference clock using an integer part of the ratio to generate a rough period timing; a fraction conversion unit converting a decimal point part of the ratio into the number of the elements passed by the pulse signal to generate a fraction; and an output processing unit selecting a timing when outputs of the ring oscillator and the counter circuit become values corresponding to the fraction as an output timing when a time corresponding to the fraction has passed after the rough period timing, and generating an output signal oscillating at a period represented by the period setting value according to the output timing.

Abstract: An apparatus includes a first conductive path comprising a first set of inductive elements connected in series, a second conductive path comprising a second set of inductive elements connected in series, each inductive element of the second set of inductive elements inductively coupled to, and having a mutual capacitance with, a corresponding inductive element of the first set of inductive elements. In some embodiments, the apparatus further includes a first amplifier having an amplifier input and an amplifier output, the amplifier output electrically connected to a proximal end of the first conductive path or the second conductive path. The described apparatus delays a signal according to the gain of the input amplifier. A method that uses the described apparatus is also disclosed herein.

Abstract: The present invention provides a touch panel controller for controlling even a large touch panel with little EMI. The touch panel controller of the present invention includes a plurality of driving circuits (DC1 through DCm) for driving respective drive lines (DL1 through DLm) of a capacitive touch panel unit 2 by supplying driving signals (Ds) to the respective drive lines (DL1 through DLm), and a rise/fall time of each of the driving signals (Ds) is variable.

Abstract: An adjustable delay line includes a series of delay elements for adjusting the accumulative delay. Each element has a plurality of registers indicating to various devices within the delay element to be ‘on’ or ‘off’, thereby changing the time delay through the element. A master control indicates to the delay line whether to go faster (increment) or go slower (decrement). When one of these control signals is applied to the delay line, it is applied to half the elements, either the odd or the even numbered elements. Only one element will have its state changed by the increment or decrement control signal, and it will be the element for which the previous delay's corresponding element is already set or un-set depending upon the applicable case.

Abstract: Systems and methods for providing a full fail-safe capability in signal transmission networks are disclosed. For example, a system for providing a full fail-safe capability in signal transmission networks includes at least a first electronic circuit to transmit and receive signals or data, at least one driver unit coupled to the at least a first electronic circuit, and at least one receiver unit coupled to the at least a first electronic circuit and the at least one driver unit. The at least one receiver unit includes at least one offset signal generating unit, a signal comparing unit, and a switching unit to couple an offset signal from the at least one offset signal generating unit to an input of the signal comparing unit.

Abstract: An adjustable delay line includes a series of delay elements for adjusting the accumulative delay. Each element has a plurality of registers indicating to various devices within the delay element to be ‘on’ or ‘off’, thereby changing the time delay through the element. A master control indicates to the delay line whether to go faster (increment) or go slower (decrement). When one of these control signals is applied to the delay line, it is applied to half the elements, either the odd or the even numbered elements. Only one element will have its state changed by the increment or decrement control signal, and it will be the element for which the previous delay's corresponding element is already set or un-set depending upon the applicable case.

Abstract: A semiconductor memory device includes a first internal clock generation circuit configured to generate a first internal clock by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device, a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal, a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage, a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal, and a data output circuit configured to output a data in synchronization with the synchronization clock signal.

Abstract: Tuning circuitry may include a controller that is configured to determine a phase difference for a pair of signals generated at different points in a master delay line of a master-slave delay locked loop (DLL) circuit. One of signals of the pair may be communicated through a slave delay line of the master-slave DLL circuit before the phase difference is determined. A programming delay value used to set a phase delay of the slave delay line may be adjusted or tuned based on the phase difference.

Abstract: A device for maintaining synchronization of a plurality of FPGAs which can easily and precisely maintain the synchronization of the plurality of FPGAs in a device in which two or more FPGAs are interactively connected and operated is provided. The device is included in each of the plurality of FPGAs, and includes a trigger signal generator configured to generate an internal trigger signal itself; a trigger multiplexer configured to select one of the internal trigger signal generated by the trigger signal generator and a trigger signal input from the outside; a delay signal generator including a plurality of stages of flip-flops, each of the plurality of stages of flip-flops configured to delay the trigger signal by one clock cycle; and a synchronization multiplexer configured to select and output one of output signals of the plurality of stages of flip-flops of the delay signal generator.

Abstract: Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal.

Abstract: A pulse generator comprising: an input for receiving a trigger; an output node for outputting a signal; a delay line comprising one or more delay units and a plurality of taps; one or more pull-up devices each connected to the output node for increasing the output voltage on the output node; and/or one or more pull-down devices each connected to the output node for decreasing the output voltage on the output node; wherein the taps of the delay line are operably connected to the pull-up and/or pull-down devices such that a trigger passing along the delay line activates one or more of the pull-up and/or one or more of the pull-down devices more than once. Re-use of the pull-up and/or pull-down devices enables longer and more complex pulse shapes, such as high-order Gaussian pulse shapes to be produced while keeping the number of components low, thus reducing chip area, power requirements and parasitic capacitance.

Abstract: An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.

Abstract: Apparatuses and method for controlling delay circuits during an idle state to reduce degradation of an electrical characteristic is disclosed. An example apparatus includes a delay line circuit including a plurality of delay stages, and further includes a delay line control circuit coupled to the delay line circuit. The delay line control circuit is configured to enable delay stages of the plurality of delay stages, and is further configured to control enabled delay stages of the plurality of delay stages to provide a respective output clock signal having a high logic level during an idle state.

Abstract: Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: In an approach for calibrating a delay line having a plurality of taps, a first clock signal is input to the delay line. A second clock signal is input to a reference circuit having a plurality of taps. In response to determining that output signals of selected taps of the delay line and reference circuit do not align, a next tap of the reference circuit is selected, to determine whether or not the output signals align. In response to determining that the output signals align, reference tap data indicative of the current reference tap is stored in association with a delay tap number of the current delay tap. A next tap of the delay line is selected to determine whether or not the output signals align.

Abstract: There is provided a clock generating apparatus for generating a recovered clock by recovering a clock from an edge of a received signal, including a recovered clock generating section that generates the recovered clock, a multi-strobe generating section that generates a plurality of strobes with different phases, in accordance with a pulse of the recovered clock, a detecting section that detects a position of an edge of the received signal relative to the strobes, by referring to values of the received signal obtained at respective timings of the strobes, and an adjusting section that adjusts a phase of the recovered clock, in accordance with the position of the edge of the received signal.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A DLL system in a memory device with wide frequency application includes: a clock receiver that generates a clock for the DLL system; a delay line, coupled to the clock receiver, for receiving the generated clock and delaying the clock according to a received power supply; a power regulator, for generating the power supply to the DLL delay line according to a bias; a control logic, coupled to the clock receiver, for generating a plurality of logic signals respectively corresponding to a plurality of frequency ranges of the clock; and a bias generator, coupled between the control logic and the power regulator, for providing the bias to the power regulator, wherein the value of the bias is according to a logic signal output by the control logic.

Abstract: A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Abstract: Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.

Abstract: Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a delay length, and, in a second mode, to determine an initial delay. The apparatus further including a delay line circuit coupled to the controller and includes delay elements. Each of the delay elements includes delay gates that are the same type of delay gate. The delay line circuit is configured to, in the first mode propagate a signal through one or more of the delay elements to provide a delayed signal. The delay line circuit is further configured to, in the second mode, propagate a pulse signal through one or more of the delay elements and provide a corresponding output signal from each of the one or more delay elements responsive to the pulse signal reaching an output of the corresponding delay element.

Abstract: Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current source and provide a delay that is dependent on the charging current. Each delay element may be a current-starved delay element. The delay element(s) may be coupled in series to implement a delay line or in a loop to implement an oscillator. The bias circuit controls generation of the charging current based on a function of at least one parameter (e.g., a switching threshold voltage) of the at least one delay element in order to reduce variations in delay with temperature. The current source provides the charging current for the delay element(s) and is controlled by the bias circuit.

Abstract: A digital controlled delay line (DCDL) includes a signal gated delay line generating a delayed signal, a phase selector, a controller, an input signal and an output signal. The phase selector includes logic gates to couple the delayed signal from the signal gated delay line to the output signal. Preventing signal propagation to unused cells and logic gates reduces power consumption. The number of logic gates in the phase selector the delayed signal passes through is log2 p, wherein p is the number of the signal gated delay cells in the signal gated delay line and p is a power of 2. The number of logic gates is (integer part of log2 p)+1, wherein p is the number of the signal gated delay cells and p is not a power of 2.

Abstract: Process, voltage and temperature corners of an on-chip device under calibration are obtained by comparing the outputs of different on-chip components such as active on-chip components and passive-on chip components in response to an input. A first on-chip delay line including a number of active devices, which generate an array of outputs D[ ]) at different stages of the delay. A second on-chip delay line generates a single output (CLK). A DFF array samples the array of outputs (D[ ]) with the single output clock CLK. The different delay variations in different process and temperature corners cause different outputs from the DFF array. The different outputs from the DFF array provide information about the process and temperature corner that can be for rapid calibration of the on-chip device under calibration within one cycle of the CLK.

Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

Abstract: In one embodiment a circuit for testing delays is provided. A test signal generator circuit toggles a plurality of output signals 1 through N in sequential order, separating the toggles by a delay period. Each output signal is coupled to an input of a respective one of a plurality of delay circuits. A phase detector circuit is coupled to the delay circuits and is configured to determine the order in which signals output from delay circuits X?1, X, and X+1 are toggled for each delay circuit X. In response to the output signals being toggled in the order X?1 followed by X followed by X+1, the phase comparator circuit is configured to output a first signal indicating correct operation. Otherwise, the phase comparator circuit is configured to output a second signal indicating incorrect operation.

Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.