Abstract: A semiconductor integrated circuit detecting a change in the internal propagation delay and self-compensating such a change. A combination of semiconductor integrated circuits can self-compensate a change in the total propagation delay of the circuit. There is provided a ring oscillator composed of dummy device elements separate from an actually-used logic circuit portion. The oscillating pulses of the ring oscillator are counted relative to a reference pulse signal. The semiconductor integrated circuit has a delay time compensation control circuit block which generates control data used to compensate the change in the propagation delay based on the difference between the first-counted value and a subsequently counted value. In a combination of semiconductor integrated circuits, the delay time compensation control circuit block may be provided for each channel. Alternatively, the delay time compensation control circuit block may be provided for common use by many channels.

Abstract: In a sampling phase controlling apparatus for controlling a phase of a clock signal supplied to a transmission system including a discriminating circuit for discriminating a received signal and an equalizer for removing an intersymbol interference component from the received signal, a first phase control circuit is provided to control the phase of the clock signal in accordance with accumulated intersymbol interference components, and a second phase control circuit is provided to control the phase of the clock signal in accordance with the accumulated intersymbol interference components and a differential value thereof. One of the first and second phase control circuits is selected by a selector circuit.

Abstract: A programmable delay line comprises a plurality of delay stages connected in series, each of the delay stages including: a basic path for passing an input signal; a delay path for passing the input signal with a predetermined delay time; and a selector for selecting either the basic path or the delay path to pass the input signal in accordance with digital data externally inputted, wherein differences in times for passing the input signal through the basic path and through the delay path in the plurality delay stages are UD.2.sup.n (n=0, 1, 2 . . . ), UD being unit delay time. A programmable delay apparatus comprises: an oscillator and counter, which determine a coarse delay time in accordance with the upper bit data of control data, and a programmable delay line, which determines a fine delay time according to the lower bit data of the control data after the finish of the coarse delay time to obtain a total delay time. The counter provides a wide range of available delay times.

Abstract: A memory device for recording a time factor of data includes a threshold element, coupling capacitance, an RC-circuit, and a digital counter. A reference voltage is input to the RC-circuit. The output of the RC-circuit and an input voltage are each input to the coupling capacitance. The output of the coupling capacitance is input to the threshold element. When the voltage received by the threshold element reaches a threshold voltage level, the threshold element generates an output voltage. The digital counter receives the threshold element output voltage and the reference voltage. The digital counter is triggered by the reference voltage to begin counting clock pulses generated by a reference clock. The digital counter is then triggered by the threshold element output voltage to stop counting the clock pulses.

Abstract: A programmable time-intervals generator comprising first and second digital counters, a memory, a digital divider and a digital adder. On the occurrence of a first event, the first counter starts counting, and on the occurrence of a second event, only the most significant bits of the number counted up to then are stored, thereby providing a division by truncation. From the stored number, at least two discrete fractions are obtained by the divider, whereafter said fractions are summed at the adder which operates on strings of bits. The second counter counts down the sum number and, on becoming cleared, generates a signal.