Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.

Abstract: The present invention discloses an electric signal outputting apparatus in a serial electric transmission system. The electric signal outputting apparatus includes a switching part for switchably generating high and low output signals in accordance with signal data and transmitting the output signals to a transmission path, an impedance matching part for matching an output impedance to the impedance of the transmission path, and an auxiliary switching part for subsidiarily supplying current to an output node in the transmission path and subsidiarily absorbing current from the output node in the transmission path when the switching part switches the generation between high and low output signals, wherein the auxiliary switching part conducts the supplying and the absorbing for a period shorter than a pulse width of a reference clock of the serial electric transmission system.

Abstract: An impedance compensation circuit for inputs of a programmable device includes programmable impedance circuits connected with input nodes. The programmable impedance circuits can be configured to apply a compensating voltages to input nodes to reduce or eliminate unwanted offset voltages. An impedance compensation circuit may include resistors in series or current sources in parallel. A set of bypass switches selectively apply each resistor or current source to an input node, thereby changing the offset voltage of the node and compensating for impedance mismatches. Control logic provides signals to control the bypass switches. The control logic may be implemented using programmable device resources, enabling the control logic to be updated and improved after the manufacturing of the device is complete. The control logic can automatically evaluate offset voltages at any time and change compensating impedances accordingly. This reduces manufacturing costs and takes into account temperature and aging effects.

Abstract: A system and method are provided for providing an impedance match of an output buffer to a transmission line without significantly increasing the power consumption of the output buffer. A system and method are also provided for providing an impedance match of an output buffer to a transmission line, while still allowing for an adjustable output swing as is required for loads such as laser transmitters and optical modulators.

Abstract: A circuit for discriminating between complementary first and second input signals. By using a logic gate in parallel with a signal amplifying circuit, the signal amplifying circuit can be disabled when it is no longer required. Once the logic gate is capable of detecting distinct complementary states in the two input signals, the signal amplifying circuit is disabled and the circuit uses one of the input signals as its output signal. The circuit is improved by using a pair of Schmitt inverters so the logic circuit will not vacillate unpredictably when the input signals are in an indeterminate state.

Abstract: A signal transmission circuit, a CMOS semiconductor device, and a circuit board improve the signal transmission characteristic of a signal line having a large capacitance that is generated on the long signal line inside a large-scale integrated circuit when the signal line is long or when many driven circuits are connected to the signal line. The midpoint voltage of the power source voltage of the drive circuit and driven circuit is output. An assist-circuit having low output impedance is then connected to the signal line. The voltage of the signal line is thus held at the midpoint voltage of the power source voltage. At the same time, a drive signal that is output from the driver circuit is excited centered at the midpoint voltage (threshold voltage of the driven circuit) with a small amplitude. The driven circuit is then driven by this drive signal that is restricted to the small amplitude.

Abstract: A polarity detector 100 wherein bistables 105 and 107 selectively sample the sequence of pulses and store samples. The samples and the output signal 125, stored by the bistable 109, are compared by the logic circuit 108. When the stored samples have identical polarity and the polarity of the output signal 125 is not identical to the polarity of the samples, then the polarity of the output signal 125 is changed to the polarity of the samples. However, when the polarity of the samples and that of the output signal 125 are not identical, then the polarity of the output signal 125 remains unchanged. In addition, when the polarity of the stored samples are not identical, the polarity of the output signal 125 remains unchanged. Hence, the polarity of the output signal 125 indicates the polarity of the sequence of pulses 120.

Abstract: A circuit for detecting timing errors and for selecting the correct clock edge for mid-point data sampling, includes a rising edge sampling device for sampling an input data signal at a rising edge of an input clock and generating a first interim data signal. A falling edge sampling device samples the input data signal at a falling edge of the input clock and generates a second interim data signal. An error signal generation devise, arranged in each of the rising edge and falling edge sampling devices, generates an error signal if designated setup time and hold time requirements are not met. The error signal is one of an error-rise or error-fall signal. A state machine receives the first and second interim signals and the error signal. The state machine automatically outputs the first interim data signal to a logic device if the error-fall signal is detected, and outputs the second interim data signal to the logic device if the error-rise signal is detected.

Abstract: An adjustable precision delay circuit includes a series of inverter gates and a multiplexer for selecting any of their outputs or the input to the series. The polarity of the signal input to this circuit is controlled so that any selected output always has the same predetermined polarity, thereby eliminating timing errors arising from factors that vary with the polarity of the output.

Abstract: A measurement circuit in the output circuit of a sensor detects the polarity of a source to which a load is connected. The detection of one of the two polarities establishes one of two states which is stored in a storing element and the correct one of two drivers is switched to the output terminals. This state is maintained for as long as there is no change to the polarity at the output terminals. If the terminals are interchanged, then the measurement circuit correctly restores the stored state, so that the correct driver is associated with the load in each case. If positive instead of negative switching sensors are required, there is no need to replace the equipment. When the voltage is turned on, the equipment is initialized, so that it is set in accordance with the new circumstances.