Abstract: A differential mode converter that includes an input mode converter configured to convert an input voltage in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; and a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage.

Abstract: A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor.

Abstract: Sampling circuits and methods for sampling are provided. In a first operating phase, sampling capacitors are coupled to inputs, and in a second operating phase, to a common-mode signal.

Abstract: Systems and methods for determining a touch input are provided. The systems and methods generally include measuring the peak voltage at an electrode over a measurement period and determining a touch input based on the peak voltage. The systems and methods can conserve computing resources by deferring digital signal processing until after a peak electrode capacitance has been sampled. The systems and methods are suitable for capacitive sensors using self-capacitance and capacitive sensors using mutual capacitance. The systems and methods are also suitable for capacitive buttons, track pads, and touch screens, among other implementations.

Abstract: In some embodiments, a circuit includes: a first chopping circuit configured to receive an input signal and generate a modulated signal responsive to the input signal; first and second input capacitors selectively coupled to receive a modulated signal or a common-mode voltage; an amplifier having an input and an output, the input coupled to the first and second input capacitors; an auto-zeroing circuit comprising one or more auto-zeroing feedback capacitors selectively coupled between the amplifier input and output; a gain selection circuit comprising one or more gain selection feedback capacitors coupled to the amplifier input and selectively coupled to the amplifier output or the common-mode voltage; an offset compensation circuit comprising one or more offset capacitors coupled to the amplifier input and selectively coupled to a reference voltage or the common-mode voltage; and a second chopping circuit configured to generate a demodulated signal responsive to the amplifier output.

Abstract: There is provided a hearing aid with an antenna connected to a transmission and/or reception circuit for transmission and/or reception of the electromagnetic energy via the antenna. A coupling circuit, e.g. including a directional coupler, is configured to sense an electric return power from the antenna, and to generate a power signal based on the sensed electric return power. A controllable impedance circuit is connected to the antenna, so as to allow adjusting of impedance of the antenna in at least two different steps. A processor is configured to generate a tuning control signal to the controllable impedance circuit in response to the power signal. This allows control of the impedance of the antenna for minimizing impedance mismatch, and thus improve performance of the antenna by tuning the impedance to the operating conditions of the antenna, preferably in an automatic manner.

Abstract: A power domain isolation system, such as without requiring a transformer, can include a reactive circuit, an input network having first and second input nodes that are coupled in parallel with the reactive circuit via respective first and second current control circuits, and an output network having first and second output nodes that are coupled in parallel with the reactive circuit via respective third and fourth current control circuits. The first and second current control circuits can be configured to couple the reactive circuit to the input nodes when the third and fourth current control circuits are configured to electrically isolate the reactive circuit from the output nodes, and the first and second current control circuits can be configured to electrically isolate the reactive circuit from the input nodes when the third and fourth current control circuits are configured to couple the reactive circuit to the output nodes.

Abstract: This application relates to circuitry for monitoring for instability of an amplifier. The amplifier (100) has a first signal path between an amplifier input (INN) and an amplifier output (VOUT) and a feedback path from the output to form a feedback loop with at least part of the first signal path. A comparator (212) has a first input configured to receive a first signal (INN) derived from a first amplifier node which is part of said feedback loop and a second input configured to receive a second signal (INP) derived from a second amplifier node which varies with the signal at the amplifier input but does not form part of said feedback loop. The comparator is configured to compare the first signal to the second signal and generate a comparison signal (COMP), wherein in the event of amplifier instability the comparison signal comprises a characteristic indicative of amplifier instability.

Abstract: Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

Abstract: In one embodiment, a spread spectrum clock generator, comprising a digital delta sigma modulator coupled to a fractional N, phase locked loop (PLL), the PLL comprising a discrete-time capacitance multiplier loop filter, the discrete-time capacitance multiplier loop filter comprising: an amplifier comprising a non-inverting input and an inverting input; a first switched capacitor resistor and a capacitor coupled to the non-inverting input, the capacitor coupled between the first switched capacitor resistor and the non-inverting input; and a second switched capacitor resistor coupled to the inverting input.

Abstract: A method of operating switched capacitor filter integration circuits by pre-charging a final filter capacitor thereof with the final full voltage gain value during a first subframe to obtain an enhanced signal to noise ratio without changes to the circuit or components thereof.

Abstract: An input buffer circuit includes an input differential amplifier unit, a differential amplifier stage, and a buffer. The input differential amplifier unit has input terminals and at least one output terminal, wherein at least two of the input terminals of the input differential amplifier unit are configured to be capacitively coupled respectively so as to provide at least one pair of signal paths for a first input signal and a second input signal of a differential input signal. The differential amplifier stage, coupled to the input differential amplifier unit, has first and second differential input terminals, and a corresponding output terminal, wherein the first and second differential input terminals are capable of being coupled to the first input signal and the second input signal respectively. The buffer, coupled to the output terminal of the differential amplifier stage, is used for outputting an output single-ended signal.

Abstract: Disclosed is a resonant circuit and method for matched clock and data timing performance for improving timing closure of digital circuits on advanced semiconductor manufacturing processes. The matched resonance circuit comprises pulse generator circuit (202) and plurality of generating latches (206A-N) and plurality of sampling latches (304A-N). The pulse generator circuit (202) comprises plurality of inverters (210A-N), optimum resistance (214) and exclusive OR (Ex-OR) gate (218) which are connected in series and a matched capacitance. The pulse generator circuit (202) generates timing pulse output using one or more buffers and clock inductor. Each generating latch receives clock timing pulse output as timing pulse into plurality of sampling flip-flop latches (304A-N) through clock sample path (CS) to match arrival of timing pulse and outputs of plurality of input data lines that are resonated by connecting one or more of respective load capacitances with at least one shared inductor (208).

Abstract: There is described an apparatus for measuring a capacitance formed by a sense plate and a counter plate, wherein the sense plate comprises a first sub-plate and a second sub-plate, the first sub-plate and the second sub-plate being electrically separated.

Abstract: A control circuit, of a control loop, for a lighting driver. The lighting driver is adapted to controllably connect an electronic ballast to an LED light source or lamp. The control circuit comprises a biasing circuit having an adjustable impedance. A tuning circuit adjusts the impedance of the biasing circuit so as to tune a parameter of a frequency response of the control loop and thereby of the lighting driver.

Abstract: A signal processing circuit that achieves functionality similar to that of a switched capacitor circuit without the necessity a clock. The circuit compensates for finite open loop gain and for offset voltages in the components, allowing the circuit to “calculate” the result of a problem represented by the circuit essentially immediately upon the presentation of a new input or set of inputs. After the circuit is initialized to remove gain, an input is applied to the circuit, and propagates through the network and affects the state of amplifier outputs; the propagation from the input through capacitors to the ultimate output(s) of the circuit is the analog calculation taking place. The calculation is not mediated by a clock, but rather the calculation corresponds to the circuit's one-time response to the application of the inputs. Using these techniques complex signal processing circuits and even analog neural networks may be constructed.

Abstract: Apparatuses and methods of converting a capacitance measured on a sense element to a digital value are described. One apparatus includes a modulator having a modulator capacitor, a sense element selectively coupled in a feedback loop of the modulator to operate as a switching capacitor. The apparatus also includes a first switch coupled between a voltage source and a first node of the switching capacitor and a second switch coupled between the first node of the switching capacitor and a first node of the modulator capacitor. The switching capacitor provides a charge current to the modulator capacitor via the second switch. The modulator measures a capacitance of the sense element and converts the measured capacitance to a digital code representing the capacitance.

Abstract: Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.

Abstract: A switched-capacitor analog-to-digital converter (ADC) includes: a main digital-to-analog converter (DAC) circuit; a comparator coupled to the main DAC circuit and configured to determine whether the input to the comparator exceeds a pre-determined threshold; and a supplementary DAC circuit coupled to the main DAC circuit, wherein the switched-capacitor ADC is configured to operate in at least one of a first mode or a second mode, wherein in the first mode for measuring an offset of the switched-capacitor ADC, the supplementary DAC circuit is configured to shift a voltage at an output of the main DAC circuit by a first value having a first polarity, and wherein in the second mode for measuring a full-scale gain error of the switched-capacitor ADC, the supplementary DAC circuit is configured to shift the voltage at the output of the main DAC circuit by a second value having a second polarity opposite the first polarity.

Abstract: According to an embodiment, a sample-hold circuit according to this embodiment is made up of a first device having a first withstand voltage and a second device having a second withstand voltage lower than the first withstand voltage. The sample-hold circuit includes a first switch element, a first capacitor, a second switch element, a third switch element, and a fourth switch element. The first switch element has the first withstand voltage. The first switch element operates upon receiving a first signal output from the device having the first withstand voltage. The second switch element has the first withstand voltage. The third switch element has the second withstand voltage. The fourth switch element has the second withstand voltage.

Abstract: An analog to digital converter is disclosed that is designed to receive a differential analog signal and includes a signal chopping circuit and a successive approximation register (SAR) coupled to the signal chopping circuit. The signal chopping circuit is designed to invert a polarity of the differential analog signal and includes a first switching circuit having a first transistor and a second switching circuit having a second transistor. A gate of the first transistor and a gate of the second transistor is each coupled to a same bootstrap capacitor. Coupling both switching circuits to the same bootstrap capacitor (as opposed to separate bootstrap capacitors) greatly frees up space on the die or chip.

Abstract: An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).

Abstract: Embodiments of switched capacitor voltage converters and methods for operating a switched capacitor voltage converter are disclosed. In an embodiment, a switched capacitor voltage converter includes serially connected switching devices, a voltage generator connected to the serially connected switching devices and configured to generate driver voltages in response to a first voltage at a first terminal that is connected to the serially connected switching devices, and voltage drivers configured to drive the serially connected switching devices based on the driver voltages.

Abstract: A signal acquisition or conditioning amplifier can be configured and controlled to use correlated doubling sampling (CDS) of a differential input signal, and a storage capacitor in a capacitive or other feedback network, a low power operational transconductance amplifier (OTA) capable of being powered down between CDS samplings, and which can be operated in a manner that provides good performance characteristics while still providing low or efficient power consumption. The amplifier and other signal processing circuitry can allow power to be scaled down, when less signal measurement throughput is needed, and to be scaled up, when more signal measurement throughput is needed. Such flexibility can help make the present approach useful for a wide range of signal acquisition and measurement applications. Precharging via buffer amplifiers can provide improved signal acquisition circuitry effective input impedance.

Abstract: A filtering method and a filter are disclosed. The method includes integrating values of an input signal by an integrator comprising a memory; storing an integration value in the memory; cyclically resetting the memory after integrating a first predefined number of values of the input signal; in a steady operating mode, generating a value of an output signal based on the integration value stored in the memory each time after integrating the first predefined number of values of the input signal; and in an initial operating mode, generating an initial value of the output signal based on the integration value stored in the memory after integrating a second predefined number of values of the input signal, wherein the second predefined number is smaller than the first predefined number.

Abstract: A method for dynamic calibration of current sense for switching converters includes biasing a reference transistor with a Zero Temperature Coefficient current source, and a respective gate of each of the reference transistor and a power transistor with a gate voltage. The reference transistor and the power transistor each comprise a matching temperature coefficient. A reference voltage sensed across the reference transistor is multiplied by a gain, thereby generating a first calibration voltage, wherein the gain is determined by a gain coefficient. A transistor voltage sensed across the power transistor is multiplied by the gain, thereby generating a second calibration voltage. The first calibration voltage is compared to a target voltage to generate an error voltage. The gain coefficient is determined with an Analog to Digital Converter in response to the error voltage, thereby minimizing a difference between the target voltage and each of the calibration voltages.

Abstract: A sampling device includes a switch capacitor circuit. First ends of two switches are respectively connected to an input signal. Second end of the first switch is connected to an upper plate of a first capacitor. Second end of the second switch is connected to a lower plate of a second capacitor. A connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source. The first ends of a third switch and a fourth switch are respectively connected to an input common-mode voltage. A second end of the third switch is connected to the upper plate of the first capacitor. A second end of the fourth switch is connected to the lower plate of the second capacitor. The connection node is connected to the power source. Thus, an output common-mode voltage of the sampling device is adjustable.

Abstract: A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements.

Abstract: An integrated circuit (IC) is provided with a plurality of diode based mm-wave peak voltage detectors (PVD)s. During a testing phase, a multi-point low frequency calibration test is performed on one or more of the PVDs to determine and store a set of alternating current (AC) coefficients. During operation of the IC, a current-voltage sweep is performed on a selected one of the PVDs to determine a process and temperature direct current (DC) coefficient. A peak voltage produced by the PVD in response to a high frequency radio frequency (RF) signal is measured to produce a first measured voltage. An approximate power of the RF signal is calculated by adjusting the first measured voltage using the DC coefficient and the AC coefficient.

Abstract: A termination circuit is provided. The termination device includes terminals configured to receive a corresponding signal; unit circuits respectively connected to the terminals, the unit circuits each including a unit resistor and a unit switch element connected to each other in series; common mode capacitors; first switch elements respectively connected between each of the unit circuits and a first corresponding common mode capacitor of common mode capacitors, each of the first switch elements being configured to turn on when the corresponding signal is received in a first mode; and second switch elements respectively connected between each of the unit circuits and a second corresponding common mode capacitor of the common mode capacitors, the second switch elements being configured to turn on when the corresponding signal is received in a second mode different from the first mode.

Abstract: A transmitter for establishing communication between a device and a differential network bus includes current driving means connected to each of the two conduction lines of the differential network bus, through a first and second conduction paths of the transmitter; at least one unidirectional current regulator for extracting a first current equal to a known ratio of a parasitic current circulating through the first conduction path, with a direction inverse to the driving current through the conduction path connected to one of the lines of the differential bus; means for obtaining, from the first current, a second current with a magnitude equal to the original magnitude of the parasitic current; and means for introducing the second current into the second conduction path connected to the other line of the differential bus.

Abstract: An apparatus is described. The apparatus includes a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage.

Abstract: An attenuator for attenuating a signal is disclosed. The attenuator comprises a differential input port with a positive input node and a negative input node to receive the signal; and a differential output port with a positive output node and a negative output node to output the attenuated signal. The attenuator further comprises a first switched resistor network connected between the positive input node and the positive output node; and a second switched resistor network connected between the negative input node and the negative output node. Further a pair of compensation paths is connected to the first and second switched resistor networks for cancellation their parasitic leakages, where a first compensation path is connected between the positive input node and the negative output node, and a second compensation path is connected between the negative input node and the positive output node.

Abstract: A delta-sigma modulator and a delta-sigma converter include an analog amplifying unit to amplify an analog signal and having at least a primary feedback coefficient, a quantizer to quantize an output signal of the analog amplifying unit, a DA converter to perform DA conversion on output of the quantizer and output a feedback signal, an adder-subtractor to input into the analog amplifying unit an analog signal obtained by subtracting the feedback signal from an analog signal input therein, a reset circuit to reset the analog amplifying unit at predetermined periods, and a control circuit to control the analog amplifying unit so that the analog amplifying unit operates as an integrator with the primary feedback coefficient of 1 until a predetermined period elapses after the reset circuit resets the analog amplifying unit and as an amplifier with the primary feedback coefficient of greater than one after the predetermined period has elapsed.

Abstract: In order to eliminate influence of a noise voltage applied to a diaphragm of a capacitance type sensor, the capacitance type sensor includes: a detection capacitor formed of a diaphragm and a fixed electrode, the diaphragm being connected to a frame and deformed by receiving an external force; and a fixed capacitor connected in series with the detection capacitor, so that it is intended to detect a divided voltage applied to the detection capacitor by applying a voltage to the detection capacitor and the fixed capacitor, and further includes: a noise voltage generating part connected to the frame and adapted to generate a noise voltage caused in the frame; a noise voltage adding part adapted to add the noise voltage to the voltage applied to each of the capacitors; and a noise voltage subtraction part adapted to subtract the added noise voltage from a divided voltage of the detection capacitor.

Abstract: An integrated circuit is described. The integrated circuit comprises a first portion having programmable resources; a second portion having hardened circuits including an analog-to-digital converter circuit configured to receive an input signal and generate an output signal; and a monitor circuit configured to receive an output signal generated by the analog-to-digital converter circuit; wherein the monitor circuit is configurable to control a calibration of the analog-to-digital converter circuit based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

Abstract: Systems and methods for dimming control using TRIAC dimmers are provided. An example apparatus for a power conversion system includes: a process-and-drive component configured to receive an input signal and output a drive signal to a switch to affect a current that flows through a primary winding of a power conversion system. The input signal includes a first pulse associated with a first input period and a second pulse associated with a second input period. The drive signal is associated with a first modulation period for the first input period and a second modulation period for the second input period. The process-and-drive component is further configured to: determine the first modulation period for the first input period; change the drive signal between a first logic level and a second logic level at a modulation frequency during the first modulation period; determine the second modulation period for the second input period.

Abstract: A correlated double sampling (CDS) circuit includes a comparator and a first circuit. The comparator including, a first input terminal, a second input terminal, at least one output terminal, and a plurality of first transistors operably coupled between the at least one output terminal and the first and second input terminals. The first circuit includes at least one second transistor, the at least one second transistor operably coupled to the at least one output terminal and one of the first input terminal and the second input terminal, the at least one second transistor having at least one of (i) a different number of layers than the first transistors, and (ii) a different dimension than the first transistors.

Abstract: An amplifier includes an output stage circuit and a compensation circuit. The output stage circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The compensation circuit includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor is coupled between the first input terminal and the second output terminal, and is configured to operate as a first Miller capacitor. The second capacitor is coupled between the second input terminal and the first output terminal, and is configured to operate as a second Miller capacitor. The third capacitor and the fourth capacitor are configured to alternately operate as the first Miller capacitor and the second Miller capacitor according to at least one clock signal.

Abstract: A correlated double sampling integrating circuit is provided. The circuit includes: a sampling and holding module, an energy storage unit and a feedback module. The sampling and holding module is configured to perform sampling and holding for different input signals. The energy storage unit is configured to store charges corresponding to the input signals upon the sampling and holding to generate node signals, and the feedback module is configured to form a negative feedback loop with the energy storage unit to control node signals at an integrating stage to keep consistent with node signals at a resetting stage and prevent output jump of the correlated double sampling integrating circuit. The correlated double sampling integrating circuit reduces noise, and prevents or weakens output jump of the correlated double sampling integrating circuit caused by the increase of the count of integrations.

Abstract: A voltage reference generator comprises a voltage reference, a variable gain amplifier connected to an output terminal of the voltage reference, a sampling capacitor connected to an output terminal of the voltage reference generator and to an output terminal of the variable gain amplifier via a sampling switch. The switch is adapted to close during a first portion of a switching period, and open during a second portion of the switching period. The voltage reference generator also comprises a ripple monitor adapted to estimate a magnitude of variation of an output voltage of the voltage reference generator resulting from charging and discharging of the sampling capacitor, and based on the estimate, perform one of control of the sampling switch to reduce a switching frequency of the sampling switch to increase a magnitude of the variation of the output voltage, and control of the sampling switch to increase the switching frequency.

Abstract: In a power converter, each gate-driving circuit uses charge from a selected pump capacitor operate a corresponding switch. The switches transitions between different states, each of which corresponds to a particular interconnection of pump capacitors. During clocked operations, the first switch closes, thereby establishing a connection with the first pump capacitor. Prior to the first switch closing, the second switch closes.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may comprise an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Abstract: The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.

Abstract: Bias circuit and a bias generator circuit comprising such a bias circuit. The bias circuit (10, 11) comprises a switched capacitor resistor circuitry (C1, C2, M12-M17), and an operational amplifier (M1-M4, M10) with an input differential transistor pair (M1, M2). The bias circuit further comprises additional source follower transistors (M5, M6) associated with the first and second input differential transistors (M1, M2).The bias generator circuit has a PMOS switched capacitor reference circuit (11) and a NMOS switched capacitor reference circuit (10) and a transconductor reference cell (15). The transconductor reference cell (15) is a replica of a basic reference cell used in a further circuit.

Abstract: An amplifier includes a supply voltage terminal and a reference voltage terminal and an input terminal. An amplifier arrangement includes a first and second branch coupled between the supply and reference voltage terminals, and one or more transistors configured to provide current flow through each of the branches based on the input signal at the input terminal. A first output terminal is coupled to the first branch to provide a first output signal based on the current flow therethrough. A second output terminal is coupled to the second branch to provide a second output signal based on the current flow therethrough. An impedance-modifying circuit is coupled to the second output terminal to provide a voltage variation in the second output signal in response to the input signal greater than a voltage variation in the first output signal in response to the input signal.

Abstract: The present subject matter relates to devices, systems, and methods for controlling an array of two-state elements that can be independently positioned in either first state or a second state. A non-volatile memory in communication with the plurality of two-state elements is configured to receive an input digital control word that addresses a location within the non-volatile memory and to output one of a plurality of array control words stored at the location addressed within the memory to the plurality of two-state elements, wherein the array control word sets a predetermined combination of the plurality of two-state elements to be in the first state and in the second state, and wherein the predetermined combination of the plurality of two-state elements in the first state and in the second state optimally achieves a desired behavior of the array corresponding to the input digital control word.

Abstract: A circuit comprises an amplifier, a first switch arranged between an amplifier input and an amplifier output, a first capacitor, a first resistor, a second switch, a third switch, a first converter coupled to the first amplifier output, a register storing a last digital value, a second converter converting the stored last digital value into a corresponding voltage value, and a control circuit. The control circuit charges the first capacitor to the corresponding voltage value by coupling a second converter output to a second capacitor terminal and switching on the first switch, or by coupling the second converter output to the first capacitor terminal and switching on the third switch; switches on the first switch and the second switch for providing the input voltage signal to the first capacitor; and switches on the third switch for determining a subsequent digital value of the converted output amplifier signal.

Abstract: An apparatus is described. The apparatus includes a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage.

Abstract: An amplifier circuit a differential input stage coupled to a first input and to a second input between which a differential input voltage is present. A converter stage is coupled to the input stage to convert the differential input voltage into a converted voltage. An output stage is coupled to the converter stage and generates, starting from the converted voltage, an output voltage on a single output of the amplifier circuit. A biasing stage is coupled to the input stage and to the output stage to supply a biasing current. A chopper module reduces a contribution of offset and noise associated with the output voltage. The chopper module is coupled to the input stage, converter stage, and to the biasing stage. The chopper module includes an input chopper stage, a converter chopper stage, and a biasing chopper stage that operate jointly under control of a chopper signal.