Abstract: An example log power detector includes a gain or attenuation circuit and a detector circuit. The gain or attenuation circuit includes a plurality of gain or attenuation elements arranged in a sequence, each gain or attenuation element configured to generate an output signal that is an amplified or attenuated version of an input signal provided thereto. The detector circuit includes a plurality of detectors, each detector configured to receive the output signal from a different one of the gain or attenuation elements and to generate a signal indicative of a power of the received output signal. At least the last detector is configured to receive a DC offset signal that is different from a DC offset signal received by at least one other detector. Such a log detector may provide effective noise compensation to reduce errors caused by input noise, especially for low-power and/or high-frequency input signals.

Abstract: Distributed amplifier systems and methods are disclosed. An example distributed amplifier system includes first stage traveling wave amplifier (TWA) circuitry that is controllable to provide one of a first set of discrete gain settings. The first stage TWA circuitry includes a first input transmission line, a first output transmission line, and a first plurality of amplifiers coupled antiparallel between the first input transmission line and the first output transmission line. The first set of discrete gain settings has approximately constant logarithmic spacing.

Abstract: Disclosed herein are power detectors and methods for detecting the average power level of an RF input signal and the voltage envelope of the RF input signal. Also disclosed herein are linear envelope detectors and methods for detecting the voltage envelope of an RF input signal.

Abstract: An apparatus includes multiple field effect transistors and multiple wires. An input wire may be configured to transfer an input signal along an axis. The field effect transistors may be configured to generate a pair of intermediate signals by amplifying the input signal. Multiple gates of the field effect transistors may be configured to receive the input signal. A topology of the gates may be rotated to be perpendicular to the axis. The field effect transistors may be located in two rows mirrored about the axis. Intermediate wires may be configured to transfer the intermediate signals parallel to the axis. A collection wire may be configured to transfer the intermediate signals toward each other and generate an output signal by combining the intermediate signals. An output wire may be configured to transfer the output signal parallel to the axis and away from the field effect transistors.

Abstract: The disclosure concerns a tunable logarithmic detector amplifier (TLDA) system where dynamic tuning functionality is applied to resonant circuits used for feedback control as well as applying tuning to the amplifier. Control signals for the tuning function are generated from the baseband processor. The control of the amplifier tuning and resonator tuning can be performed from information derived from baseband where metrics such as SNR, SINR or CQI are used to optimize system performance. Bandwidth and sensitivity of the receiver are key specifications targeted for optimization using this technique. This technique can be implemented in designs where a wide bandwidth is required.

Abstract: Video equalization including performing equalization such that a sequence of images have dynamic range (optionally other characteristics) that is constant to a predetermined degree, where the input video includes high and standard dynamic range videos and images from both. Equalization is performed with a common anchor point (e.g., 20% gray level, or log mean of luminance) input video and the equalized video, and such that the images determined by the equalized video have at least substantially the same average luminance as images determined by the input video. Other aspects are systems (e.g., display systems and video delivery systems) configured to perform embodiments of the equalization method.

Abstract: The present invention relates to a transponder, which comprises an antenna and a multi-stage rectifier. The antenna is connected to an input of the multi-stage rectifier having m rectifier stages, and a shunt limiter is connected to an output of the rectifier and connected to an nth stage of the multi-stage rectifier, wherein n<m.

Abstract: A logarithmic amplifier produces a logarithmic output signal as a function of an input signal. The amplifier comprises a reference signal, first and second function generators, and a low-pass filter. The first function generator produces a periodic exponential waveform from the reference signal based upon a resistor-capacitor time constant, wherein the exponential waveform exponentially increases from a minimum to a maximum in each period. The second function generator produces a pulsed waveform from the exponential waveform, wherein the pulsed waveform comprises a first portion having a first amplitude for a first time period and a second portion having a different amplitude for the remainder of the signal period, and wherein the duration of the first time period is determined in response to the exponential waveform. The low pass filter produces the logarithmic output signal as a function of the pulsed waveform.

Abstract: A received signal strength indicator according to an aspect of the invention may include a gain calibration section including a calibration limiter, a calibration load unit and a comparison and adjustment unit. The calibration load unit is connected to output terminals of the calibration limiter, and generating an output differential voltage whose gain is a unit gain when a predetermined input differential voltage is input to the calibration limiter, and a comparison and adjustment unit comparing the input differential voltage with the output differential voltage, and adjusting an output of a variable current source included in the calibration limiter so that the input differential voltage becomes identical to the output differential voltage.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A geometric ladder circuit produces a transfer function having substantially uniform steps measured in dB. Where the ladder has a plurality of substantially identical resistor rungs of a first resistance, one stile that is a conductor connecting the rungs, and another having a series of substantially identical resistors of a second resistance, then for identical currents injected at different rungs, the output signal at an end of the ladder is attenuated by a number of substantially equal steps, one for each rung between input and output. For a ladder with a base rung R, an output at an end opposite the base rung, stile resistors of resistance ?R, and other rungs all of resistance (1+(1/?))R, the step size is 20 log10(1+?).

Abstract: A logarithmic amplifier is configured to produce a logarithmic output signal that is an logarithmic function of an input signal. The amplifier comprises a reference signal, first and second function generators, and a low-pass filter. The first function generator is configured to produce a periodic exponential waveform from the reference signal based upon a resistor-capacitor time constant, wherein the exponential waveform exponentially increases from a minimum value to a maximum value in each period. The second function generator is configured to produce a pulsed waveform from the exponential waveform, wherein the pulsed waveform has a signal period, and wherein the pulsed waveform comprises a first portion having a first amplitude for a first time period and a second portion having a different amplitude for the remainder of the signal period, and wherein the duration of the first time period is determined in response to the exponential waveform.

Abstract: Embodiments of the invention are generally directed to a high-speed differential energy difference integrator (EDI) for adaptive equalizers. In an embodiment, the EDI includes two differential full-wave rectifiers providing differential outputs that are cross-coupled to the inputs of an integration capacitor. In one embodiment, the active areas of the transistors of the differential full-wave rectifiers are substantially the same.

Abstract: A mixer capable of detecting or controlling a common mode voltage thereof, includes at least: a mixing module for mixing a first set of differential signals and a second set of differential signals to generate at least one mixed signal; and a compensation module for compensating at least one operation point of the mixing module.

Abstract: A wireless communication system uses a transmission power detection circuit. The transmission power detection circuit has excellent linearity of detection output for transmission output power and can obtain detection output not having temperature dependence. The transmission power detection circuit has a rectifying detection part that includes plural amplifiers connected in series and obtains detection output by taking out rectified outputs from emitters of input transistors of amplifiers of individual stages and synthesizing them. A compensation voltage generating circuit has a dummy amplifier having a construction similar to the amplifiers constituting the rectifying detection part and a coefficient circuit that changes output of the dummy amplifier at a specified ratio, and generates voltage for compensating temperature characteristics.

Abstract: A geometric ladder circuit produces a transfer function having substantially uniform steps measured in dB. Where the ladder has a plurality of substantially identical resistor rungs of a first resistance, one stile that is a conductor connecting the rungs, and another having a series of substantially identical resistors of a second resistance, then for identical currents injected at different rungs, the output signal at an end of the ladder is attenuated by a number of substantially equal steps, one for each rung between input and output. For a ladder with a base rung R, an output at an end opposite the base rung, stile resistors of resistance ?R, and other rungs all of resistance (1+(1/?))R, the step size is 20 log10 (1+?).

Abstract: One embodiment of the present invention is directed to an apparatus for reducing errors affecting the intercept of a logarithmic device, the apparatus including a first switching device coupled to an input of the logarithmic device. The first switching device for switches the input of the logarithmic device between an input signal and a reference signal. The apparatus further includes a polarity switching device coupled to an output of the logarithmic device. The polarity switching device is configured to switch the polarity of an output signal of the logarithmic device when the logarithmic device is receiving one of the input signal and the reference signal. The apparatus further includes a low pass filter coupled to the polarity switching device.

Abstract: A logarithmic amplifier is compensated by a feedback loop. The feedback loop may control a series of detector cells in response to an output from one or more of the detector cells. The feedback loop may be used to provide frequency compensation to the log amp by adjusting the bias currents to the detector cells. One detector cell may be arranged to generate a limiting signal while another detector cell is arranged to generate a zero signal. By arranging the feedback loop to adjust the bias cell so as to maintain the difference between the limit signal and the zero signal at a constant value, the output swing of the detector cells is held constant, thereby stabilizing the slope of the log amp.

Abstract: A signal waveform detection circuit includes an amplifier circuit and a comparing circuit. The amplifier circuit has differential amplifiers connected in series. Each of the differential amplifiers has a common connection point. The comparing circuit is connected to the common connection points of the amplifier circuit. The comparing circuit includes comparing units connected to one of the differential amplifiers. Each of the comparing units has a threshold voltage generating circuit for generating signals. Each signal has a threshold voltage that is set between a maximum threshold voltage of a signal output from the corresponding differential amplifier during a maximum amplitude output and a minimum threshold voltage of a signal output from the corresponding differential amplifier during a minimum amplitude output. The comparing unit further has a comparator comparing a voltage at the common connection point with the threshold voltage.

Abstract: A demodulating logarithmic amplifier rectifies a radio frequency signal prior to amplification through progressive stages. A full wave linear or squaring rectifier receives a waveform signal at the input and provides a rectified signal that is proportional to an envelope or a square of the envelope of the waveform signal at the output. The rectified signal is then fed to a series of limiting amplifier stages where the signal is progressively amplified. After each individual amplifier stage, the partially amplified signal is passed through a voltage-to-current converter to create a current signal. All the current signals are subsequently summed to produce an amplified current output signal that is representative of the logarithm of the envelope of the input signal.

Abstract: A conversionless direct detection system for detecting signals having a very large dynamic range, with a virtually unlimited bandwidth utilizes a successive detection approach having successive log amplifier gain stages, with each gain stage involving simultaneous use of an RF transistor to perform both limiting and logging functions. FET transistors are used to extend the operating range beyond 200 GHz, with the self-bias in combination with a drain resistor limiting voltage and current swings. A log video output is tapped off the source resistor and is coupled to a buffering stage, with the outputs of the buffering stage summed to accommodate very large dynamic range swings of the input voltage, with successive stages saturating at different points to operate at different and contiguous regions, thus to provide the wide dynamic range. The limited RF signal is tapped off the drain resistor, with the stages connected in series to provide the limited RF output as the output of the last stage.

Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract: A voltage controlled low pass filter comprising first and second circuits connected in series between a filter input and a filter output and a third circuit for adding a DC bias voltage to the filter input with AC signals to be filtered. The first circuit has a gain inversely related to the DC bias voltage and is operative to convert any signal applied to the filter input into a first circuit output signal which is a logarithmic function of the applied signal. The second circuit has a gain directly related to the DC bias voltage such that the overall gain of the first and second circuits is unity. The second circuit also has a bandwidth which is inversely related to the gain of the second circuit, and is operative to convert the first circuit output signal into a signal at the filter output which is an exponential function of the first circuit output signal.

Abstract: A parallel-summation logarithmic amplifier is described that uses a novel topology of cascaded and parallel amplifiers to achieve extremely high bandwidth. Included in the topology is a unique delay matching scheme for logarithmic amplifiers that is amenable to fabrication in integrated circuit form. The result is flat group delay over broad frequency ranges and different power levels. The resulting log amplifier is suitable for radar applications and for use in high data rate fiber-optic networks. Also described is a unique design process that yields a set of amplifier gains that closely approximate a logarithm. Also described is the novel idea of using a parallel feedback amplifier (PFA) in piecewise-approximate logarithmic amplifiers. This innovation allows for the design of broadband amplifiers with significantly different gains and similar phase characteristics, which is extremely useful when designing high-frequency logarithmic amplifiers.

Abstract: A signal strength detecting device includes a logarithmic amplifier and an amplitude detector. A constant current source whose current is proportional to the absolute temperature is used as a current source for biasing the logarithmic amplifier. In contrast, a constant current source whose current is not proportional to the absolute temperature is used as a current source for biasing the amplitude detector. This makes it possible to solve a problem of a conventional signal strength detecting device of being unable to detect the signal strength of a received signal correctly because it employs a constant current source whose current is proportional to the absolute temperature as the current source for biasing the amplitude detector, and hence the collector current output from differential amplifiers constituting the amplitude detector can vary in response to the absolute temperature even if the signal strength of the received signal is kept constant.

Abstract: A precision-controlled logarithmic amplifier having reduced interference parameters. In an embodiment, the invention comprises a logarithmic amplifier having an output signal providing a logarithmic representation of an input signal. A precision-control circuit is coupled to the logarithmic amplifier. The precision-control circuit produces a bias and a saturation current that act to reduce the effects of bias and saturation currents that are produced in the logarithmic amplifier and affect the output signal of the logarithmic amplifier.

Abstract: An improved logarithmic amplifier (100) and method in which a signal at an output (106) is logarithmic with respect to the voltage supplied at a gain control input (102). The logarithmic amplifier (100) includes a first amplifier stage (110) and a second amplifier stage (130) which are coupled together by a current mirror stage (120). Alternative embodiments of logarithmic amplifier (200) and (300) include different biasing methods for biasing the second amplifier stage (130).

Abstract: A logarithmically controlled attenuator circuit includes a resistive attenuator having a single series resistive element connected between an input conductor and an output conductor, and a plurality of parallel resistive elements each having a first terminal connected to the output conductor. A plurality of switching elements controllably couple the parallel resistive elements, respectively, between the output conductor and a first reference voltage conductor. A control circuit produces successive gradually increasing and then leveling off analog control signals on the control terminals of successive switching elements, respectively. A programmable implementation includes a first group of parallel resistive elements (Q1,3,5 . . . ) each having a first terminal connected to the output conductor (12), and a second group of parallel resistive elements (Q2,4,6 . . . ) each having a first terminal connected to the output conductor (12).

Abstract: A logarithmic amplifier is provided with a calibration circuit to allow for current measurement over a wide-dynamic range that includes extremely low current levels in a manner which mitigates or eliminates sensitivity to temperature. Calibration currents are generated by application of a series of voltage ramps of selectable slope to a capacitor. This provides a set of known current levels, selectable over a range of decades, for periodic calibration of the logarithmic amplifier. The selectable calibration currents can also be advantageously used to provide a fixed, known bias current to the input of the logarithmic amplifier to improve the response time of the amplifier for measurement of small sensor currents on the order of 10-100 fA.

Abstract: A logarithmic attenuator circuit includes a resistive attenuator in which the series resistors are P-channel MOSFETs with gate electrodes connected to V.sub.DD and the parallel resistors are P-channel MOSFETs which also function as switches. A control circuit (8B) produces a plurality of successive control signals (V1,2 . . . 10) on the gate electrodes of the successive MOSFETs which functions as switches in response to a gain control signal (V.sub.

Abstract: A logarithmic level detector that provides a very accurate level detector output signal that is greatly insensitive to temperature and process spread. The logarithmic level detector includes a weighted summed reference circuit which is subtracted from a level output signal of the cascade of limiting amplifiers so as to form a relative level detector output signal, and further compensation circuitry at input and output side, and an overall gain stabilizing circuit.

Abstract: A logarithmic conversion circuit includes a narrow band generating unit consisting of a local oscillator (104) and a mixer (103) for receiving an output of the local oscillator and the input signal and a first band-pass filter (105) connected to the mixer for generating a narrow band signal from a broad band input signal; a selection member (106-7) directly connected to the first band-pass filter for selecting either the input signal or the narrow band signal; first and second LOG amps (108, 111) connected in series to the selection member; and a noise suppression unit connected in parallel between the first and second LOG amps and including a second band-pass filter (109) for transmitting only the broad band input signal and a low-pass filter (110) for transmitting only the narrow band signal.

Abstract: The present invention concerns a method and apparatus that generally prevents a glitch from occurring in an output of a sense amplifier during a transition from a strong zero to a weak zero. The present invention detects the voltage difference between a virtual ground node and a read product term line and turns off a pull down of a first stage of the sense amplifier. The low on the read product term line generally causes a node between the first and second stage of the sense amplifier to swing high for both a strong or weak zero condition. A diode clamp generally limits the current drawn under the strong or weak zero condition by clamping the output of the first stage from going too high. When a transition from a strong zero to a weak zero occurs, the output of the first stage essentially remains high since the gate to source drive on the pulldown remains considerably weak.

Abstract: A programmable analog array (10) comprises an array (11) of cells, each cell including analog circuitry (12), a switch control circuit (18), and a digital storage element (16). The switch control circuit (18) receives a clock signal and sequentially configures the circuits within the analog circuitry (12) to realize different circuit functions in accordance with configuration data stored in different digital memory units (17A-17D) within digital storage element (16). During a time interval, the analog signals generated by the analog circuitry (12) before that time interval are stored in an analog storage element (14), which is constructed from a portion of a capacitor network (54) in the analog circuitry (12) and is partitioned into a set of analog memory units (56A-56D). Each analog memory unit (56A-56D) stores the analog signal for a corresponding phase of the clock signal.

Abstract: A temperature compensated logarithmic detector biased with a proportional to absolute temperature (PTAT) voltage produced in accordance with an area ratio of biasing transistors is disclosed. According to one implementation of the invention, the temperature compensated logarithmic detector includes biasing circuitry and a logarithmic detector cell. The biasing circuitry receives an input signal and produces a PTAT bias voltage from the input signal. The PTAT characteristic of the PTAT bias voltage is produced by an area ratio. The logarithmic detector cell converts the input signal to a logarithmic output signal in accordance with a logarithmic transfer function over a narrow range.

Abstract: A logarithmic amplifier circuit including a first triple-tail cell for rectifying an initial input signal to produce a first rectified output signal and a first amplified output signal, a second triple-tail cell for rectifying the first amplified output signal of the first triple-tail cell to produce a second rectified output signal and a second amplified output signal; and an adder for adding the first rectified output signal and the second rectified output signal. Each of the first and second triple-tail cells has first, second and third transistors whose emitters or sources are coupled together, said first and second transistors forming a differential pair. The differential pair and third transistor are driven by a single tail current. A base or gate of the third transistor are applied with ad c tuning voltage. Reduction of the circuit scale and total current consumption, low-voltage operation, and the logarithmic characteristics tuning can be realized.

Abstract: A logarithmic amplification circuit is provided which is composed of a differential amplifier, a plurality of full-wave rectifiers including two half-wave rectifiers connected so as to have their input signals inverse in phase to each other and respectively receiving an output signal of the differential amplifier, and an adder for adding the output signals of the full-wave rectifier. Each of the half-wave rectifiers includes a differential transistor pair only one of which has an emitter resistor.

Abstract: A logarithmic amplifier circuit is provided, which contains a differential amplifier, a first rectifier for rectifying an initial input signal and for generating a first rectified output signal, a second rectifier for rectifying an amplified output signal from the differential amplifier and for generating a second rectified output signal, and an adder for adding the first and second rectified output signals to produce an output signal having a logarithmic characteristic. The first and second rectifiers each is made of a triple-tail cell. The cell contains first, second and third emitter- or source-coupled transistors and a constant current source for driving the transistors. An input signal is applied across bases or gates of the first and second transistors, and a dc voltage is applied to a base or gate of the third transistor. An output current is outputted through the coupled collectors or drains of the first and second transistors or through the collector or drain of the third transistor.

Abstract: A logarithmic amplifying circuit with a reduced power dissipation and suitable for applying to an integrated circuit. The logarithmic amplifying circuit has cascade-connected differential amplifiers, a rectifier connected to each if the amplifiers and an adder for adding the output currents of the rectifiers. Each of the rectifiers has a differential pair composed of a plurality of transistors emitter-coupled or source-coupled, a constant current source for a tail current of the differential pair and an offset voltage source for superimposing a DC offset voltage on a differential input voltage to be supplied to the differential pair.

Abstract: A detector cell for a logarithmic includes a differential pair of inputs across which a input signal V.sub.0 is applied across. The detector cell also includes a pair of differential outputs. The detector cell is comprised of three transistors Q4, Q5 and Q6. Resistors are coupled between the bases of adjacent transistors. The resistors form a voltage divided across which the input signal V.sub.0 is divided. The emitters of the three transistors are coupled to a current source, which sends a predetermined amount of current Ihd D. The collectors of the first and third transistors are coupled together to form a first differential input of the differential input pair. The collector of the second transistor alone forms the second differential input of the pair. The emitter area of the second transistor is ratioed with respect to the first and third so that a current I.sub.1 flowing through the first differential output is equal to a current I.sub.

Abstract: A logarithmic convertor based on a nonlinear successive detection principle has a temperature-compensated biassing arrangement and a large operating range due to a d.c. feedback network for offset reduction and an attenuating input stage permitting large input voltages. The log convertor exploits the exponential relationship between the collector current and base-emitter voltage of a bipolar transistor to render the convertor insensitive to temperature and process parameter variations. The converter is a cascade of sections, each having a constant-gain differential amplifier having a particularized current source. The constant-gain amplifier may include a Darlington differential pair, and the current sources have outputs that are either temperature-independent, or proportional to temperature.

Abstract: In a logarithmic intermediate frequency amplifier circuit including first through M-th intermediate frequency amplifiers which are connected in cascade and first through M-th double balanced differential circuits which are connected to the first through the M-th intermediate frequency amplifiers, respectively, each of the first through the M-th double balanced differential circuits comprises primary, secondary, and tertiary differential circuits. The primary differential circuit includes a pair of transistors each of which is one of NPN and PNP types and which are connected to a first constant current source. The secondary differential circuit includes a pair of transistors each of which is another one of NPN and PNP types and which are connected to a second constant current source. The tertiary differential circuit includes a pair of transistors each of which is the other one of the NPN and the PNP types and which are connected to a third constant current source.

Abstract: A cascaded amplifier is comprised of a number of amplifying stages connected in cascade such as the dual emitter-coupled amplifier shown. A first pair of transistors (14,20) provides limiting amplification and a second pair of transistors (16,18) with degeneration (22,24) provide linear amplification. Each pair of transistors is driven by a current source (28,26) which supplies a current (IT, IT2) proportional to absolute temperature (PTAT). The small signal amplification is then substantially independent of temperature and the value of the limited output is proportional to absolute temperature. This latter effect is countered by including a translinear variable current gain amplifier (54,56,58,60) in the last dual-gain stage of the cascaded amplifier to modify the output voltage in a manner inversely proportional to absolute temperature. A transfer function may thus be provided which is substantially independent of temperature.

Abstract: A logarithmic amplifying circuit with a wide input dynamic range using cascade-connected differential amplifiers, a rectifier connected to each of the amplifiers and an adder for adding the output currents of the rectifiers. The rectifiers each have a quadritail cell which consists of a single tall current source and four transistors. The transistors are emitter-connected or source-connected and driven by the tail current source. The bases or gates of the first and second transistors of the quadritail cell are connected to respective terminals of a differential input pair of the rectifier. The collectors or drains of the first and second transistors are connected in common to one terminal of a differential output pair of the rectifier, and the collectors or drains of the third and fourth transistors are connected in common to the other output terminal of the rectifier.

Abstract: A C-MOS logarithmic IF amplifier is provided which comprises a plurality of IF amplifiers cascade-connected to each other through a first coupling capacitor, a plurality of rectifiers each receiving a signal from the corresponding one of the plurality of IF amplifiers through a second coupling capacitor different in capacity from the first coupling capacitor, and an adder for adding the output signals of these rectifiers to each other. The first and second coupling capacitors are preferable to be connected in series to cascade-connect those IF amplifiers therethrough. Each of the rectifiers is applied with an output signal of the corresponding one of the IF amplifier from the connection point of the corresponding first and second coupling capacitors.

Abstract: A wideband amplifier which employs a plurality of cascaded logarithmic amplifier stages under the control of a digital signal processor which nulls offset voltages. In one aspect of the invention, the digital signal processor controls switches, one switch associated with each amplifier stage for determining an appropriate offset voltage and producing a counterbalancing signal. In another aspect of the invention the amplifier includes two potentiometers or variable signal devices which can set the overall input signal level and set the ratio of maximum to minimum of the input signal level, respectively, to desired levels. In a third aspect of the invention, a lookup table is associated with the digital signal processor for storing correction factors to be applied to digitized values in order to produce a final result which is corrected for variations in the amplifier characteristic from true logarithmic.

Abstract: A dual-mode successive detection amplifier for providing a first output signal corresponding to a logarithmic function of a RF input signal, and for providing a second limited RF output signal is disclosed herein. A RF input signal is applied to the first of a succession of amplification stages arranged along a RF signal path to cascade amplify the RF input signal into the limited RF output signal. A plurality of detector/limiter (D/L) circuits interposed between the amplification stages limit RF signal energy propagating along the RF signal path so as to prevent saturation of the amplification stages. The D/L modules also provide a succession of detection signals corresponding to video envelopes of the RF signal energy produced by each of the amplification stages. The detection signals are applied to a video summation line and therein summed to produce the logarithmic output signal.

Abstract: The invention relates to a method and an arrangement intended for radio communication systems and effective in digitalizing and subsequently processing numerically arbitrary radio signals. The signals are represented by composite (complex) vectors which have been subjected to disturbances in the system, such that information in the signals has been lost. This information is restored in its entirety when practising the present invention. For the purpose of solving this problem, the inventive digitalizing arrangement includes a multistage logarithmic amplifier chain (A) in which each stage is connected to a separate detector (D), the output signals of which are added in an adder. The adder output signals are then transmitted to a first A/D-converter (AD1) for digitalizing and converting the amplitude components of the signal.