Abstract: The object is to provide a technology enabling appropriate driving of an IGBT. A driving circuit is a driving circuit that drives an IGBT by controlling the gate voltage of the IGBT, and includes a first charging capability and a second charging capability. The first charging capability increases the gate voltage up to a threshold voltage of the IGBT, and a second charging capability increases the gate voltage beyond the threshold voltage. An increase in the gate voltage with the first charging capability per unit time is higher than an increase in the gate voltage with the second charging capability per unit time.

Abstract: In a general aspect, a silicon carbide (SiC) rectifier can include a substrate of a first conductivity type, a drift region of the first conductivity type, a junction field effect transistor (JFET) region of the first conductivity type, a body region of a second conductivity type, an anode implant region of the first conductivity type, and a channel of the first conductivity type. The channel can be in contact with and disposed between the JFET region and the anode implant region. A portion of the channel between the anode implant region and the JFET region can be disposed in the body region, The channel can be configured to be off under zero-bias conditions, and on at a positive turn-on voltage.

Abstract: The present invention relates to an insulated gate bipolar transistor (IGBT) driver module for driving at least one gate of at least one IGBT device, and method therefor. The IGBT driver module comprises at least one series capacitance operably coupled between a driver component of the IGBT driver module and the at least one gate of the at least one IGBT device. The IGBT driver module further comprises at least one series capacitance charge adjustment component controllable to determine a gate voltage error (?Gerr) at the at least one gate of the at least one IGBT device and dynamically adjust a charge of the at least one series capacitance based at least partly on the determined gate voltage error (?Gerr).

Abstract: In accordance with an embodiment, a method of operating a switched-mode power supply includes controlling a first switch coupled between an inductor and a reference node. Controlling includes modulating a first switching signal to control a first current through the first switch to a first predetermined current, and attenuating a current supplied by the first switch to the inductor in accordance with an attenuation factor to form an attenuated current. Attenuating includes providing a pulse modulated signal to a second switch coupled between the first switch and the inductor, where the attenuation factor is related to a pulse density of the pulse modulated signal.

Abstract: Systems and methods provide actuator control. Actuator control is provided via charge control as opposed to voltage control. A driver for driving an actuator can include a charge pump for injecting charge into one or more capacitive elements of the actuator. The driver can further include a capacitance detection aspect for detecting the capacitance of the capacitive elements of the actuator to determine positioning of the actuator.

Abstract: Embodiments of the present invention provide a flash memory which has high operating efficiency and a longer service life, and relate to the field of electronic technologies. The flash memory includes a control circuit and a plurality of memory cells, where the memory cell is a floating-gate MOS transistor which includes a source, a gate, a drain, and a substrate; the control circuit is separately connected to the source, the gate, the drain, and the substrate and configured to output a control signal to them, so as to implement a bitwise overwrite operation on the memory cell; and the control circuit is further configured to generate a control signal when data stored by any one of the memory cells is 0, so that the memory cell overwrites the data stored by the memory cell from 0 to 1 according to the control signal.

Abstract: A semiconductor integrated circuit device includes a substrate structure layer including a substrate having a well and a diffusion region thereon, an interconnect layer including a pair of power supply lines arranged at a preset spacing from the substrate structure layer; the interconnect layer also including an input side interconnect and an output side interconnect between the pair of power supply lines, a standard cell having a logic circuit on the substrate; the logic circuit being electrically connected to the pair of power supply lines, the input side interconnect and the output side interconnect, and one or more capacitances arranged between the substrate structure layer and the interconnect layer and arranged in a region between the pair of power supply lines, the region being inclusive of a region superposed with the pair of power supply lines.

Abstract: A switching system for a combustion engine ignition system comprises a switching device switchable between an accumulation condition and a transfer condition to activate an ignition element. The switching system comprises control logic that provides a control signal for controlling the switching device, measures a progress indicator indicative of progress in switching the switching device from the transfer condition to the accumulation condition, and causes the control signal to vary with a first variation rate during a first stage until the progress indicator reaches a first progress condition. The control logic causes the control signal to vary with a second variation rate, lower than the first variation rate, during a second stage until the progress indicator reaches a second progress condition, and causes the control signal to vary with a third variation rate, higher than the second variation rate, during a third stage of the preliminary switching.

Abstract: A semiconductor device outputs a signal to control a gate potential a switching device. The semiconductor device includes a first signal output terminal, and is capable of receiving or internally creating a reference signal, which varies between a first potential and a second potential. The semiconductor device can switch between first and second operations. The first operation outputs to the first signal output terminal a signal that is at a third potential when the reference signal is at the first potential, and that is at a fourth potential higher than the third potential when the reference signal is at the second potential. The second operation outputs to the first signal output terminal a signal that is at the fourth potential when the reference signal is at the first potential, and that is at the third potential when the reference signal is at the second potential.

Abstract: The disclosed transistor switching methodology enables independent control of transistor turn-on delay and slew rate, including charging, during a pre-charge period, a transistor control input to a threshold voltage VT with a predetermined turn-on delay; and then charging, during a switch-on period, the transistor control input from VT to an operating point with a predetermined slew rate. This methodology is adaptable to load switching applications, for example, to control a high side/low side load switch such that, during the switch on period, the output voltage supplied to the load rises from zero volts to an operating load voltage with the predetermined slew rate. In one embodiment, I_delay and I_slew_rate currents are used to charge the transistor control input respectively during the pre-charge and switch-on periods.

Abstract: The present invention discloses a semiconductor switch comprising a switching unit. Said switching unit includes: a transistor having a drain, a gate and a source; a drain bias resistor coupled to the drain; a drain bias selecting circuit to couple the drain bias resistor with a first or a second drain bias according to the transistor's state; a gate bias resistor coupled to the gate; a gate bias selecting circuit to couple the gate bias resistor with a first or a second gate bias according to the transistor's state; a source bias resistor coupled to the source; and a source bias selecting circuit to couple the source bias resistor with a first or a second source bias according to the transistor's state, wherein the first and second drain biases are different, the first and second gate biases are different, and the first and second source biases are different.

Abstract: A lateral insulated gate turn-off (IGTO) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of NPN and PNP transistors, where the well forms the base of the NPN transistor. When a turn-on voltage is applied to the gate, the p-base has a reduced width, resulting in the beta of the NPN transistor increasing beyond a threshold to turn on the IGTO device by current feedback.

Abstract: A circuit includes a switching element with a first terminal, a second terminal and a control terminal. The circuit also includes an impedance network coupled between the control terminal and a switching node. The circuit also includes a first accelerating element coupled between the control terminal and a first node. The first node is different from the switching node. The circuit is configured to temporarily activate the first accelerating element when a switching state of the switching element is to be changed.

Abstract: A gate drive circuit includes: an input port for receiving a control signal; an output port; a capacitor connected to the output port; a modulation unit which generates (i) a first modulated signal indicating timing of a first logical value of the control signal and (ii) a second modulated signal indicating timing of at least a second logical value of the control signal; a first electromagnetic resonance coupler which wirelessly transmits the first modulated signal; a second electromagnetic resonance coupler which wirelessly transmits the second modulated signal; a first rectifier circuit which generates a first demodulated signal by demodulating the first modulated signal, and outputs the first demodulated signal to the output port; and a second rectifier circuit which generates a second demodulated signal by demodulating the second modulated signal, and outputs the second demodulated signal to the output port.

Abstract: A method and apparatus for controlling a device in electronic equipment having a plurality of devices are provided. The apparatus includes a power supply for supplying power, a slave device including a driving circuit operated according to the supplied power for transmitting and receiving data to and from another device, a switching circuit for connecting the driving circuit to a ground terminal when the switching circuit is turned-on and for opening the driving circuit from the ground terminal when the switching circuit is turned-off, and a host device for transmitting a control signal for turning-on the switching circuit when driving the slave device and for turning-off the switching circuit when not driving the slave device. When the device is not driven, the switching circuit may open a driving circuit from a ground terminal, thereby cutting-off leakage of an electric current through the device.

Abstract: A gate voltage generating circuit to provide a gate voltage to a transistor switch is disclosed. The gate voltage generating circuit includes a first voltage generating circuit and a second voltage generating circuit. The first voltage generating circuit supplies a first voltage to a gate electrode of the transistor switch. The second voltage generating circuit supplies a second voltage to the gate electrode of the transistor switch. The second voltage is larger than a voltage to turn on the transistor switch. The first voltage is larger than the second voltage.

Abstract: A gate drive circuit which drives a gate terminal of a semiconductor switching device includes: a first wireless signal transmitter which transmits an input first AC signal wirelessly; a second wireless signal transmitter which transmits an input second AC signal wirelessly; a first rectifier circuit which includes a first diode that rectifies an output signal from the first wireless signal transmitter; and a second rectifier circuit which includes a second diode that rectifies an output signal from the second wireless signal transmitter. A threshold voltage of the second diode is larger than a threshold voltage of the first diode.

Abstract: An apparatus and method for implementing a bootstrapped switching circuit having improved (i.e. faster) turn-on time is provided. In an embodiment, an inner switching loop is implemented in a bootstrapped switching circuit where the inner switching loop is configured to turn on an input switch in the bootstrapped drive circuit independent of the drive circuit output. The embodiment decouples the inner switching loop circuitry from the output drive circuit of the bootstrapped switching circuit, which typically has a larger load capacitance than the inner switching loop. This allows the inner switching loop to turn on the input switch in the bootstrapped switching circuit faster and decreases the turn-on time of the bootstrapped switching circuit.

Abstract: A lateral insulated gate turn-off (IGTO) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of NPN and PNP transistors, where the well forms the base of the NPN transistor. When a turn-on voltage is applied to the gate, the p-base has a reduced width, resulting in the beta of the NPN transistor increasing beyond a threshold to turn on the IGTO device by current feedback.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: Disclosed herein is a resistor-sharing switching circuit, including: a first switching element turning on/off between a first input and output terminal and a second input and output terminal; a second switching element turning on/off between the first input and output terminal and a third input and output terminal; a signal transmission unit connected to both a control terminal of the first switching element and a control terminal of the second switching element; and a resistor having one end connected to the signal transmission unit and the other end connected to a control signal input terminal.

Abstract: An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.

Abstract: In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.

Abstract: A semiconductor device outputs a signal to control a gate potential a switching device. The semiconductor device includes a first signal output terminal, and is capable of receiving or internally creating a reference signal, which varies between a first potential and a second potential. The semiconductor device can switch between first and second operations. The first operation outputs to the first signal output terminal a signal that is at a third potential when the reference signal is at the first potential, and that is at a fourth potential higher than the third potential when the reference signal is at the second potential. The second operation outputs to the first signal output terminal a signal that is at the fourth potential when the reference signal is at the first potential, and that is at the third potential when the reference signal is at the second potential.

Abstract: A gate drive circuit for driving an IGBT serving as a power semiconductor device includes a constant-current gate drive circuit that charges a gate capacity of the IGBT at a constant current, and a constant-voltage gate drive circuit that is connected in parallel to the constant-current gate drive circuit between input and output terminals thereof via a series circuit constituted by a MOSFET and a resistor, and charges the gate capacity of the IGBT at a constant voltage, wherein the gate drive circuit charges the gate capacity of the IGBT using both the constant-current gate drive circuit and the constant-voltage gate drive circuit at the time of driving the IGBT.

Abstract: The present invention relates to semiconductor technology. In particular, the present invention relates to high-speed, high voltage switching for a high voltage generator for an X-ray system. Switching elements, e.g. IGBTs or MOS-FETs, are employed for high-speed high voltage switching. However, circuit elements or parasitic elements at an input of the switching element limit the switching speed of the switching element. The present invention proposes applying a higher than allowed voltage to the input of the switching element, e.g. a voltage higher than the maximum allowed gate voltage of an IGBT or MOS-FET, to increase switching speed. A feedback loop is provided for save operation.

Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.

Abstract: One configuration of the present disclosure is directed to a switch driver circuit. The switch driver circuit can include an input to receive a control signal; an output to control a state of an switch in accordance with the control signal; and a set of parallel switches. The set of parallel switches in the switch driver circuit includes a P-type field effect transistor in parallel with an N-type field effect transistor. During operation, via variations in the control signal, the control signal selectively and electrically couples a voltage source signal to the output of the switch driver circuit to control the state of the switch.

Abstract: An ignitor semiconductor apparatus can include an output stage IGBT that controls the ON and OFF of the primary current of ignition coil, a sensing IGBT and a sensing resistance for detecting the current flowing through output stage IGBT, gate resistance and a current control circuit that detects the voltage across sensing resistance and controls the current flowing through output stage IGBT. First and second gate control circuits separately control the gate voltages of IGBT's such that the gate voltage of the output stage IGBT is higher than the gate voltage of the sensing IGBT, when the current flowing through output stage IGBT is larger than a predetermined current value, and such that the gate voltage of output stage IGBT is lower than the gate voltage of sensing IGBT, when the current flowing through output stage IGBT is smaller than the predetermined current value.

Abstract: Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described.

Abstract: A control circuit controls a driving transistor connected in series with an electrical load between a power supply voltage and a ground. The control circuit includes a pull-up resistor connected at one end to a power supply voltage side of the driving transistor, a current detection resistor for detecting an electric current flowing from the driving transistor to the ground, a current mirror circuit including a starting transistor connected between the pull-up transistor and the current detection resistor. The current mirror circuit supplies a mirror current of the electric current. The control circuit further includes a current source circuit for supplying a driving current to a control terminal of the driving transistor in accordance with the mirror current to turn ON the driving transistor in response to an external control signal.

Abstract: There is provided a method for testing a switching circuit including a first FET connected between input/output terminals, a capacitor connected between one of the input/output terminals and the first FET, and a second FET that is connected in parallel with the capacitor and has a gate electrode connected to a ground terminal. The method includes, applying a potential that sets the second FET to a conducting state to the ground terminal, and testing a DC test for the first FET via the second FET.

Abstract: A control circuit controls a driving transistor connected in series with an electrical load between a power supply voltage and a ground. The control circuit includes a pull-up resistor connected at one end to a power supply voltage side of the driving transistor, a current detection resistor for detecting an electric current flowing from the driving transistor to the ground, a current mirror circuit including a starting transistor connected between the pull-up transistor and the current detection resistor. The current mirror circuit supplies a mirror current of the electric current. The control circuit further includes a current source circuit for supplying a driving current to a control terminal of the driving transistor in accordance with the mirror current to turn ON the driving transistor in response to an external control signal.

Abstract: Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described.

Abstract: A gate driving circuit for a voltage-driven power semiconductor switching device has (a) the voltage-driven power semiconductor switching device, (b) a driving circuit for supplying a drive signal to the gate electrode of the switching device, and (c) an inductance between the emitter control terminal or source control terminal of the switching device and the emitter main terminal or source main terminal of a semiconductor module. A voltage produced across the inductance is detected. The gate-driving voltage or gate drive resistance is made variable based on the detected value.

Abstract: An embodiment of a control circuit is proposed for turning on a power switching device, the switching device turning on in response to a control signal exceeding a threshold value. The control circuit includes pre-charging means for providing the control signal at a pre-charging value not reaching the threshold value, and soft turn-on means for gradually increasing the control signal from the pre-charging value to a turn-on value exceeding the threshold value; the pre-charging means includes means for sensing an indication of the threshold value, and means for setting the pre-charging value according to the sensed threshold value.

Abstract: A switch includes a switching transistor, a switching resistor, connected between a control terminal of the switching transistor and a switching control terminal, and an accelerating element. The accelerating element includes a resistance smaller than a resistance of the switching resistor, the accelerating element being adapted to be connected in parallel to the switching resistor upon switching of the switching transistor until a voltage at the control terminal of the switching transistor has reached a predetermined value.

Abstract: A core voltage controlling apparatus suitable for a center processing unit (CPU) is provided. The apparatus includes a level shifting unit, a time-delay unit and a logic unit. An input terminal of the level shifting unit receives and shifts a first voltage signal, and an output terminal generates a second voltage signal, in which the first voltage signal indicates a power-on stable state, and the second voltage signal indicates a magnitude of the core voltage. The time-delay unit delays the second voltage signal to generate a third voltage signal. The logic unit is coupled to the time-delay unit for performing a logic operation on the third voltage and a fourth voltage signal transmitted by a power supply, and generating a fifth voltage signal for controlling a core voltage generator whether to provide the core voltage to the CPU or not, in which the fourth voltage signal indicates a power state.

Abstract: A gate drive circuit includes a turn-on side circuit for turning on a gate of a power switching device, the turn-on side circuit including a first turn-on side power supply circuit and a second turn-on side power supply circuit, the first turn-on side power supply circuit including: a first turn-on voltage source for supplying a first turn-on voltage; first turn-on wiring; and a first turn-on switch connected in the first turn-on wiring and controlled by a gate drive signal; and the second turn-on side power supply circuit including: a second turn-on voltage source for supplying a second turn-on voltage applied to the gate of the power switching device to set the power switching device in a steady (on) state; second turn-on wiring; a second turn-on switch connected in the second turn-on wiring; and a turn-on side delay circuit for delaying the gate drive signal and passing it to the second turn-on switch.

Abstract: The invention concerns a method for controlling a switching assembly comprising a plurality of transistors connected in parallel, having a linear operating mode, a closed-switch operating mode and an off operating mode including a first operating phase during which a current flows from a source terminal to a drain terminal and a second operating phase during which no current flows. The method includes the following successive steps; (a) controlling the switching assembly in closed-switch mode during part of the first phase; (b) controlling the switching assembly in linear mode; (c) controlling the assembly in off mode during part of the second phase.

Abstract: This patent specification describes a backflow prevention circuit which includes a first switch configured to conduct or to shut down a current path from an input terminal to an output terminal, a logic circuit configured to binarize an input voltage at the input terminal based on an output voltage at the output terminal and to output a binary signal and a shutdown circuit configured to cause the first switch to shut down independently of a switching control signal in accordance with the binary signal output from the logic circuit. The switching control signal performs a switching control of the first switch. The logic circuit outputs a shutdown signal to shut down independently of the switching control signal when the input voltage becomes smaller than the output voltage.

Abstract: A fast active DCAP cell which has a short turn-on time, achieves a high capacitance density, and which minimizes leakage overhead during its normal operation mode is disclosed. The DCAP cell has a pair of PMOS transistors that have their drains connected to a gate of a PMOS transistor and their sources connected to the VDD rail. The drain and source of the PMOS transistor are connected to the VSS rail. Likewise, the DCAP cell has a pair of NMOS transistors that have their drains connected to a gate of an PMOS transistor and their sources connected to the VSS rail. The drain and source of the PMOS transistor are connected to the VDD rail. None of the gates of the transistors is connected to the VDD or VSS rail. This protects the gate oxide from being damaged by ESD surge currents.

Abstract: A switch circuit is provided for conditional communication within a magnetic-induction interface, including first and second control nodes, a data input and output nodes, a parallel circuit, and first and second control nodes. The parallel circuit includes a pair of legs, each leg connecting to the data input and data output nodes. Each leg has a connector to a condition. Each control node is connected to the corresponding connector. The condition is one of the interface is connected and the interface is disconnected. The parallel circuit enables communication between the data input and output nodes only in response to the condition being that the interface is disconnected. The pair of leg includes first and second legs. The first leg includes a first MOSFET and a first diode. The first MOSFET has a first source, a first gate and a first drain. The second leg includes a second MOSFET and a second diode. The second MOSFET has a second source, a second gate and a second drain.

Abstract: A switching control system and method is provided that optimizes switching efficiencies for power switching applications including automotive ignition systems, solenoid drivers, motor drivers and power regulation systems. In an ignition system, a coil current switching magnitude is controlled at the start of ignition coil charging, thereby avoiding an untimely spark event. When the transistor threshold voltage is reached, the collapse rate of the ignition system transistor collector voltage is reduced by reducing the gate charging current. The reduced collector voltage slew rate results in a reduced primary and secondary coil output voltage. After the collector voltage collapses, a continued rapid charge is provided to place the transistor in a hard saturation bias condition. In an aspect, the present invention dynamically determines the threshold voltage of a power transistor.

Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described.

Abstract: A quick turn on apparatus and method for a NMOSFET switch are used to maintain the gate voltage of the NMOSFET switch non-zero but not enough to turn on the NMOSFET switch, such that the NMOSFET switch turns on more quickly when it is to be turned on. Seamless transition can be further achieved in a single pole double throw switching circuit by using the quick turn on apparatus and method.

Abstract: The present invention provides a driving circuit. It includes a plurality of current mirrors to generate a first charge current and a second charge current in response to a reference current. A switch circuit generates a driving signal in response to an input signal. A driving switch is coupled between the first charge current and the switch circuit. Once the driving switch is turned on and the level of the input signal is in high level, the switch circuit generates the driving signal, the level of the driving signal-being in high level, in response to the first charge current and the second charge current. A detection circuit generates a control signal to turn on/off the driving switch. The detection circuit turns off the driving switch to disable the first charge current after a period of delay time when the level of the driving signal is in high level.

Abstract: A high voltage rectifier device exhibiting low forward resistance and fast switching time formed of a high voltage structure connected in a cascode configuration with a low voltage structure. The high voltage structure is a bidirectional normally on semiconductor switch have two pairs of gate and source terminals which shuts off if either of the gate terminals is reverse biased. The low voltage structure is a diode, preferably a Schottky or barrier diode. The device is advantageously formed as an integrated circuit. With one of the terminal pairs of the switch clamped to zero volts, the device behaves as a diode, or the second terminal pair can be employed to provide the functions of a three terminal controlled rectifier. Among other possible applications are integrated circuits using four of the devices as a bridge rectifier, and as an anti-parallel diode for connection with an IGBT.

Abstract: A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.