Abstract: A driver circuit for driving a switching device having a control electrode. The driver circuit includes an ON circuit configured to turn on the switching device in response to a first drive signal, and an OFF circuit configured to discharge a parasitic capacitance of the control electrode of the switching device with a constant current, to turn off the switching device, in response to a second drive signal.

Abstract: Provided is a semiconductor device including a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode, a fourth electrode, and a second control electrode, a first capacitor having a first end and a second end, a Zener diode having a first anode and a first cathode, a first resistor having a third end and a fourth end, a first diode having a second anode and a second cathode, a second resistor having a fifth end and a sixth end, a second diode having a third anode and a third cathode, and a second capacitor having a seventh end and an eighth end.

Abstract: A method for operating an IGBT includes determining a maximum stationary reverse bias required for operation of the IGBT, determining a first removal charge, the removal of which at the gate of the IGBT causes an electric field strength that enables the IGBT to accept the maximum stationary reverse bias during stationary blocking, determining a second removal charge, the removal of which at the gate causes an electric field strength that leads to a dynamic avalanche, and, when the IGBT is switched off, removing from the gate during a charge removal duration a removal charge that is greater than the first removal charge and smaller than the second removal charge.

Abstract: A method for detecting a threshold voltage of a driving transistor includes: obtaining at least one first threshold voltage of at least one driving transistor when each driving transistor is driven by a corresponding first driving signal; obtaining a threshold reference voltage of the driving transistor according to the at least one first threshold voltage; obtaining a second driving signal of the driving transistor according to the threshold reference voltage and the first driving signal of the driving transistor, a value of the second driving signal being greater than a value of the first driving signal; and obtaining a second threshold voltage of the driving transistor when the driving transistor is driven by the second driving signal.

Abstract: A low-power-consumption high-speed zero-current switch includes a delay controller, a driving stage and a power transistor MN, wherein: an input of the delay controller is connected with an external clock CLK, an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor MN; the delay controller includes a gate signal generator, a sampling circuit and a current controller, and three of which form a negative feedback loop for stabilizing the turn-on voltage VON and the turn-off voltage VD to 0, so that when the power transistor MN is turned on or off, the source-drain voltage thereof is 0. The present invention no longer uses a high-power-consumption high-speed comparator, but uses a low-power-consumption delay controller to generate turn-on and turn-off signals of the power transistor.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: A power semiconductor drive circuit includes a parallel circuit connected to a gate of a power semiconductor element and constituted by two transistors for setting gate resistance of the power semiconductor element; a gate voltage monitoring circuit connected to the gate of the power semiconductor element and the parallel circuit, wherein a monitoring voltage is set in the gate voltage monitoring circuit to monitor a gate voltage of the power semiconductor element; a signal delay circuit to delay an output signal of the gate voltage monitoring circuit; and a gate control circuit to change the magnitude of combined resistance of the parallel circuit based on an output signal output from the signal delay circuit.

Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

Abstract: In an aspect, a circuit can include a first HEMT, a second HEMT, and a variable capacitor. A drain of the first HEMT can be coupled to a source of the second HEMT. An electrode of the variable capacitor can be coupled to a source of the first HEMT, and another electrode of the variable capacitor can be coupled to a gate of the second HEMT. In another aspect, an electronic device can include a die including a HEMT and a variable capacitor. An electrode of the variable capacitor can be coupled to a source or a gate of the HEMT, and another electrode of the variable capacitor can be coupled to an external terminal of the die. In a further aspect, an electronic device comprising a die, wherein the die includes a variable capacitor, a first diode, and a second diode.

Abstract: A device for overcurrent protection, the device may include a main transistor that is configured to supply, via an output node, a load current to a load; a current limiting resistor; a replica transistor that is configured to provide a replica current to the current limiting resistor; wherein the replica current is smaller than the load current, wherein a value of the replica current is responsive to a value of the load current; an amplifier; a current limiting transistor; a variable signal source that is configured to output a reference signal; wherein a value of the reference signal is based on a main transistor voltage; wherein the amplifier is configured to prevent the load current from exceeding a first load current threshold by biasing the main transistor and the replica transistor with a bias signal; wherein a value of the bias signal is responsive to the reference signal and to the replica current.

Abstract: Systems and methods are provided for improved linearity of audio amplifiers. In one example, a system includes a first current source configured to provide a first current signal having a first current source output capacitance, and a second current source configured to provide a second current signal having a second current source output capacitance, where the first and second current source output capacitances are a different value. The system further includes a first capacitor compensation device coupled to an output of the first current source configured to provide a capacitance value to compensate for the second current source output capacitance, and a second capacitor compensation device coupled to an output of the second current source configured to provide a capacitance value to compensate for the first current source output capacitance. The system further includes a plurality of switches configured to switch the first and second current signals.

Abstract: The semiconductor device according to one embodiment includes a power transistor and a sense transistor connected in parallel with each other, a first operational amplifier having a non-inverting input terminal connected to an emitter of the sense transistor and an inverting input terminal connected to an emitter of the power transistor, a resistor element having one end connected to the emitter of the sense transistor and another end connected to a first node, and an adjustment transistor placed between the first node and a low-voltage power supply. The first operational amplifier adjusts a current flowing through the adjustment transistor so that an emitter voltage of the power transistor and an emitter voltage of the sense transistor are substantially the same.

Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.

Abstract: An electronically switchable diplexer (200), especially an electronically switchable diplexer (200) with low video crosstalk, comprises a low-pass terminal (210), a terminal (220) for feeding in a first control signal, a common terminal (230), a high-pass terminal (240), and a terminal (250) for feeding in a second control signal, wherein the low-pass path of the diplexer (200) operates down to DC (direct current).

Abstract: A semiconductor device drive circuit includes a first drive circuit and a second drive circuit. The first drive circuit generates a control signal for controlling a voltage-controlled switching element. The first drive circuit generates a control signal in synchronization with a voltage signal input to the first drive signal. The first drive circuit has an output current capability corresponding to a magnitude of the voltage signal. The second drive circuit outputs a voltage signal to the first drive circuit. The second drive circuit includes an output adjustment circuit that adjusts the magnitude of the voltage signal.

Abstract: The invention provides a power converter comprising: an input for receiving input power with a variable nominal mains level, wherein said variable nominal mains level falls within at least 90V to 240V; a main power switch (Q1) driven by the input power, and a control circuit (Q2, Q3) for controlling a control current of the main power switch (Q1), wherein the control circuit in (Q2, Q3) is adapted to sense the level of the input power and draw current from a control terminal of the power switch (Q1) according to the level, and said control circuit is adapted to operate in linear region and increase the drawn current along with the increase of the level throughout the variable nominal mains level of the input power, wherein the control circuit comprises: a Darlington bridge with a first transistor (Q2) and a second transistor (Q3), the first transistor (Q2) with a base terminal connected to a circuit position indicative of the voltage amplitude of the input power, the second transistor (Q3) with a base termina

Abstract: There is a problem in related-art semiconductor devices that the chip size of a semiconductor device having an active Miller clamp function cannot be reduced. According to one embodiment, a semiconductor device is configured to, when a power device is turned on or off, monitor a gate voltage Vg of the power device, set a predetermined range within a transition range, the transition range being a range within which the gate voltage Vg changes, change, when the gate voltage Vg is within the predetermined range, the gate voltage Vg of the power device by using a predetermined number of constant-current circuits, and change, when the gate voltage Vg is outside the predetermined range, the gate voltage Vg by using a larger number of constant-current circuits than the number of constant-current circuits that are used when the gate voltage Vg is within the predetermined range.

Abstract: Apparatus and methods for level shifting in a radio frequency system are provided. In certain configurations, a radio frequency system includes a level shifter operable to provide level shifting to an input signal. The level shifter is biased by a bias voltage and powered by a supply voltage and a charge pump voltage. The radio frequency system further includes a charge pump configured to provide the charge pump voltage and to receive a mode signal operable to enable the charge pump in a first state and to disable the charge pump in a second state. The radio frequency system further includes a level shifter control circuit configured to control the bias voltage to track the charge pump voltage when the mode signal is in the first state, and to control the bias voltage with the supply voltage when the mode signal is in the second state.

Abstract: A drive device driving a power converter that includes a switching element formed from a wide bandgap semiconductor, includes a PWM-signal output unit that generates a drive signal that drives the switching element with PWM; an on-speed reducing unit that, when the switching element is changed from off to on, reduces a change rate of the drive signal; and an off-speed improving unit that, when the switching element is changed from on to off, draws charge from the switching element at a high speed and with a charge drawing performance higher than that at a time when the switching element is changed from off to on.

Abstract: An integrated circuit device includes a clock gating circuit, which is configured to generate a first plurality of clocks in response to a first reference clock at a first frequency and a plurality of operation enable signals. A plurality of functional circuits are provided, which are responsive to respective ones of the first plurality of clocks. The plurality of functional circuits is configured to generate respective ones of the plurality of operation enable signals, with each of the plurality of operation enable signals having a first logic state that enables a respective clock within said clock gating circuit and a second logic state that disables the respective clock within said clock gating circuit.

Abstract: The semiconductor device according to one embodiment includes a power transistor and a sense transistor connected in parallel with each other, a first operational amplifier having a non-inverting input terminal connected to an emitter of the sense transistor and an inverting input terminal connected to an emitter of the power transistor, a resistor element having one end connected to the emitter of the sense transistor and another end connected to a first node, and an adjustment transistor placed between the first node and a low-voltage power supply. The first operational amplifier adjusts a current flowing through the adjustment transistor so that an emitter voltage of the power transistor and an emitter voltage of the sense transistor are substantially the same.

Abstract: A method of controlling electrical power delivery to a well tool can include transmitting trigger light via an optical waveguide to a circuit in a well, and the circuit delivering the electrical power to the well tool in response to the circuit receiving the trigger light. A circuit for supplying electrical power to at least one well tool can include a photodiode which receives light from an optical waveguide in a well, a voltage increaser which increases a voltage output by the photodiode, and an electrical energy storage device which receives electrical energy via the voltage increaser, whereby the electrical power can be supplied to the downhole well tool from the storage device.

Abstract: A gate drive circuit includes a first switch and a first capacitor. A first terminal of the first capacitor is electrically coupled to the first switch. The first switch is electrically coupled between the first terminal and a voltage supply of the power transistor. A second terminal of the first capacitor is electrically coupled to the reference potential. The gate drive circuit further includes a first voltage limiter in parallel with the first capacitor. The first voltage limiter limits a voltage across the first capacitor to a first predetermined voltage. The gate drive circuit further includes a second capacitor, a pre-charging circuit arranged between the first terminal of the first capacitor and a first terminal of the second capacitor. The gate drive circuit further includes a third capacitor with a first terminal electrically coupled to a second terminal of the second capacitor and a second terminal electrically coupled to a gate terminal of the power transistor.

Abstract: A rising time detecting circuit detects a rising time of an output voltage, and generates a rising time voltage according to the rising time. A rising time comparing circuit compares the rising time voltage with a target rising voltage, and outputs a rising comparison signal showing a compared result. A FET driving circuit controls an upper MOSFET based on the rising comparison signal. A rising regulating circuit regulates a change speed of the rising time voltage according to a rising regulating signal.

Abstract: In a switching control circuit, a determiner determines whether there is one of a first type of abnormality and a second type of abnormality different therefrom in a target switching element and/or the switching control circuit. A controller controls a second switching element to close a low-impedance discharge path for discharging a control terminal of the target switching element when it is determined that there is the first type of abnormality, and disables closing of a high-impedance discharge path for discharging the control terminal while the low-impedance discharge path is closed by the second switching element. The controller controls a third switching element to close the high-impedance discharge path when it is determined that there is the second type of abnormality; and disables closing of the low-impedance discharge path while the high-impedance discharge path is closed by the third switching element.

Abstract: A gate drive circuit in an aspect of the present disclosure includes a modulated signal generation circuit that generates a first modulated signal, a first isolator that isolatedly transmits the first modulated signal, and a first rectifier circuit that generates a first output signal by rectifying the first modulated signal. The first modulated signal includes a first amplitude, a second amplitude larger than the first amplitude, and a third amplitude larger than the second amplitude. The first output signal includes a first output voltage value according to the first amplitude, a second output voltage value according to the second amplitude, and a third output voltage value according to the third amplitude.

Abstract: An apparatus for providing auxiliary power to an off-line switcher. The apparatus includes a high voltage semiconductor switch and a driver for the high voltage semiconductor switch. The driver includes a first switch, the first switch coupled to the a third terminal of the high voltage semiconductor switch and to ground, a second switch coupled to a first terminal of the high voltage semiconductor switch, a third switch coupled to the first terminal of the high voltage semiconductor switch and to ground. The driver further includes a diode, the anode of the diode coupled to the third terminal of the high voltage semiconductor switch and the cathode of the diode coupled to the second switch.

Abstract: A driving circuit of the present invention drives a switching element connected to a main current circuit. The driving circuit includes a driving potion applying on/off-voltage to a gate of the switching element, a common inductor disposed in an interconnection part commonly connected to the driving circuit and a source side of the switching element in a loop formed of the main current circuit and the switching element, and a capacitor connected between the gate side and the source side on the driving portion side with respect to the common inductor.

Abstract: Embodiments of the disclosure relate to a low drop diode equivalent circuit. Piezoelectric device based vibration energy harvesting requires a rectifier for conversion of input ac to usable dc form. Power loss due to diode drop in rectifier is a significant fraction of the already low levels of harvested power. The low-drop-diode equivalent can replace the rectifier diodes and minimize power loss. The diode equivalent mimics a diode using linear region operated MOSFET. The diode equivalent is powered directly from input signal and requires no additional power supply for its control. Power used by the control circuit is kept at a value which gives an overall output power improvement. The diode equivalent replaces the four diodes in a full wave bridge rectifier, which is the basic full-wave rectifier and is a part of the more advanced rectifiers like switch-only and bias-flip rectifiers.

Abstract: A high frequency switch device includes a branch transmission line corresponding to each output terminal provided with a switching part. In the branch transmission line, the switching part includes a transmission side diode provided in such a manner that a cathode thereof is arranged on a side of an input terminal 41 and an anode thereof is arranged on a side of the output terminal, and a ground side diode provided in such a manner that a cathode thereof is grounded and an anode thereof is electrically connected between the output terminal and the transmission side diode in the branch transmission line. The branch transmission line includes a first capacitor and a second capacitor on the side of the output terminal from the transmission side diode in such a manner that the anode of the ground side diode is connected between the first capacitor and the second capacitor.

Abstract: A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load.

Abstract: A half bridge circuit including an isolation substrate, a metal layer on one surface of the isolation substrate, a power loop substrate on the metal layer, an upper switch on the power loop substrate, a lower switch on the power loop substrate and coupled to the upper switch, a capacitor on the power loop substrate and coupled to the upper switch, a first via through the power loop substrate and coupled between the lower switch and the metal layer, and a second via through the power loop substrate and coupled between the capacitor and the metal layer, wherein the power loop substrate has a height and separates the metal layer from the upper switch, lower switch and capacitor by the height.

Abstract: A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.

Abstract: An integrated circuit including a first power rail, a second power rail, a power clamp connected between the first and second power rails; and a trigger circuit connected to the power clamp and the first second power rails. The trigger circuit includes an RC element formed on the basis of field effect transistors, first inverter stage connected to the RC element, a second inverter stage, and a third inverter stage. The first, second and third inverter stages are connected in series to a control input of the power clamp. The trigger circuit also included a feed back connection from an output of the second inverter stage to the first inverter stage.

Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.

Abstract: The present invention discloses a semiconductor switch comprising a switching unit. Said switching unit includes: a transistor having a drain, a gate and a source; a drain bias resistor coupled to the drain; a drain bias selecting circuit to couple the drain bias resistor with a first or a second drain bias according to the transistor's state; a gate bias resistor coupled to the gate; a gate bias selecting circuit to couple the gate bias resistor with a first or a second gate bias according to the transistor's state; a source bias resistor coupled to the source; and a source bias selecting circuit to couple the source bias resistor with a first or a second source bias according to the transistor's state, wherein the first and second drain biases are different, the first and second gate biases are different, and the first and second source biases are different.

Abstract: A power electronic device includes first and second electronic switches, each integrated on a package having a low parasitic inductance, a supply terminal and a ground terminal. The first conduction terminal of the first switch may be coupled with the supply terminal, and the second conduction terminal of the second electronic switch may be coupled with the ground terminal. The corresponding control terminals of the switches may be coupled to corresponding pilot drivers. The package may include first and second electric terminals, wherein the second conduction terminal of the first switch is coupled to the first electric terminal, and the first conduction terminal of the second switch is coupled to the second electric terminal. A first inductance may be interposed between the first electric terminal and the output terminal and/or a second inductance interposed between the second electric terminal and the output terminal.

Abstract: The dead time is secured stably in a semiconductor drive circuit for switching devices using a wide band gap semiconductor. The drain terminal of the switching device of an upper arm is connected to the positive terminal of a first power supply, the source terminal of the switching device of a lower arm is connected to the negative terminal of the first power supply, and the source terminal of the switching device of the upper arm is connected with the drain terminal of the switching device of the lower arm. A gate drive circuit provided for each switching device includes an FET circuit and a parallel circuit made of a parallel connection of a first resistor and a first capacitor and having a first terminal connected to the gate terminal of the switching device.

Abstract: A controller for a converter is designed to receive from a measuring device measurement signals from an output line of the converter, and to analyze the measurement signals in order to generate a switching signal that has a switching frequency, wherein the controller comprises a sampler for generating a sample signal by sampling received measurement signals. The sampler is designed to perform the sampling at a sampling frequency that is less than three times the switching frequency. A converter comprises a controller in accordance with the invention.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages.

Abstract: A semiconductor device includes a first layer of a first-type, a second layer of a second-type formed on the first layer, a third layer of the first type formed on the second layer, a first electrode connected to the second and third layers, a second electrode connected to the first layer, a third electrode embedded in a trench formed through the third and second layers and into the first layer, a fourth electrode embedded in the trench below the third electrode, and an insulating layer formed in the trench around the fourth electrode. The first layer includes a first region that is in contact with the insulating layer and at which a concentration of the first-type dopant is lower than the concentration at a second region that is formed around the first region.

Abstract: An integrated circuit 2 includes a transistor 26 Which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract: A gate drive circuit which drives a gate terminal of a semiconductor switching device includes: a first wireless signal transmitter which transmits an input first AC signal wirelessly; a second wireless signal transmitter which transmits an input second AC signal wirelessly; a first rectifier circuit which includes a first diode that rectifies an output signal from the first wireless signal transmitter; and a second rectifier circuit which includes a second diode that rectifies an output signal from the second wireless signal transmitter. A threshold voltage of the second diode is larger than a threshold voltage of the first diode.

Abstract: A method and apparatus for predictive switching an output have been disclosed.

Abstract: There is provided a semiconductor integrated circuit including at least one MOS transistor a source or drain of which is connected an output terminal, and a driver circuit configured to drive a back gate or a well of the MOS transistor in a manner that voltage swing is in a same phase as the output terminal.

Abstract: A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.

Abstract: The present invention discloses a fast switching current mirror circuit and method for generating fast switching current. The circuit and method for fast switching of a current mirror with large MOSFET size will save space and current consumption.

Abstract: A high frequency switch device includes a branch transmission line corresponding to each output terminal provided with a switching part. In the branch transmission line, the switching part includes a transmission side diode provided in such a manner that a cathode thereof is arranged on a side of an input terminal 41 and an anode thereof is arranged on a side of the output terminal, and a ground side diode provided in such a manner that a cathode thereof is grounded and an anode thereof is electrically connected between the output terminal and the transmission side diode in the branch transmission line. The branch transmission line includes a first capacitor and a second capacitor on the side of the output terminal from the transmission side diode in such a manner that the anode of the ground side diode is connected between the first capacitor and the second capacitor.

Abstract: A power semiconductor device includes first and second power semiconductor elements connected in parallel to each other and a drive control unit. The drive control unit turns on or off each of the first and second power semiconductor elements in response to an ON instruction and an OFF instruction repeatedly received from outside. Specifically, the drive control unit can switch between a case where the first and second power semiconductor elements are simultaneously turned on and a case where one of the first and second power semiconductor elements is turned on first and thereafter the other thereof is turned on, in response to the ON instruction. The drive control unit turns off one of the first and second power semiconductor elements first and thereafter turns off the other thereof, in response to the OFF instruction.