Abstract: A leakage current blocking circuit and a leakage current blocking method for a decoupling capacitor are provided. A first end of the decoupling capacitor is coupled to a power voltage. The leakage current blocking circuit is coupled between a second end of the decoupling capacitor and a ground voltage, and the leakage current blocking circuit includes at least one switch. The at least one switch is used to provide a channel for the decoupling capacitor to be coupled to the ground voltage when the decoupling capacitor is not damaged, and when the decoupling capacitor is damaged, the at least one switch is turned off to block a leakage current of the decoupling capacitor.

Abstract: A radio frequency (RF) switch includes a switchable RF path including a plurality of transistors coupled in series; a gate bias network including a plurality of resistors, wherein the gate bias network is coupled to each of the plurality of transistors in the switchable RF path; and a bypass network including a first plurality of transistors coupled in parallel to each of the plurality of transistors in the switchable RF path and a second plurality of transistors coupled in parallel to each of the plurality of resistors in the gate bias network.

Abstract: Circuitry includes a pair of switches arranged in series, and a gate driver. The gate driver, responsive to a magnitude of current through one of the switches exceeding a threshold, discharges a gate of the one through a first resistor. The gate driver also, responsive to a voltage across a parasitic inductance of the switch becoming zero, discharges the gate through a second resistor but not the first resistor.

Abstract: One aspect of a semiconductor device includes a plurality of first structures, in which each of the first structures includes: a first N-type region; a P-type region which is surrounded by the first N-type region; and a second N-type region which is surrounded by the P-type region. The first N-type region and the P-type region are wired, and the plurality of first structures are connected in parallel to form one diode.

Abstract: A gate driver integrated circuit drives an output signal onto its output terminal and onto the gate of a power transistor. In a turn-on episode, a digital input signal transitions to a digital logic high level. In response, the gate driver integrated circuit couples the output terminal to a positive supply voltage terminal, thereby driving a positive voltage onto the gate of the power transistor. In response to a high-to-low transition of the digital input signal, the driver drives a negative voltage onto the output terminal and power transistor gate for a short self-timed period of time, and then couples the output terminal to a ground terminal, thereby driving the output terminal and power transistor gate up to ground potential. The output terminal and power transistor gate are then held at ground potential in anticipation of the next turn-on episode of the power transistor.

Abstract: A system includes a storage capacitor coupled between an input voltage source and a ground terminal, a voltage sensing circuit coupled to the input voltage source and to the storage capacitor, a first transistor coupled to the voltage sensing circuit, a current mirror circuit coupled to the first transistor, a diode coupled between the storage capacitor and the current mirror circuit, and a second transistor configured to couple between a gate of a power switching device and the ground terminal. A gate of the second transistor is coupled to the storage capacitor by way of the voltage sensing circuit.

Abstract: A gate driver integrated circuit drives an output signal onto its output terminal and onto the gate of a power transistor. In a turn-on episode, a digital input signal transitions to a digital logic high level. In response, the gate driver integrated circuit couples the output terminal to a positive supply voltage terminal, thereby driving a positive voltage onto the gate of the power transistor. In response to a high-to-low transition of the digital input signal, the driver drives a negative voltage onto the output terminal and power transistor gate for a short self-timed period of time, and then couples the output terminal to a ground terminal, thereby driving the output terminal and power transistor gate up to ground potential. The output terminal and power transistor gate are then held at ground potential in anticipation of the next turn-on episode of the power transistor.

Abstract: Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

Abstract: A semiconductor assembly includes a first FET integrated within the semiconductor assembly and comprising gate, source and drain terminals. The semiconductor assembly further includes a low voltage switching device integrated within the semiconductor assembly and being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal.

Abstract: Various embodiments may relate to a synchronous rectifier including at least one rectifier cell, to which power is supplied via a secondary winding of a transformer arranged between the input connections of the synchronous rectifier. The rectifier cell comprises a bipolar main switch operated in the inverse mode, wherein an energy store is provided in the base line of the bipolar main switch, which energy store, in conjunction with an auxiliary switch which is concomitantly controlled by the relevant secondary winding for the bipolar main switch, ensures that the main switch is switched off prior to the end of the inverse phase.

Abstract: Methods and systems for active charge control diodes with improved reverse recovery characteristics. An extra control terminal is added on the side of a diode nearest to its p-n junction. The control terminal connects to a control region which extends from the drift region to the cathode surface and which is most preferably separated from the cathode region by an insulated trench. During turn-off, the control terminal is most preferably driven negative relative to the cathode just before reversing the polarity of the applied external voltage.

Abstract: A switching control circuit includes voltage application means that applies a first voltage to a gate of a power device in a first period and applies a second voltage to the gate of the power device in a second period, wherein the first period starts when the power device is turned on; current detection means that detects whether a current flowing through the power device exceeds a threshold; and voltage decrease means that decreases the voltage with a first speed if the current detection means detects that the current exceeds the threshold in a second detection period, decreases the gate voltage with a second speed, lower than the first speed, if the current detection means detects that the current exceeds the threshold in a third detection period, and does not decrease the gate voltage if the current detection means detects that the current exceeds the threshold in the first period.

Abstract: A method to manufacture a vertical capacitor region that comprises a plurality of trenches, wherein the portions of the semiconductor region in between the trenches comprise an impurity. This allows for the trenches to be placed in closer vicinity to each other, thus improving the capacitance per unit area ratio. The total capacitance of the device is defined by two series components, that is, the capacitance across the dielectric liner, and the depletion capacitance of the silicon next to the trench. An increase of the voltage on the capacitor increases the depletion in the silicon and the depletion capacitance as a result, such that the overall capacitance is reduced. This effect may be countered by minimizing the depletion region which may be achieved by ensuring that the silicon adjacent to the capacitor is as highly doped as possible.

Abstract: Systems and methods are disclosed for operating a highly linearized resistance for a switch through use of a bootstrapped features. In one exemplary implementation, there is provided a method and system that implements a method for operating a circuit configured to provide a highly linearized resistance including receiving a signal via a bootstrapped switch, coupling the received signal to a gate if the received signal is high, receiving a signal via a switch control input coupled to a high impedance element. Moreover, the method includes coupling the high impedance element to the gate and turning off the switch via a gate turn off when the gate turn off pulls the gate low.

Abstract: A transistor being one of an IGBT and a MOSFET and arranged near a gate control circuit applies a gate control signal from the gate control circuit to the gate of a transistor arranged far from the gate control circuit. A gate control signal is applied via a resistive element to the transistor arranged near the gate control circuit.

Abstract: A switching arrangement for triggering a semiconductor switching element with a first electrode, a second electrode and a control electrode includes: a pulse generator for generating a control voltage input signal; a bias voltage capacitor; a first electrical resistor electrically connected in series with the bias voltage capacitor between first and second terminals of the pulse generator, wherein the control electrode is electrically connected to the bias voltage capacitor and the first electrical resistor, and the first electrode is electrically connected to the pulse generator and the first electrical resistor; and an additional capacitor connected in series to the pulse generator, the first electrical resistor, and the bias voltage capacitor.

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract: The present invention discloses a semiconductor switch comprising a switching unit. Said switching unit includes: a transistor having a drain, a gate and a source; a drain bias resistor coupled to the drain; a drain bias selecting circuit to couple the drain bias resistor with a first or a second drain bias according to the transistor's state; a gate bias resistor coupled to the gate; a gate bias selecting circuit to couple the gate bias resistor with a first or a second gate bias according to the transistor's state; a source bias resistor coupled to the source; and a source bias selecting circuit to couple the source bias resistor with a first or a second source bias according to the transistor's state, wherein the first and second drain biases are different, the first and second gate biases are different, and the first and second source biases are different.

Abstract: A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal and its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage that offsets parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. A high resistance direct path to ground on an output node of the power-on reset circuit prevents residual charge from causing an undesired misfire.

Abstract: Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.

Abstract: A method and apparatus for controlling a device in electronic equipment having a plurality of devices are provided. The apparatus includes a power supply for supplying power, a slave device including a driving circuit operated according to the supplied power for transmitting and receiving data to and from another device, a switching circuit for connecting the driving circuit to a ground terminal when the switching circuit is turned-on and for opening the driving circuit from the ground terminal when the switching circuit is turned-off, and a host device for transmitting a control signal for turning-on the switching circuit when driving the slave device and for turning-off the switching circuit when not driving the slave device. When the device is not driven, the switching circuit may open a driving circuit from a ground terminal, thereby cutting-off leakage of an electric current through the device.

Abstract: A gate drive circuit includes: an input port for receiving a control signal; an output port; a capacitor connected to the output port; a modulation unit which generates (i) a first modulated signal indicating timing of a first logical value of the control signal and (ii) a second modulated signal indicating timing of at least a second logical value of the control signal; a first electromagnetic resonance coupler which wirelessly transmits the first modulated signal; a second electromagnetic resonance coupler which wirelessly transmits the second modulated signal; a first rectifier circuit which generates a first demodulated signal by demodulating the first modulated signal, and outputs the first demodulated signal to the output port; and a second rectifier circuit which generates a second demodulated signal by demodulating the second modulated signal, and outputs the second demodulated signal to the output port.

Abstract: A gate drive circuit which drives a gate terminal of a semiconductor switching device includes: a first wireless signal transmitter which transmits an input first AC signal wirelessly; a second wireless signal transmitter which transmits an input second AC signal wirelessly; a first rectifier circuit which includes a first diode that rectifies an output signal from the first wireless signal transmitter; and a second rectifier circuit which includes a second diode that rectifies an output signal from the second wireless signal transmitter. A threshold voltage of the second diode is larger than a threshold voltage of the first diode.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: Disclosed herein is a resistor-sharing switching circuit, including: a first switching element turning on/off between a first input and output terminal and a second input and output terminal; a second switching element turning on/off between the first input and output terminal and a third input and output terminal; a signal transmission unit connected to both a control terminal of the first switching element and a control terminal of the second switching element; and a resistor having one end connected to the signal transmission unit and the other end connected to a control signal input terminal.

Abstract: A transistor being one of an IGBT and a MOSFET and arranged near a gate control circuit applies a gate control signal from the gate control circuit to the gate of a transistor arranged far from the gate control circuit. A gate control signal is applied via a resistive element to the transistor arranged near the gate control circuit.

Abstract: An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.

Abstract: In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.

Abstract: A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.

Abstract: An apparatus and method for protecting a switch from overvoltage transients that might otherwise occur when the switch is turned off. A transient-suppression controller controls a rate-of-change of voltage across a switch by delivering control signals to the switch. Controlling the rate-of-change of voltage enables controlled absorption of stored parasitic energy that might otherwise cause overvoltage transients. In some embodiments the switch is a MOSFET and the control signals are currents delivered to the gate of the MOSFET. In some embodiments, control is open-loop; in other embodiments closed-loop control is used to maintain essentially constant voltage across the switch as it turns off.

Abstract: A power circuit. One embodiment provides a circuit for driving a power transistor having a control electrode and a load path. The circuit includes a driver circuit configured to change the power transistor to a completely on or off state with the aid of a control signal supplied to the control electrode. A series circuit includes a semiconductor switching element and a capacitor. The series circuit is connected in parallel with the load path and the capacitor provides a supply voltage for the driver circuit.

Abstract: According to an exemplary implementation, a switching circuit includes a bipolar junction transistor, a base current supply configured to turn-on the bipolar junction transistor, and a base discharge switch configured to selectively draw current away from a base of the bipolar junction transistor so as to turn-off the bipolar junction transistor. The base discharge switch can further be configured to selectively prevent the base current supply from providing current to the base of the bipolar junction transistor. The base discharge switch may be coupled across the base of the bipolar junction transistor and an emitter of the bipolar junction transistor. The base discharge switch can further be configured to selectively cause the base of the bipolar junction transistor to have a base voltage substantially lower than an emitter voltage of the bipolar junction transistor.

Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.

Abstract: A circuit includes first to fifth resistors and first to third electronic switches. The circuit allows a signal from a first terminal of the second electronic switch to change from a low level to a high level gradually, and to change from a high level to a low level abruptly.

Abstract: Embodiments of a circuit, which includes a device and a switch, which is electrically coupled to the device, to control power applied to the device, are described. This switch includes a control terminal, which controls the switch, and two other terminals, which can receive power to be applied to the device. Moreover, the circuit is configured to apply a voltage to the control terminal to ensure the switch remains open when a supply voltage is applied to one of the two other terminals while powering-up the circuit, thereby preventing spurious application of the supply voltage to the device.

Abstract: A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.

Abstract: A load driving circuit in which the off-time Toff and the fall time Tf can be improved in turn-off operation of the N-channel type MOSFET used as a high side switch. The load driving circuit uses an N-channel type power MOSFET as a high side switch connected between a power supply and a load, including a comparator circuit for comparing a gate voltage of the power MOSFET with a power-supply voltage; and a shut-off circuit for discharging the gate terminal of the power MOSFET in turn-off operation of the power MOSFET, the rate of discharging the gate terminal of the power MOSFET performed with the shut-off circuit being set such that the discharge rate provided if the gate voltage Vg is lower than the power-supply voltage Vp is slower than the rate of discharging the same provided if the gate voltage Vg is higher than the power-supply voltage Vp.

Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.

Abstract: An ignitor semiconductor apparatus can include an output stage IGBT that controls the ON and OFF of the primary current of ignition coil, a sensing IGBT and a sensing resistance for detecting the current flowing through output stage IGBT, gate resistance and a current control circuit that detects the voltage across sensing resistance and controls the current flowing through output stage IGBT. First and second gate control circuits separately control the gate voltages of IGBT's such that the gate voltage of the output stage IGBT is higher than the gate voltage of the sensing IGBT, when the current flowing through output stage IGBT is larger than a predetermined current value, and such that the gate voltage of output stage IGBT is lower than the gate voltage of sensing IGBT, when the current flowing through output stage IGBT is smaller than the predetermined current value.

Abstract: A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.

Abstract: A control circuit controls a driving transistor connected in series with an electrical load between a power supply voltage and a ground. The control circuit includes a pull-up resistor connected at one end to a power supply voltage side of the driving transistor, a current detection resistor for detecting an electric current flowing from the driving transistor to the ground, a current mirror circuit including a starting transistor connected between the pull-up transistor and the current detection resistor. The current mirror circuit supplies a mirror current of the electric current. The control circuit further includes a current source circuit for supplying a driving current to a control terminal of the driving transistor in accordance with the mirror current to turn ON the driving transistor in response to an external control signal.

Abstract: There is provided a method for testing a switching circuit including a first FET connected between input/output terminals, a capacitor connected between one of the input/output terminals and the first FET, and a second FET that is connected in parallel with the capacitor and has a gate electrode connected to a ground terminal. The method includes, applying a potential that sets the second FET to a conducting state to the ground terminal, and testing a DC test for the first FET via the second FET.

Abstract: A control circuit controls a driving transistor connected in series with an electrical load between a power supply voltage and a ground. The control circuit includes a pull-up resistor connected at one end to a power supply voltage side of the driving transistor, a current detection resistor for detecting an electric current flowing from the driving transistor to the ground, a current mirror circuit including a starting transistor connected between the pull-up transistor and the current detection resistor. The current mirror circuit supplies a mirror current of the electric current. The control circuit further includes a current source circuit for supplying a driving current to a control terminal of the driving transistor in accordance with the mirror current to turn ON the driving transistor in response to an external control signal.

Abstract: Disclosed is a method for controlling the recombination rate in the base region of a bipolar semiconductor component, and a bipolar semiconductor component.

Abstract: A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes an auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt; an auxiliary FET in parallel with the main switching FET; the auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a predetermined maximum rate of decrease the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain; the auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.

Abstract: A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A trimming process is used to adjust the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition.

Abstract: A switch includes a switching transistor, a switching resistor, connected between a control terminal of the switching transistor and a switching control terminal, and an accelerating element. The accelerating element includes a resistance smaller than a resistance of the switching resistor, the accelerating element being adapted to be connected in parallel to the switching resistor upon switching of the switching transistor until a voltage at the control terminal of the switching transistor has reached a predetermined value.

Abstract: A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.

Abstract: A core voltage controlling apparatus suitable for a center processing unit (CPU) is provided. The apparatus includes a level shifting unit, a time-delay unit and a logic unit. An input terminal of the level shifting unit receives and shifts a first voltage signal, and an output terminal generates a second voltage signal, in which the first voltage signal indicates a power-on stable state, and the second voltage signal indicates a magnitude of the core voltage. The time-delay unit delays the second voltage signal to generate a third voltage signal. The logic unit is coupled to the time-delay unit for performing a logic operation on the third voltage and a fourth voltage signal transmitted by a power supply, and generating a fifth voltage signal for controlling a core voltage generator whether to provide the core voltage to the CPU or not, in which the fourth voltage signal indicates a power state.

Abstract: A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.