Abstract: A charge pump circuit receives a battery voltage of a power line, and outputs a raising voltage proportional to the battery voltage. A low voltage detecting circuit detects a low voltage state in which a detecting voltage obtained by dividing the raising voltage. Thus, it is possible to indirectly detect a low voltage state in which the battery voltage is lower than a predetermined threshold value. When the low voltage state is detected, a drive circuit turns off a MOSFET. At this time, the battery voltage is temporarily varied, but the charge pump circuit has a filter action and a delay action, whereby temporary variation does not easily appear in the raising voltage (detecting voltage), and an error in operation of the MOSFET can be prevented.

Abstract: A circuit and methods for use in increasing both bandwidth and switching speed of CML circuits. Two differential pairs are provided with one differential pair having a size that is a fraction of the other pair. Thus, one pair will have a size of W while the other will have a size of W/A. Each one of the first differential pair is coupled to at least one of the second pair. By reconfiguring the connections between the two pairs, circuits which have fast charging/discharging times and increased bandwidth are obtained.

Abstract: A driving circuit of this invention has a comparator that compares an input signal with a sampling signal to perform a pulse width modulation to the input signal, a driving transistor circuit that switches according to an output signal of the comparator, and a filter that reduces a switching frequency component of the driving transistor circuit. The switching frequency of the driving transistor circuit is a product of multiplication of a horizontal frequency. Also, a PLL circuit that locks the frequency of the sampling signal to the frequency acquired from multiplication of the horizontal frequency is provided. Therefore, when the driving circuit with the PWM method is built in a television set, beat interference can be prevented, avoiding an unpleasant view caused by the raster interference on the television screen.

Abstract: The invention utilizes a boost-strap method to improve switch operation in a design that is particularly advantageous for supplying high voltages within a low voltage design. A native NMOS transistor, a PMOS transistor, and a capacitor are connected in series between the high voltage source and the output, where the gate of the native NMOS is connect to the output. In an initialization phase, the plate of the capacitor connected to the output is precharged by receiving the input signal while the other plate of the capacitor is held near ground. In a subsequent enable phase, the native NMOS and PMOS transistors are turned on and the high voltage is supplied to the output.

Abstract: An improved interconnection switch using NMOS passgates is presented which allows the gate voltage of the NMOS passgate to be bootstrapped to a higher voltage than the initial voltage applied thereon so as to allow a higher logic HIGH signal to be passed. The stimulus for this bootstrapping is the transition of the logic signal at the input terminal of the NMOS passgate, which obviates the need for a separate external stimulus. Because the bootstrapping occurs as a result of the dynamic coupling between the gate terminal and the channel of the NMOS passgate, the voltage across the gate oxide does not exceed the magnitude of the logic HIGH signal, thereby rendering the use of thick-oxide devices unnecessary.

Abstract: The present invention relates to a bootstrap circuit. The present invention stably perform a read operation of a flash memory cell by constructing the bootstrap circuit to be clamped only at a high potential voltage ‘HVcc’ and to be normally operated at a low potential voltage source ‘LVcc’ to easily control on a word line boosting voltage, by sensing the high potential voltage source ‘HVcc’ and the low potential voltage source ‘LVcc’.

Abstract: An integrated circuit device is discussed that includes an data output driver having two modes of operation for driving a data bus. The output driver includes a circuits to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.

Abstract: A circuit for providing a control voltage to a switch includes a capacitor, a first pair of switches for coupling the capacitor to an input voltage source and a second pair of switches for coupling the capacitor to the switch. The first pair of switches is controlled by a control signal in response to the voltage across the capacitor in order to prevent overcharging the capacitor beyond a first predetermined level. The second pair of switches is controlled by a second control signal in response to the voltage across the switch in order to replenish the capacitor voltage when the capacitor voltage falls to a second predetermined level. The first and second pairs of switches are closed during non-overlapping time intervals in order to isolate the switch from the input voltage source, thereby preventing switching transients from affecting the input voltage source and permitting the circuit to be used to drive a variety of switch types arranged in a variety of configurations.

Abstract: If single-stage boosting is selected by a mode selection circuit, drive signals (S1, S3) are supplied as in-phase signals, and a switch (SW1) is kept closed by a control signal (S2), thereby controlling first and second charge pumps to boost the power supply voltage at the same timing. If two-stage boosting is selected, drive signals (S1, S3) are supplied as complementary signals, and the switch (SW1) is controlled by a control signal (S2), thereby controlling the first charge pump to boost the power supply voltage and controlling the second charge pump to further boost the boosted voltage. By this operation, even if single-stage boosting is selected, the first and second charge pumps can be used as a single charge pump.

Abstract: The present invention relates to a logic gate circuit capable of reducing sub-threshold leakage current by applying the reverse voltage to the gate of a turned-off MOS device. The logic gate circuit in accordance with the present invention includes a CMOS logic gate having PMOS devices and NMOS devices with a low threshold voltage, a first voltage generator applying a first reverse voltage to the PMOS device of the CMOS logic gate during a pull-down operation, and a second voltage generator outputting a second reverse voltage to the NMOS device of the CMOS logic gate during a pull-up operation. The first voltage generator outputs a voltage greater than the source voltage by the threshold voltage to the first MOS device when the second MOS device performs a pull-down operation, and the second voltage generator outputs a voltage smaller than the earth voltage by the threshold voltage when the first MOS device performs a pull-up operation.

Abstract: An improved gate drive circuit powered by a DC source voltage, the drive circuit having an isolated output stage with a parallel-connected by-pass capacitor and a switched input capacitor circuit that maintains a charge on the by-pass capacitor for driving the gate of a controlled MOS transistor while isolating the by-pass capacitor from the source voltage. In a fully isolated embodiment of the improved gate drive circuit, a bank of controlled switches alternately couples the input capacitor to the source voltage and the by-pass capacitor, while in another embodiment, uni-directional isolation is achieved by replacing one or more of the controlled switches with diodes.

Abstract: A booster is provided with first to k-th (k is an even number) transistors connected to one another in series, first to k-th capacitors each having an end connected to the gate and source of each of the first to k-th transistors, and a clock driver which supplies clock signals out of phase with one another to the other ends of the first to k-th capacitors. The clock driver simultaneously supplies low-level clock signals to two or more adjacent capacitors out of the first to k-th capacitors.

Abstract: A synchronized boosted voltage generator includes a pump controller for receiving an externally applied clock signal and an externally applied control signal, and outputting a charging control signal, a precharging control signal and a charge transfer control signal, a pumping capacitor for receiving the charging control signal and charging a node, a precharge circuit for receiving the precharging control signal and clamping a potential at the node so as not to fall below a predetermined voltage, a charge transfer transistor for transferring to a load the potential charged on the node and the pumping capacitor, respectively, and a charge transfer circuit for receiving the charge transfer control signal and outputting a pumping control signal for controlling the charge transfer transistor. The generator employs an internal clock signal generated by a ½ frequency divider from an externally applied clock signal, whereby a fixed duty cycle clock is to generate a stable boosted-voltage.

Abstract: A voltage generation circuit generates an output voltage at an output node thereof by sharing charge between a first node and a second node so as to increase a potential at the second node from a first voltage to a second voltage. The first node is charged to a third voltage and the second node is driven to a fourth voltage that is greater than the third voltage. Charge is shared between the first node and the second node so that the first and second nodes reach a common fifth voltage, which is between the third and fourth voltages. The first node is driven to a sixth voltage, which is greater than the fourth voltage. Charge is shared between the first node and the output node to generate the output voltage thereat.

Abstract: A multi-stage circuit has a first stage and a second stage that both share a bootstrap module. More specifically, the first stage has an output switch, and the second stage has an input switch in communication with the output switch. The multi-stage circuit thus includes the bootstrap module in communication with both the output switch and the input switch. The bootstrap module is capable of applying a voltage to both the input and output switches, while the applied voltage ensures that the first and second switches remain in an on state at specified times.

Abstract: An improved word line boost circuit suitable for use on integrated circuits such as flash memory devices includes a two step boosting circuit with a floating circuit node. A first circuit provides an initial boost of the output voltage from a precharged voltage. Part of the first circuit is floated, lessening a load on a second circuit. Then, the second circuit provides a second boost of the output voltage with increased power efficiency. A time delay separates the onset of the second boosting operation from the onset of the first boosting operation so as to define a two-step boost.

Abstract: A multiple core charge pump includes a plurality of switches disposed between the taps of a delay chain and the individual charge pump cores. When the switches are closed, an oscillating clock signal is permitted to propagate through the delay chain and reach individual charge pump cores via the taps. A regulator senses the output voltage of the charge pump. When the output node reaches the desired voltage, the regulator simultaneously causes each of the switches to open, decoupling each of the charge pump cores from the taps of the delay chain, and preventing signals which are still propagating through the delay chain from triggering the charge pump cores. A transition detector may also be used to narrow the pulse width of the oscillating clock signal which is applied to each switch.

Abstract: An integrated voltage source includes a charge pump having multiple charge pump stages connected in series. A first one of the these charge pump stages is connected to the high voltage output of the charge pump, and the remaining charge pump stages are coupled to this first charge pump stage in a manner such that substantially all the charge pumped by all of the additional charge pump stages is also pumped by the first charge pump stage. In one mode of operation, the first charge pump stage and at least one additional charge pump stage are enabled. In another mode of operation, the first charge pump stage and at least two additional charge pump stages are enabled. A control circuit determines the mode of operation and, therefore, the number of charge pump stages that are enabled.

Abstract: The present invention relates to a potential generation circuit of charge pump type, this circuit including at least two stages formed of capacitors and of circuitry for isolating or interconnecting the capacitors, to generate an output potential by charge transfer between the stages. The circuit is driven by two control potentials oscillating between a first and a second value. The circuit includes a self-oscillating control circuit to generate control potentials, to eliminate time delays between charge and discharge phases.

Abstract: The diode drops associated with the output voltage from a conventional charge pump are eliminated in the present invention with a dual-chain charge pump that utilizes the pumped voltages from each charge pump chain to drive the gates of the other charge pump chain. As a result, the voltages on the gates of the transistors are pumped up to a level such that there is no threshold voltage drop across the transistor, and thus, making it behave like an ideal switch.

Abstract: A leakage current compensation system and method is disclosed that reduces frequency spurs and phase offset in a frequency synthesizer. The leakage current is determined based on the phase offset of the frequency synthesizer relative to a reference clock. A leakage current compensation circuit provides a leakage current compensation signal to the frequency synthesizer at the loop filter terminals to minimize the phase offset.

Abstract: An integrated switching mode power supply (10) has a follower device (59) providing a supply voltage (VBOOT) to a node (70) of the power supply. A driver circuit operates in response to an input signal (VCONTROL) and has an output (40) for providing a drive signal (VDRIVE) that bootstraps the node to a potential greater than the supply voltage.

Abstract: A voltage level translator is provided that operates over a wide range of voltage levels at a fast translation speed. The voltage level translator includes an input terminal that receives an input signal and a capacitor having its first terminal coupled to the input terminal. A clamp circuit is coupled to the input terminal and to the second terminal of the capacitor and operable to provide a signal on the second terminal of the capacitor in response to a first voltage level of the input signal. A voltage source circuit is coupled to the clamp circuit and to the second terminal of the capacitor and provides a signal on the second terminal of the capacitor in response to a second voltage level of the input signal. An output buffer has a first input terminal coupled to the first terminal of the capacitor and a second input terminal coupled to the second terminal of the capacitor.

Abstract: A driver circuit transmits a signal to a receiver circuit through a signal transmission line. The driver circuit has an output driver, a front driver, and a level adjuster. The front driver drives the output driver, and the level adjuster adjusts the output level of the front driver. The output driver generates a signal whose level is variable in response to an output level of the front driver.

Abstract: Output nodes (Noutn, Noutp) outputting a negative potential (VN) and a positive potential (VPS) respectively are supplied with fixed potentials by reset circuits respectively when unused. Switches (SW2, SW3) conduct when generating the negative potential, while switches (SW1, SW4) conduct when generating the positive potential. Reference potentials for the generated potentials are supplied to internal nodes N10, N20) through the switches (SW1, SW3) respectively. Poly-diode elements are employed for a voltage generation part, whereby a charge pump circuit capable of generating positive and negative voltages can be implemented without remarkably changing a fabrication method.

Abstract: An input buffer includes an amplifier circuit, such as a differential amplifier circuit, inverting amplifier circuit or pull-up/pull-down amplifier circuit. A momentary boost circuit is coupled to an input buffer input terminal, an input terminal of the amplifier circuit, and an output terminal of the amplifier circuit, and is operative to generate a boosted input signal at the input terminal of the amplifier circuit from an input signal at an input buffer input terminal for an interval that is terminated responsive to an output signal at the output terminal of the amplifier circuit.

Abstract: The present invention concerns a bootstrap circuit in DC/DC static converters comprising first current generator means controlled to close in function of a first signal and a recharge circuit of a capacitor. The bootstrap circuit has the characteristic of comprising second current generator means controlled to close with a second signal synchronous with the first signal, the second signal has times and modalities such to send to the capacitor recharge currents such to compensate the discharge of the capacitor itself.

Abstract: A universal zero voltage transition switching cell using a small choke, a pair of switches, and a capacitor is revealed. The application of the universal zero voltage transition switching cell to any of a wide variety of hard switching pulse width modulated power converter topologies yields identical power converters with zero voltage switching properties, without the requirement that the magnetizing current in the main power choke be reversed during each switching cycle. In the subject invention the energy required to drive the critical zero voltage switching transition is provided by the small choke that forms part of the universal zero voltage transition switching cell. The application of the universal zero voltage transition switching cell to buck, boost, buck boost, Cuk, Wittenbreder, flyback, forward, and SEPIC converters is shown.

Abstract: To a first node at a boosted potential, a control circuit is connected for controlling a potential of the first node so that the potential of the first node does not exceed a predetermined potential, wherein the control circuit has a capacitor connected between the first node and a second node, a first switching transistor having a source-drain current path inserted between the second node and the ground node and a gate to which a control signal is input, and a second switching transistor having a source-drain current path inserted between the first node and the ground node, and a gate connected to the second node.

Abstract: An apparatus and method for boosting a transmission gate by charging a pair of capacitors and using the coupling effect of that pair of capacitors to overdrive the gate inputs of NMOS and PMOS transistors of a transmission gate to turn on the transistors more strongly and speed the passage of data signals.

Abstract: A buffer circuit includes an amplifier, a pass gate circuit and a level shifter. The pass gate circuit communicates an input signal to the amplifiers and includes a terminal to control the communication. A level shifter furnishes a control signal to the terminal of the pass gate circuit and regulates the control signal based on a magnitude of the input signal.

Abstract: A circuit is provided that has an output buffer connected to one of a plurality of output pads. A power source is connected to one of the plutrality of output pads. A first pair of capacitors is connected to the power source. A second pair of capacitors is connected to the first pair of capacitors and the power source. A first pair of signal sources are connected to the first pair of capacitors. A second pair of signal sources connected to the second pair of capacitors. The first pair of signal sources and the second pair of signal sources control discharge to the power source and recharge to the power source of the first pair of capacitors and the second pair of capacitors to cancel out noise caused by either a voltage or current switching transient. Also, a method is provided for sending data to an output buffer, determining data to be clocked the next cycle, and controlling a charge-pump circuit to compensate for a voltage transition from one of high-to-low and low-to-high.

Abstract: A semiconductor integrated circuit capable of achieving drain current and transconductance required for driving an analog switch even after lowering a supply voltage. The circuit includes a boosting section for generating a voltage equal to or greater than the supply voltage, and an output section for outputting a voltage generated by the boosting section according to an input signal. The boosting section includes a capacitor for storing electric charges equivalent to a difference between the voltage equal to or greater than the supply voltage and the supply voltage. Accordingly, a voltage equal to or greater than the supply voltage can be applied to the analog switch requiring large transconductance. Therefore, even if the supply voltage is decreased, a percentage of a reduction of the transconductance can be relatively low, whereby a voltage of electronic equipment can be lowered.

Abstract: An input buffer capable of achieving quick response. The input buffer includes first and second direct-current (DC) voltage controllers and first and second drivers. The first and second DC voltage controllers generate first and second alternating current (AC) signals having AC voltage components of the buffer input signal reflected thereon, respectively. The first driver drives the voltage level of a buffer output signal to the level of a first voltage, that is, a power supply voltage, in response to the first AC signal. The second driver drives the voltage level of a buffer output signal to the level of a second voltage, that is, a ground voltage, in response to the second AC signal. The first and second AC signals respond to a buffer input signal quickly. The first and the second drivers drive the levels of the buffer output signal to the power supply voltage level and the ground voltage level quickly and by a large amount.

Abstract: Method and circuitry for efficiently boosting voltage for low power supply applications. In one embodiment a phase boosting circuit that boosts a clock signal to substantially twice the power supply voltage level in a single half-cycle is implemented. The circuit eliminates the need for depletion transistors and can thus be implemented using conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes. A novel voltage summing circuit allows the phase doubler to achieve greater boosting capability for applications with ultra low power supply voltages.

Abstract: A nonlinear resistor circuit utilizes capacitively-coupled multi-input MOSFETs in order to enable integration thereof by a standard CMOS process, and which can realize two types of nonlinear resistance characteristics; i.e., A-type and V-type nonlinear resistance characteristics. The circuit includes a core circuit which comprises enhancement-type N-channel and P-channel MOSFETs with source terminals being connected with each other.

Abstract: A low cost half bridge driver IC fabricated in the process technology with a minimum or reduced number of masking steps to implement all the blocks and without the use of the low threshold voltage CMOS. The half bridge driver IC uses a universal 12 Volt supply for all of the blocks with reference to the ground or to the half bridge output. Furthermore, the low differential current from high voltage level shifter transistors of the half bridge driver IC can provide enough voltage swing to set or reset the latch when high threshold voltage DMOS transistors are used in the pulse filter.

Abstract: The boosted switch device comprises an input terminal and an output terminal; a supply line set to a supply potential; a ground line set to a ground potential; a transistor connected between the input and output terminals; a capacitor; and a switch device connecting the capacitor between the supply line and the ground line, when the transistor is off, and between the input terminal and the control terminal of the transistor, when the transistor is on.

Abstract: Standby leakage reduction circuitry that uses boosted gate drive of a leakage control transistor during an active mode. A circuit block includes a first leakage control transistor coupled to receive a first supply voltage and coupled in series with an internal circuit block that performs a particular function. A gate drive circuit is included to apply a first boosted gate drive voltage to a gate of the first leakage control transistor during an active mode of the internal circuit block. The gate drive circuit furthers applies a standby gate voltage to the gate during a standby mode of the internal circuit block, the standby gate voltage to cause a gate to source voltage of the leakage control transistor to be reverse-biased.

Abstract: If single-stage boosting is selected by a mode selection circuit, drive signals (S1, S3) are supplied as in-phase signals, and a switch (SW1) is kept closed by a control signal (S2), thereby controlling first and second charge pumps to boost the power supply voltage at the same timing. If two-stage boosting is selected, drive signals (S1, S3) are supplied as complementary signals, and the switch (SW1) is controlled by a control signal (S2), thereby controlling the first charge pump to boost the power supply voltage and controlling the second charge pump to further boost the boosted voltage. By this operation, even if single-stage boosting is selected, the first and second charge pumps can be used as a single charge pump.

Abstract: A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its voltage loss.

Abstract: A booster circuit uses a source voltage to generate a boosted voltage that is higher than the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a signal voltage applied to an input terminal. The first capacitor is discharged to boost the voltage at a boosting node, whereas the second capacitor is discharged to boost the voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an “H” level to an “L” level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced by the charging of the second capacitor, a transistor is deactivated in response to the voltage at the output terminal.

Abstract: A level shifting circuit comprises a first insulated-gate transistor which has its gate provided with an input signal and a second insulated-gate transistor which has its drain connected with the source of the first insulated-gate transistor. The second insulated-gate transistor may have the same conductivity type as the first insulated-gate transistor. A voltage not affected by factors such as the manufacturing process used to make the device, operating temperature, or supply voltage is applied to the gate of the second insulated-gate transistor. A ratio of gate channel width to gate channel length for these two insulated-gate transistors are set to a same value, thereby allowing the level-shifting circuit to output a constant predetermined value; and which is not affected by the aforementioned manufacturing process, operating temperature, and supply voltage factors.

Abstract: The present invention relates to a charge-pumping circuit for low-supply voltage. A small charge-pumping circuit was added at the gates of the original Dickson charge-pumping circuit's each stage for bias voltage and the first transistor group was added between well and gate. The second transistor group was added between the gate and drain of original trans0istor. Thus, the charge-pumping circuit for low-supply voltage can supply a higher positive or negative voltage.

Abstract: There is provided a level shift circuit which includes an input terminal for receiving a logic input signal changing between a first voltage and a reference voltage. An output terminal provides a logic output signal changing between a second voltage and the reference voltage. A pull-up transistor has a control electrode and a pair of controlled electrodes. The controlled electrodes are coupled between the second voltage and the output terminal. A pull-down transistor has a control electrode and a pair of controlled electrodes. The control electrode of the pull-down transistor is coupled to the input terminal, and the controlled electrodes of the pull-down transistor are coupled between the reference voltage and the output terminal. A charge/discharge circuit charges the control electrode of the pull-up transistor with the second voltage when the logic input signal is changed from the reference voltage to the first voltage.

Abstract: The invention pertains to an improved method and circuit arrangement for signal processing. The invention is advantageously used for processing analog signals in applications in which low energy consumption is of the essence. An idea of the invention is to achieve an integrator topology where the active charge-transferring element is a preferably source-follower-type transistor in which one input terminal is arranged so as to be substantially independent of the input signal and in which the essential signal path elements of the circuit topology are connected in a fixed manner. The circuit arrangement according to the invention is realized preferably in such a manner that it comprises separate transistors for sampling and charge transfer. Thus it is possible to connect an input signal in a fixed manner to an input terminal of the sampling transistor, and an input terminal of the charge-transferring transistor can be connected in a fixed manner to a constant voltage.

Abstract: A bootstrapped CMOS driver for driving a large capacitive load, which employs a drive unit consisting of pull-up and pull-down devices, and a pull-up section and a pull-down section performing pull-up and pull-down operations, respectively, in accordance with a level of an input signal. The pull-up section and the pull-down section can be embodied as a plurality of MOS devices and dual bootstrap capacitors controlled by a single input signal or as a plurality of MOS devices and a single bootstrap capacitor controlled by two input signals.

Abstract: Provided is a method of operating a charge-pump, which may be implemented in IC devices such as digital signal processors (DSPs) and mixed signal analog circuits. The method includes the steps of charging a first capacitor, and then choosing between two switching sequences based on the relative values of the input voltage and the output voltage. When the input voltage is determined to be greater than the output voltage, the method applies a first switching sequence to discharge the first capacitor into a second capacitor by first partially discharging the first capacitor into the second capacitor, then fully discharging the first capacitor into the second capacitor. When the input voltage is determined to be less than or equal to the output voltage, the method uses a second switching sequence to prevent the discharge of the second capacitor into the first capacitor by electrically isolating the first capacitor.

Abstract: A capacitively isolated input system that permits sensing of an input voltage with a below-ground value or a below-substrate voltage value. Multiple input signals are received, and each input signal is connected to cross-connected switching components. Switched output signals are capacitively connected to additional switching components and to a sensing amplifier. This system allows the sensing amplifier to receive capacitively isolated input signals and to provide corresponding output signals at voltages no lower than ground voltage.

Abstract: A voltage generation circuit includes a boost circuit boosting a power supply voltage and transmitting the boosted voltage to an output transistor according to a boost control signal, a gate boost circuit boosting a gate voltage VHbst of the output transistor according to the boost control signal, a clamp circuit having a function of clamping VHbst to a prescribed voltage, and an output transistor receiving VHbst at its gate and provided to connect the boost circuit and a voltage supply node. The clamp circuit is activated according to the boost control signal.