Abstract: A device includes source circuitry comprising a first portion of a current mirror and a first transistor. The device also includes load circuitry comprising a second portion of the current mirror and a second transistor, wherein the load circuitry is disposed at a distance from the source circuitry. The device further includes a path coupled to a first gate of the first transistor and to a second gate of the second transistor, wherein the path provides a predetermined voltage to both of the first gate of the first transistor and to the second gate of the second transistor.

Abstract: Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: A communication device capable of transmitting and receiving high-potential signals is provided. The communication device includes a duplexer including first to fourth transistors, a transmission terminal, a reception terminal, an antenna terminal, and first and second control terminals. The transmission terminal is electrically connected to one of a source and a drain of each of the first and second transistors. The reception terminal is electrically connected to one of a source and a drain of each of the third and fourth transistors. The antenna terminal is electrically connected to the other of the source and the drain of each of the second and fourth transistors. The first control terminal is electrically connected to gates of the second and third transistors. The second control terminal is electrically connected to gates of the first and fourth transistors. A semiconductor of each of the first to fourth transistors contains a metal oxide.

Abstract: According to aspects of the disclosure, a method and system are provided for transferring a load between a primary power source and a secondary power source. In accordance with the disclosure, a method of transferring a load between a first power source and a second power source includes analyzing a plurality of power sources to identify one or more power sources providing a power greater than a threshold value. The method also includes selecting a power source from the identified one or more power sources providing power greater than the threshold value. The method further includes connecting the selected power source to a transfer mechanism. The method still further includes actuating the transfer mechanism, using power provided to the transfer mechanism by the selected power source, to transfer the load from a connection with the first power source to a connection with the second power source.

Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

Abstract: System and methods for reducing nonlinearity in radio frequency (RF) circuitries (e.g., RF switch circuitry and/or RF amplifier circuitry) are provided. A high-linearity RF integrated circuit device includes an input port; an output port; nonlinear circuitry arranged on a signal path between the input port and the output port; a shunt path including signal adjustment circuitry; and adjustable nonlinearity generation circuitry coupled to the signal adjustment circuitry, the adjustable nonlinearity generation circuitry including one or more metal-oxide-semiconductor (MOS) devices; and at least one nonlinearity generation activation element connected in parallel with a source terminal and a drain terminal of a first MOS device of the one or more MOS devices and responsive to an activation control signal. The nonlinear circuitry may include at least one of switching circuitry or amplifier circuitry. The shunt path may be coupled to the input port or the output port.

Abstract: In a drive circuit, a differential circuit unit is configured such that resetting of an output voltage of the differential circuit unit is carried out, and the resetting of the output voltage of the differential circuit unit is cancelled. A value of the difference between first and second divided terminal voltages at a timing of cancelling the resetting is defined as a reference voltage. The differential circuit unit generates, as the output voltage, a product of a voltage change from a reference voltage and a predetermined amplification factor after cancelling of the resetting of the differential circuit unit. A signal generator generates a gate signal for the upper- and lower-arm switches in accordance with a value of the output voltage of the differential circuit unit while the upper- and lower-arm switches are in an off state.

Abstract: A voltage limiter incorporated in a radio frequency identification (RFID) integrated circuit (IC) for a RFID tag is disclosed. The RFID IC includes a radio frequency (RF) rectifier and a clock generator. The RF rectifier is configured to convert an AC signal received from an antenna incorporated in the RFID tag to a DC signal. The voltage limiter includes a current sink device coupled between output of the RF rectifier and ground and a charge pump to control conduction of current through the current sink device to limit output voltage of the RF rectifier to a predefined voltage level.

Abstract: A semiconductor device that tests and/or monitors each of batteries provided in an assembled battery is provided. The semiconductor device includes a hysteresis comparator and a circuit, and the circuit has a function of setting a high-level side threshold voltage and a low-level side voltage of the hysteresis comparator. The circuit includes first and second capacitors. A first terminal of the first capacitor is electrically connected to a high-level side reference potential input terminal of the hysteresis comparator and a first terminal of the second capacitor is electrically connected to a low-level side reference potential input terminal of the hysteresis comparator.

Abstract: A method comprises configuring a power converter to operate as a boost converter, the power converter comprising a low side switch and a high side switch, during a first dead time after turning off the low side switch and before turning on the high side switch, configuring the power converter such that a current of the power converter flows through a high speed diode, and after turning on the high side switch, configuring the power converter such that the current of the power converter flows through a low forward voltage drop diode.

Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.

Abstract: The objective is to provide a function of detecting loss of a current detection function, at a time when a switching device has an open failure, in an arm that has the current detection function and a temperature detection function and in which two or more switching devices are connected in parallel with one another. A switching apparatus includes a current detector and a temperature detector provided in at least one of the two or more switching devices that are connected in parallel with one another and a controller that determines an overcurrent in the switching device in which the current detector is provided, that determines an overheating state and a temperature-rising failure in the switching device in which the temperature detector is provided, based on an output of the temperature detector, and that controls the switching devices.

Abstract: An integrated circuit includes a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node, and generates an initiation voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitive unit at the first node and coupled to a second capacitive unit at a second node. The first voltage generation circuit generates, in response to the initiation voltage at the first node, a first control signal based on a first supply voltage to the second voltage generation circuit. The second voltage generation circuit generates, in response to the first control signal received from the first voltage generation circuit, a second control signal to the first node, based on a second supply voltage.

Abstract: A doorbell chime bypass circuit includes a first node, a second node, and a bi-directional FET switch in series with the first node and the second current node. The bi-directional FET switch includes a first FET and a second FET in series, and is configured to cease conducting current between the first and second nodes when gate voltages of the first and second FETs are below a cut-off threshold. The bypass circuit further includes a sensing circuit configured to determine a level of current flowing through the bi-directional FET switch, and a switch controller configured to set the gate voltages of the first and second FETs to a level below the cut-off threshold when the sensing circuit senses that the level of current meets a doorbell press current threshold, causing the bi-directional FET switch to cease conducting current between the first and second nodes.

Abstract: A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.

Abstract: The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.

Abstract: The present description concerns a method of controlling a bidirectional switch (200), including: first (210 1) and (210 2) field-effect transistors electrically in series between first (262 1) and second (262 2) terminals of the bidirectional switch; third (614) and fourth (612) field-effect transistors electrically in series between said first and second terminals of the bidirectional switch, a first connection node (252) in series with the first and second transistors being common with a second connection node (616) in series with the third and fourth transistors, including steps of: receiving a voltage (V200) between the terminals of the bidirectional switch; detecting, from the received voltage, a first sign of said voltage; at least while the first sign is being detected, coupling the first terminal to said first node (252), potentials of control terminals of the first, second, third, and fourth transistors being referenced to the potential (REF) of the first and second nodes having common sources of th

Abstract: To provide a semiconductor device signal transmission circuit for drive-control, a method of controlling a semiconductor device signal transmission circuit for drive-control, a semiconductor device, a power conversion device, and an electric system for a railway vehicle capable of preventing malfunction due to noise while speeding up or reducing loss of a switching operation. The semiconductor device signal transmission circuit for drive-control that is connected between a semiconductor device constituting an arm in a power conversion device and a drive circuit configured to drive the semiconductor device, including: an inductor; and an impedance circuit including a switch and connected in parallel with the inductor.

Abstract: A power transistor module includes a power transistor device and a control circuit. The control circuit is electrically connected to the power transistor device for providing at least one gate voltage to drive the power transistor device, and adjusting the at least one gate voltage in response to an output power of the power transistor module. When the output power is greater than a predetermined power load, the at least one gate voltage has a first swing amplitude; and when the output power is less than or equal to the predetermined power load the at least one gate voltage has a second swing amplitude less than the first swing amplitude.

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative VGS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.

Abstract: Methods and devices to mitigate de-biasing caused by an undesired gate induced drain body leakage current in FET switch stacks are disclosed. The devices utilize diode stacks to generate discharge paths for the undesired current. The disclosed teachings are applicable to both shunt and series implementations of FET switch stacks.

Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the abovementioned performance improvements are maintained.

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Abstract: The present disclosure relates to a power circuit including a power supply circuit and a first control circuit. The power supply circuit is electrically connected to a power supply source and a power terminal for selectively providing power to the power terminal. The first control circuit is electrically connected to the power supply circuit and configured to receive a detection signal to enable or disable the power supply circuit. When the detection signal is enabled, the first control circuit provides a first enable signal to the power supply circuit, so that the power supply circuit provides power to the power terminal. When the detection signal is at the disable level, the first control circuit is configured to provide the first disable signal to the power supply circuit, so that the power supply circuit stops providing power from the power supply source to the power terminal.

Abstract: A negative voltage generation circuit 200 includes a first DC voltage source 201 having a positive terminal connected to a first node N1 (Vin), a first diode 202 having a cathode connected to a negative terminal of the first DC voltage source 201 and an anode connected to an output terminal of a first negative voltage VC1 (fourth node N4), and a first capacitor 204 having a first terminal connected to an output terminal of the first negative voltage VC1 and a second terminal connected to a second node N2 (Vs_high), so as to supply the first negative voltage VC1 to a first driver 20 that performs switching control of a first NMOSFET 11 (first switch element) connected between the first node N1 (Vin) and the second node N2 (Vs_high).

Abstract: This invention relates to a driving circuit with electronic switches in serial connection structure, and this driving circuit includes: electronic switch module and active drive module, electronic switch module includes: n pcs electronic switches in serial connection, and n pcs electronic switches D and S terminal connected in series in turn; active drive modules includes: n pcs active drive circuits; and in this invention, the power supply and the driving pulse signal of the electronic switch K2 to Kn are obtained successively from electronic switch K1, and the electronic switch K1 to Kn is on and off in turn; The n pcs electronic switches have nanosecond level of the switching performance of the active circuit, which are suitable for the high frequency high power gate drive circuit when n pcs electronic switches series structure is used.

Abstract: According to an embodiment(s), a current detection circuit has first and second main electrodes, a vertical structure output transistor that includes a first control electrode where a control signal is supplied thereto, a third main electrode that is connected to the first main electrode, a second control electrode that is connected to the first control electrode, and a vertical structure detection transistor that has a fourth main electrode. The current detection circuit has a voltage supply circuit that supplies a divided voltage of a voltage between the first and second main electrodes to the fourth main electrode.

Abstract: Systems and methods for efficiently allowing current to bypass a group of solar cells having one or more malfunctioning or shaded solar cells without overwhelming a bypass diode. This can be done using a switch (e.g., a MOSFET) connected in parallel with the bypass diode. By turning the switch on and off, a majority of the bypass current can be routed through the switch, which is configured to handle larger currents than the bypass diode is designed for, leaving only a minority of the current to pass through the bypass diode.

Abstract: An auxiliary resonant soft-edge pole inverter circuit is provided. The power inverter circuitry may include a first pair of capacitors in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch and a diode in parallel and sharing a common central node with the first pair of capacitors. The power inverter circuit may further include a first pair of auxiliary switches connected in series with a first pair of inductors, respectively, to generate resonant current from a DC power source, the first pair of inductors also sharing the common central node. The power inverter circuitry may further include a second pair of auxiliary switches connected in series with a second pair of capacitors, respectively, the second pair of auxiliary switches also sharing the common central node, the circuit producing an alternating current output at the common central node.

Abstract: A gate drive apparatus including a gate drive unit configured to drive a gate of a switching device, a peak detection unit configured to detect that a voltage across main terminals applied between the main terminals of the switching device during a turn-off period of the switching device is at a peak, and a driving condition changing unit configured to increase a change speed of a gate voltage of the switching device caused by the gate drive unit, in response to a detection that the voltage across main terminals is at a peak.

Abstract: A switching element 1 has a gate terminal connected to an output end 123 of a driving circuit 12 via a capacitor 11 and a resistor 13 connected in parallel. The switching element 1 has a source terminal connected to the driving circuit 12 via a capacitor 14. A diode 15 connected in series with a resistor 16 has a cathode terminal connected to a section between the capacitor 11 and the resistor 13, and the gate terminal and an anode terminal connected, via the resistor 16, to a section between the source terminal and the capacitor 14.

Abstract: A voltage equalization method for use in a radiofrequency switch having multiple transistors connected in series and the radiofrequency switch. In the voltage equalization method, capacitors are additionally provided as parasitic capacitances between source electrodes and drain electrodes of transistors (M1-MN) connected in series to compose a radiofrequency switch, and voltage drop uniformity is implemented for the transistors (M1-MN) by adjusting the parasitic capacitances of the transistors (M1-MN). By means of different combinations of the positions, sizes, and spacing of metal bars on a first metal layer (1) and on a second metal layer (2), the parasitic capacitances between the source electrodes and the drain electrodes of the transistors (M1-MN) can be finely adjusted, thus increasing the voltage drop uniformity of the transistors (M1-MN). The method uses less transistors to accomplish the design of the radiofrequency switch.

Abstract: Provided is an analog switch circuit that allows switching between an on-state and an off-state according to a control signal, the analog switch circuit including a main input terminal that receives an input voltage, an output terminal, an upper-side power supply terminal that receives an upper supply voltage, a lower-side power supply terminal that receives a lower supply voltage, a main N-channel MOS transistor and a main P-channel MOS transistor that are disposed in parallel between the main input terminal and the output terminal, and a controller that includes a voltage generating circuit that generates a high-side voltage according to the upper supply voltage and the input voltage and a low-side voltage according to the input voltage and the lower supply voltage. The controller can control a gate and a back gate of each of the main N-channel and P-channel MOS transistors based on the high-side and low-side voltages.

Abstract: A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.

Abstract: An NMOS transistor performs electrical conduction or cut-off between a drain and a source by controlling a potential at a gate. A resistive element is connected between a back gate of the NMOS transistor and a high-frequency ground. A first switching circuit is disposed in parallel with the resistive element between the back gate and the high-frequency ground and causes a short circuit between the back gate and the high-frequency ground upon cut-off.

Abstract: A memory cell arrangement is provided that may include: a read-out circuit and a memory cell including: a first terminal, a second terminal, and a third terminal; the memory cell may be configured to control current flow between the second terminal and the first terminal as a function of a first voltage present at the first terminal, a third voltage applied at the third terminal, and a memory state of the memory cell. The read-out circuit is configured to: generate a characteristic voltage at the bitline by applying the third voltage at the third terminal and a second voltage at the second terminal, the characteristic voltage representing the memory state of the memory cell, and to determine the memory state of the memory cell based on sensing the characteristic voltage.

Abstract: A device includes a first diode and a second diode connected in series between a first terminal and a second terminal of a switching element, wherein the switching element is a unidirectional device and an anode of the first diode is directly connected to an anode of the second diode, a third diode connected between the first terminal and the second terminal of the switching element and a switch connected in parallel with the first diode.

Abstract: Embodiments of the disclosure include a switch having an on-state resistance that varies based on a temperature coefficient of the switch and an overcurrent protection circuit coupled to the switch and having an adjustable overcurrent threshold level determined based on an adjustable voltage generated by the overcurrent protection circuit, the adjustable voltage generated based on the temperature coefficient of the switch.

Abstract: The disclosure relates to an electronic module comprising a source terminal for receiving an input current from an electrical voltage source and comprising an electrical input capacitance which is effective with respect to the source terminal, wherein the input capacitance is connected to the source terminal via a transistor circuit. The disclosure additionally provides that the transistor circuit is configured to conduct the input current via a respective switching path of at least one transistor, and a control device is configured to switch, during the switch-on process for limiting the input current, a control voltage at a respective control terminal of the at least one transistor, in a plurality of steps, from an off value at which each switching path is switched off, to a connection value at which a contact resistance of each switching path is minimized.

Abstract: A complementary metal-oxide semiconductor (CMOS) compatible radio frequency (RF) switch circuit and high voltage control circuit (HVCC) are disclosed. In a mobile device, an RF switch circuit couples a first RF circuit to a shared antenna through a low resistance path while electrically isolating other RF circuits from the antenna by a high resistance path. Each path in the RF switch circuit includes a series metal-oxide semiconductor (MOS) Field-Effect Transistor (FET) MOSFET switch which provides a low resistance path when fully turned on by a strong positive gate-to-source voltage and a corresponding body bias voltage, and a high resistance path when fully turned off by a strong negative gate-to-source voltage and corresponding body bias voltage. The RF switch circuit paths are controlled by a CMOS compatible HVCC which supplies high and low voltage signals to the gate node and body bias node of each MOSFET in each path.

Abstract: An RFID tag is provided as a wireless communication device that transmits and receives a communication signal. The RFID tag includes a base material, a conductor pattern including an antenna pattern provided at the base material, and a discharge auxiliary electrode. The discharge auxiliary electrode is disposed at a position where the discharge auxiliary electrode overlaps or is close to the antenna pattern in planar view, and lowers a dielectric breakdown voltage between two different opposed portions on the conductor pattern. With this configuration, ignition and combustion is prevented even in a situation in which the RFID tag is subjected to high-frequency power for heating a food item while attached to the food item.

Abstract: An active matrix substrate according to an aspect of the disclosure includes a pixel portion including a plurality of gate lines and a plurality of source lines, and a plurality of pixel electrodes, and a split switch circuit configured to split a signal from a source driver to supply to the plurality of source lines, wherein the pixel portion includes a first TFT including a first oxide semiconductor layer, the split switch circuit includes a second TFT including a second oxide semiconductor layer and a third oxide semiconductor layer, and the third oxide semiconductor layer covers at least a portion of an upper face and a portion of an edge face of the second oxide semiconductor layer.

Abstract: A novel approach for the control of AC power uses power MOSFETs in a bidirectional switch subcircuit configuration having an optically coupled, electrically floating control circuit that self-biases the switches into the “on” state and uses an optically coupled control element to force the switches into the “off” state. The time constant of the control circuit is fast enough to allow phase control as well as on-off control. A plurality of subcircuits can be easily cascaded to provide improved performance.

Abstract: A switching half-bridge has two field-effect transistors and a supplementary circuit arranged upstream of a gate terminal of a first field-effect transistor and formed of a first circuit branch having a damping resistor and an inductor connected in series with the damping resistor and a second circuit branch being connected in parallel with the first circuit branch and having a series resistor and an auxiliary switch connected in series with the series resistor. The half-bridge can be switched from a first switching state to a second switching state, wherein while the auxiliary switch is open, a change in the control voltage causes the first circuit branch to temporarily change the gate-source voltage of the first field-effect transistor from the switch-on level to a second switch-off level greater than a first switch-off level, with the gate-source voltage thereafter returning to the first switch-off level.

Abstract: a radio frequency (RF) switching circuit, including: a conducting module, configured to conduct an RF signal; a gate control voltage generating module, configured to provide a gate control voltage for the conducting module to control the conducting module operating at ON-state or OFF-state; wherein the gate control voltage generating module further includes: a first resistance adaptive module, providing a first impedance in a first state for a series branch where the conducting module and the gate control voltage generation module locate, and a second impedance in a second state for the series branch where the conducting module and the gate control voltage generation module locate, wherein the first impedance is greater than the second impedance. FOM is improved comprehensively, and Ron, Coff, and a power breakdown performance are optimized, which further improves circuit performance and reduces cost.

Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.

Abstract: A voltage switching device, an integrated circuit device, and a voltage switching method are provided. The voltage switching device includes a reference voltage generator generating a first reference voltage and a second reference voltage, a fuse system coupled to a circuit device, and a switch circuit coupled to the reference voltage generator, the fuse system, and the circuit device. The fuse system generates a first enable signal and a second enable signal according to an input signal from a circuit device. The switch circuit transmits the first reference voltage or the second reference voltage to the circuit device according to the first enable signal and the second enable signal from the fuse system.

Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.