Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.

Abstract: Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.

Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.

Abstract: Provided is a driving circuit for driving a switching element in accordance with an input signal. The driving circuit includes a driving unit connected to a control terminal of the switching element, where the driving unit is configured to switch, in accordance with the input signal, which one of a source current and a sink current is to be fed to the control terminal of the switching element, a first limiter configured to operate with a predetermined time constant and to limit a control voltage at the control terminal of the switching element to a first reference voltage when overcurrent is detected for a collector current of the switching element, and a second limiter configured to, when the overcurrent is detected, start lowering the control voltage earlier than an operation start timing of the first limiter that is determined by the time constant.

Abstract: A power supply device includes a voltage conversion circuit, a current controller and a current controlling circuit. The voltage conversion circuit generates a DC voltage from an AC power source and outputs the DC voltage to a pair of output terminals. The current controller is disposed on a first current path through which an output current flows and controls the current in the first current path. The current controlling circuit drives the current controller so as to reduce a ripple component generated in the output current, based on (i) a voltage at a first potential point set on a path from an output terminal at a high-potential side of the voltage conversion circuit to the current controller in the first current path and (ii) a current detecting voltage indicating the magnitude of the output current.

Abstract: A circuit for slew rate control for a high-side switch is disclosed. The circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The circuit further comprises a sampling capacitor, and the sampling capacitor is configured to sample an input voltage corresponding to the sample and level-shift circuit. Additionally, the circuit includes a charge-limiting circuit. The sampling capacitor is configured to charge a gate capacitance of the high-side switch. The charge-limiting circuit is configured to limit a rate of charge transferred to the gate capacitance of the high-side switch per unit of time.

Abstract: An electronic device is described. The electronic device includes line voltage measuring circuitry configured to measure a line voltage to produce a line voltage measurement. The electronic device also includes load voltage measuring circuitry configured to measure a load voltage to produce a load voltage measurement. The electronic device further includes a processor coupled to the line voltage measuring circuitry and the load voltage measuring circuitry. The processor is configured to adjust a voltage ramp waveform for a transition of a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET based on the line voltage measurement and the load voltage measurement to minimize heat generation and electromagnetic interference creation by the MOSFETs. The first MOSFET and the second MOSFET control a current to a load in an alternating current configuration.

Abstract: A drive circuit turns on an NPN transistor and a transistor in response to a turn-on command in a control signal to supply a positive current to a gate of a power transistor, and turns off the transistor after lapse of a certain time period to lower gate driving capability. The drive circuit turns on a PNP transistor and a transistor in response to a turn-off command in the control signal to supply a negative current to the gate of the power transistor, and turns off the transistor after lapse of a certain time period to lower gate driving capability.

Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

Abstract: A laser detection device can be used to protect an integrated circuit. The device includes a detection cell having a buried channel of a first conductivity type extending in a substrate of the integrated circuit. The substrate is of a second conductivity type. The detection cell also has a first electrical connection coupling a first point in the buried channel to a supply voltage rail, and a second electrical connection coupled to a second point in the buried channel. A detection circuit is coupled to the second point in the buried channel via the second electrical connection and adapted to detect a fall in the voltage at the second point.

Abstract: A self-matching phase shifter/attenuator including several incremental impedance matched phase shifter/attenuator elements is disclosed. Each incremental impedance matched phase shifter element comprises a reactive component (such as either a capacitor or inductor) that can be coupled in shunt to the signal path. The shunt reactive component is coupled in series with a ground switch. When closed, the ground switch connects the shunt reactive component to ground. When the ground switch is open, the switch removes the shunt reactive component from the circuit. In addition, each incremental impedance matched phase shifter element comprises a series reactive component having a reactance that is typically equal and inverse of that of the shunt reactive component.

Abstract: In a semiconductor device in the related art, it has been necessary to match the threshold voltage of a power element with the circuit operation of a gate driver; accordingly, it has been difficult to realize the operation of the gate driver most appropriate for the employed power element. According to one embodiment, when a power element is turned off, the semiconductor device monitors the collector voltage of the power element, and increases the number of NMOS transistors that draw out charges from the gate of the power element in a period until the collector voltage becomes lower than the pre-set determination threshold, rather than in the period after the collector voltage becomes lower than the determination threshold.

Abstract: A voltage generator including an oscillator having an output, a charge pump having an input and an output, the input of the charge pump being coupled to the output of the oscillator, a smoothing capacitor, a resistor having an input end and an output end, wherein the input end is coupled to the charge pump and the output end is coupled to the smoothing capacitor, and a shorting element connected in parallel with the resistor and which, when turned on, causes the resistor to be at least partially bypassed, wherein the voltage generator is configured to supply voltage to a radio frequency (RF) switch via the smoothing capacitor, and a frequency of the oscillator is controlled to be faster during a switching period of the RF switch.

Abstract: The present disclosure provides a scan driving circuit for driving an Nth-stage scanning line including: a pull-up control module for receiving a cascade signal of an upper stage and generating a scan level signal of the Nth-stage scanning line based on the cascade signal of the upper stage; a pull-up module for pulling down the scanning signal of the Nth-stage scanning line when the first clock signal is low according to the scan level signal and the first clock signal; the pull-up control module includes a first control unit and a second control unit, the control terminal of the second control unit inputs a second clock signal for controlling the scan level signal to become smaller when the second clock signal is at a high level. The present disclosure can prevent the waveform of the gate from appearing spikes, and thus the waveform of the gate is output normally.

Abstract: A method and apparatus for controlling a power switch are disclosed. A power switch may be coupled between a power supply signal and a virtual power supply signal coupled to a circuit block. The power switch may be configured to couple the power supply signal to the virtual power supply signal based on a first control signal, and reduce a voltage level of the virtual power supply signal to a voltage level less than a voltage level of the power supply signal based on a second control signal. The power switch may be further configured to change a current flowing from the power supply signal to the virtual power supply signal based on a third control signal.

Abstract: An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.

Abstract: A ground assembly includes a first layer, a second layer, and a bypass capacitor. The first layer includes a power ground, a communication ground spaced from the power ground, a conductive path defining a parasitic inductance and electrically coupled between the power ground and the communication ground, and an electrically insulating layer. At least a portion of the insulating layer is positioned between the power and communication grounds. The second layer includes a first substrate that is spaced from the power ground to define a first parasitic capacitance therebetween and is spaced from the communication ground to define a second parasitic capacitance therebetween. The bypass capacitor is electrically coupled between the power ground and the first substrate.

Abstract: A circuit for biasing a MEMS microphone includes a first group of serially-coupled transistors coupled between a first node and a second node, a second group of serially-coupled transistors coupled between the first node and the second node, and a voltage divider circuit coupled to the second node having a number of outputs, a first group of outputs being coupled to corresponding control nodes associated with the first group of serially-coupled transistors, and a second group of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second group of serially-coupled transistors, the control nodes being either bulk nodes or gate nodes.

Abstract: A device includes a semiconductor body having an active region and a substrate region that is beneath the active region. A bidirectional switch is formed in the semiconductor body having first and second gate structures that are configured to block voltage across two polarities as between first and second input-output terminals that are in ohmic contact with the electrically conductive channel. First and second switching devices are configured to electrically connect the substrate region to the first and second input-output terminals, respectively. A passive electrical network includes a first capacitance connected between a control terminal of the first switching device and the second input-output terminal and a second capacitance connected between a control terminal of the second switching device and the first input-output terminal. The passive electrical network is configured temporarily electrically connect the substrate region to the first and second input-output terminal at different voltage conditions.

Abstract: A method for controlling a state of a battery includes: providing and using a specific connecting interface to connect the battery and a portable device; and controlling the battery to enter a shipping mode and exit the shipping mode by using the specific connecting interface.

Abstract: A package module includes a power module, a first thermal dissipating component and a packaging plastic. The power module includes a substrate and at least one power semiconductor component disposed on the substrate. The first thermal dissipating component is disposed over the power module. The packaging plastic covers the power module and the first thermal dissipating component, wherein a portion of the first thermal dissipating component is exposed from the packaging plastic.

Abstract: A power converter provides a pyramidal structure of switches communicating between a capacitive divider at the base of the pyramid and a terminal at the top of the pyramid to provide a transformation of a relationship between current and voltage in power transferred between the capacitive divider and the terminal at the top of the pyramid while providing reduced electrical interference and electrical rate of change (dv/dt).

Abstract: Systems and methods for efficiently allowing current to bypass a group of solar cells having one or more malfunctioning or shaded solar cells without overwhelming a bypass diode. This can be done using a switch (e.g., a MOSFET) connected in parallel with the bypass diode. By turning the switch on and off, a majority of the bypass current can be routed through the switch, which is configured to handle larger currents than the bypass diode is designed for, leaving only a minority of the current to pass through the bypass diode.

Abstract: A driving apparatus configured to drive a plurality of switching elements including a first switching element and a second switching element, and each of the plurality of switching elements has a gate electrode. The driving apparatus includes: a driving circuit configured to supply a voltage to the gate electrode; and a controller configured to control the plurality of switching elements to turn on or off. The controller includes a control mode having a multi-driving mode configured to drive both of the first switching element and the second switching element, and a single driving mode configured to drive only the first switching element. The controller at the single driving mode sets a gate voltage to be applied to a gate electrode of the first switching element at a clamping voltage, which is smaller than the gate voltage of the first switching element at the multi-driving mode.

Abstract: The present invention provides an integrated circuit with a multiplexed pin and a pin multiplexing method. The multiplexed pin of the integrated circuit extends out with two connecting ends to receive two logic level signals which are finally restored in a chip. A first signal input end receives a signal representing whether to enable or disable, a second signal input end receives a function signal which achieves a certain function, and a diode, a resistor, and a first current source are used together to achieve multiplexing of the pin based on turn-on and clamping characteristics of the diode. The number of pins to be packaged and the area occupied by a chip on board are reduced, which is conducive to a small package design of the chip.

Abstract: A method for reading out a sensor unit having a first set of nodes and a second set of nodes and a symmetry which allows different configurations of excitation and sensing lead to a same readout. The method includes changing the readout configuration of the sensor unit by exchanging excitation and sensing between the first set of nodes and the second set of nodes, evaluating the similarity or deviation between measurement signals obtained in different readout configurations of the sensor unit, raising an error if the measurement signals differ more from one another than a predetermined value.

Abstract: In one embodiment, a shunt resistor is provided, comprising two terminals, a semiconductor substrate embodying at least one temperature sensor comprising at least a temperature sensitive element comprising at least one pn-junction, and at least two metal layers above the semiconductor substrate, at least the upper of the metal layer comprising a path that electrically connects the two terminals, whereby the temperature sensor is below and within the periphery of the upper metal layer.

Abstract: A DC-DC converter with low power consumption and high power conversion efficiency is provided. The DC-DC converter includes a first transistor and a control circuit. The control circuit includes an operational amplifier generating a signal that controls switching of the first transistor, a bias circuit generating a bias potential supplied to the operational amplifier, and a holding circuit holding the bias potential. The holding circuit includes a second transistor and a capacitor to which the bias potential is supplied. The first transistor and the second transistor include a first oxide semiconductor film and a second oxide semiconductor film, respectively. The first oxide semiconductor film and the second oxide semiconductor film each contain In, M (M is Ga, Y, Zr, La, Ce, or Nd), and Zn. The atomic ratio of In to M in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.

Abstract: According to one embodiment, a semiconductor device includes a first transistor of a first conductivity type, and a first logical circuit. The first transistor of the first conductivity type is connected between a first node to which a power supply voltage is applied and a second node. The first transistor is turned on in the initial stage of an active cycle, and is turned off by applying the power supply voltage to the second node. The first logical circuit is driven by the power supply voltage applied to the second node. The first logical circuit outputs a voltage which is lower than the power supply voltage in the active cycle based on an input signal supplied thereto.

Abstract: Embodiments disclosed herein relate to a bias circuit that uses Schottky diodes. Typically, a bias circuit will include a number of transistors used to generate a bias voltage or a bias current for a power amplifier. Many wireless devices include power amplifiers to facilitate processing signals for transmission and/or received signals. By substituting the bias circuit design with a design that utilizes Schottky diodes, the required battery voltage of the bias circuit may be reduced enabling the use of lower voltage power supplies.

Abstract: The invention relates to a semiconductor switch and to a method for determining a current in the power path of a semiconductor switch. For this purpose, a semiconductor switch, according to the invention, has a plurality of sense connections, wherein each of said sense connections provides an individual output signal that is proportional to the current in the power path of the semiconductor switch. The evaluation of the current in the power path can be optimized by the appropriate selection of one of the plurality of sense connections in accordance with the current in the power path of the semiconductor switch.

Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.

Abstract: A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.

Abstract: A midspan power over Ethernet (“PoE”) injector (20) connects via LAN cables (514) to remote PDs (518). Each cable (514) has a remote end; and a midspan end (516). The cables (514) includes receiving and transmitting conductors, and insulated electrical conductors. The injector (20) includes pairs of sockets (24) a first socket (24) of each pair is a powered socket, and a second socket (24) is unpowered and carries only data. A data-signal bus (188) interconnects the unpowered and powered sockets. Power switches (156), equal in number to the socket pairs, connect respectively to one of the powered sockets (24). Without negotiating with a PD (518) connected by the cable (514) to the powered socket (24), a controller (34) causes switches (156) to close thereby transmitting electrical power via the powered socket (24) connected thereto and the cable (514) mated therewith to the PD (518). The controller (34) also concurrently monitors operational status: a. of each connected PD (518); and b.

Abstract: An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

Abstract: A direct-current (DC) motor control device includes first and second switches, a conducting element and a power storage element. The power storage element, the conducting element and the second switch are connected to each other and form a loop, and the first switch is connected to a common node between the power storage element and the conducting element. When the DC electric power source is normally connected to the DC motor control device, the first switch is turned on, and the conducting element establishes a unidirectional conduction from a DC motor to the power storage element while the second switch is turned off.

Abstract: The invention comprises: a smart junction box with a safe mode for photovoltaic solar power modules; and the related method of operation. Power MOSFETs are used as active bypass diodes during the normal operation of the smart junction box, but in safe mode the power MOSFETs are turned on continuously, thereby reducing the output voltage to a safe level of approximately 200 mV. A Non Volatile Memory (NVM) keeps the module in the safe mode after power from the PV cells is interrupted by momentary shading or night. The smart junction box includes transmitter and receiver circuits for wirelessly communicating with other smart junction boxes. The smart junction box enters safe mode in response to receiving a shut-down signal, and exits safe mode in response to receiving a restart signal. The smart junction box acts as a signal repeater, thereby ensuring that the shut-down and restart signals propagate to all junction boxes in the solar array.

Abstract: A resonant load power conversion apparatus is provided to lower a switching frequency of each switching device and to reduce the number of main circuit conductors. The conversion apparatus includes a single-phase inverter having a dc input side (Vdc) connected with a dc voltage source and an output side (Vout) connected with a resonant load and outputting a rectangular wave voltage with a resonance frequency. Upper and lower arms on the input side and output side of the single-phase inverter are connected, respective, with switch group circuits 100U, 100V, 100V and 100V each of which includes N series combinations (N is an integer equal to or greater than 2) of two switching devices, connected in parallel with each other by main circuit conductors. The switching devices of the switch group circuits are controlled in a time division switching control mode with a control section.

Abstract: A three-dimensional (3D) image sensor module including: an oscillator configured to output a distortion-compensated oscillation frequency as a driving voltage of a sine wave biased with a bias voltage; an optical shutter configured to vary transmittance of reflective light reflected from a subject, according to the driving voltage, and to modulate the reflective light into at least two optical modulation signals having different phases; and an image generator configured to generate image data about the subject, the image data including depth information that is calculated based on a difference between the phases of the at least two optical modulation signals.

Abstract: A power converter circuit includes a switching circuit with at least one electronic switch, a capacitor configured to provide or receive a voltage with a predefined voltage level, at least one first inductor, and a snubber circuit. The snubber circuit includes at least one second inductor inductively coupled to the at least one first inductor and electrically coupled to the capacitor.

Abstract: A semiconductor device includes: a channel layer made of a compound semiconductor; a barrier layer provided above the channel layer and made of a compound semiconductor in which an energy band on a carrier travel side in a junction with respect to the channel layer is farther from an intrinsic Fermi level in the channel layer than in the channel layer; a low-resistance region provided in a surface layer of the barrier layer, in which resistance is kept lower than portions around by containing impurity; a source electrode and a drain electrode connected to the barrier layer at positions sandwiching the low-resistance region; agate insulating layer provided on the low-resistance region; and a gate electrode provided above the low-resistance region through the gate insulating layer.

Abstract: A gate control circuit includes a first pulse generator that outputs a first pulse signal when an input signal changes from a first logical level to a second logical level, a first gate controlling portion that controls a gate voltage of a first transistor based on a first control signal when the input signal is at the second logical level, a second pulse generator that outputs a second pulse signal when the input signal changes from the second logical level to the first logical level, and a second gate controlling portion that controls the gate voltage of the first transistor based on a second control signal when the input signal is at the first logical level. The first gate controlling portion includes a first overcurrent controlling portion that controls a voltage level of the first control signal after an expiration of an output period of the first pulse signal.

Abstract: A power switch circuit includes an oscillation circuit that generates a clock signal based on a supplied first voltage. A boosting circuit receiving the clock signal and boosting the first voltage based on the clock signal to output a boosted first voltage as a second voltage is provided. A detection circuit that detects a difference in voltage levels between an input voltage and the first voltage and outputs a voltage selection signal based on the detected difference is provided. A voltage selection circuit that selects one of the first voltage and the second voltage based on the voltage selection signal and outputs the selected voltage is provided. A switching element switching according to a control voltage based on an enable signal and the selected voltage is also provided.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: In accordance with an embodiment, a radio frequency (RF) switching circuit includes a plurality of series connected RF switch cells comprising a load path and a control node, a plurality of first gate resistors coupled between control nodes of adjacent RF switch cells, and an input resistor having a first end coupled to a control node of one of the plurality of RF switch cells and a second end configured to an output of a switch driver. Each of the plurality of series connected RF switch cells includes a switch transistor.

Abstract: In a cascode switching device, avalanche breakdown of a control transistor and loss of soft switching or zero voltage switching in a high voltage normally-on depletion mode transistor having a negative switching threshold voltage and the corresponding losses are avoided by providing additional capacitance in parallel with a parallel connection of drain-source parasitic capacitance of the control transistor and gate-source parasitic capacitance of the high voltage, normally-on transistor to form a capacitive voltage divider with the drain-source parasitic capacitance of the high voltage, normally-on transistor such that the avalanche breakdown voltage of the control transistor cannot be reached. The increased capacitance also assures that the drain source parasitic capacitance of the high voltage, normally-on transistor is fully discharged before internal turn-on can occur.

Abstract: Driving a back-gate of a transistor with a follower signal that corresponds to an information signal. At least some of the illustrative embodiments are methods including: passing an information signal from a drain terminal to a source terminal of a main field effect transistor (FET), the information signal has a peak-to-peak voltage; generating a follower signal that corresponds to the information signal, the follower signal electrically isolated from the information signal, and the follower signal has a peak-to-peak voltage lower than the peak-to-peak voltage of the information signal; and applying the follower signal to a back-gate of the main FET.

Abstract: A solid state power controller (SSPC) includes a main feed line, a load line, and a P-channel field effect transistor (PCFET) connecting between the main feed line and the load line and including an off state and an on state. The on state electrically connects the main feed line and the load line and the off state electrically disconnects the main feed line and the load line. The SSPC also includes a channel control operatively connected to the PCFET to control the PCFET between the off state and the on state.

Abstract: To reduce the amplitude voltage of control signals of a MEMS device. A semiconductor device includes a MEMS device, a first transistor, a second transistor whose source or drain is electrically connected to a source or a drain of the first transistor, a third transistor which sets the potential of a gate of the first transistor to a value at which the first transistor is turned on, a fourth transistor which sets the potential of the gate of the first transistor to a value at which the first transistor is turned off, and a fifth transistor which supplies a signal to a gate of the second transistor and a gate of the fourth transistor.