Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to de-activate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.

Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Abstract: A switch is provided. The circuit includes a plurality of transistors configured to electrically isolate the input of the switch from the output of the switch. In one embodiment, for example, the plurality of transistors may be configured to provide at least one path between the input and the output of the switch, and to provide at least three layers of electrical isolation between the input and the output of the switch when the switch is open.

Abstract: Disclosed herein is a resistor-sharing switching circuit including: a first switching device and a second switching device; and a resistor whose first end is connected to a control signal input end to which a control signal for controlling bodies of the first switching device and the second switching device is applied and whose second end is connected to the bodies of the first switching device and the second switching device.

Abstract: A circuit for controlling a connector to transmit data according to Low Pin Count (LPC) protocol or Joint Test Action Group (JTAG) protocol includes a switch unit, first and second electronic switches, and first and second switch chips. When the switch unit outputs a high level signal to the first electronic switch, the connector transmits data according to LPC protocol. When the switch unit outputs a low level signal to the first electronic switch, the connector transmits data according to JTAG protocol.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: A gate driver turns on/off a switching element Q1 by applying a control signal from a controller to a gate of the switching element. The switching element has the gate, a drain, and a source and contains a wide-bandgap semiconductor. The gate driver includes a parallel circuit that includes a first capacitor C1 and a first resistor R1 and is connected between the controller and the gate of the switching element and a short-circuit unit S4 that is connected between the gate and source of the switching element and short-circuits the gate and source of the switching element after a delay from an OFF pulse of the control signal.

Abstract: Under-voltage, over-voltage, and temperature detectors disposed in a switching circuit are turned on periodically and in response to an oscillating signal having a low duty cycle. Accordingly, because the voltage and temperature detectors remain off for long durations, their operating currents, and thus the operating current of the switching circuit is substantially reduced. The switching circuit has a current limiting function which is disabled when the switch current is below a threshold value, thereby further decreasing the current consumption of the switching circuit at low switch current levels.

Abstract: Apparatus and methods for a switch circuit to provide a substantially constant gate-to source voltage to a passgate are provided. In an example, a switch circuit includes a summing circuit having an output configured to couple to the gate of a passgate, the summing circuit can be configured to maintain a substantially constant voltage between the gate and the source of the pass gate.

Abstract: Apparatus and methods are disclosed related to using one or more field effect transistors as a resistor. One such apparatus can include a field effect transistor (FET), averaging resistors and a bidirectional current source. The averaging resistors can apply an average of a voltage at the source of the FET and a voltage at the drain of the FET to the gate of the field effect transistor. The bidirectional current source can turn the FET on and off. The FET can operate in the ohmic region when on. Such an apparatus can improve the linearity of the FET as a resistor, for example, at lower frequencies near or at direct current (DC). In some implementations, the apparatus can include one or more current sources to remove an offset introduced by the bidirectional current source at the source and/or the drain of the FET.

Abstract: Embodiments of a circuit, which includes a device and a switch, which is electrically coupled to the device, to control power applied to the device, are described. This switch includes a control terminal, which controls the switch, and two other terminals, which can receive power to be applied to the device. Moreover, the circuit is configured to apply a voltage to the control terminal to ensure the switch remains open when a supply voltage is applied to one of the two other terminals while powering-up the circuit, thereby preventing spurious application of the supply voltage to the device.

Abstract: Described herein is a low-voltage multi-stage interleaver. The interleaver includes at least a first interleaver stage and a second interleaver stage. The first interleaver stage is either blocked or operating in a saturation region. The first interleaver stage facilitates cancellation of DC current, including a biasing current, so that the second interleaver stage receives no DC current input. The second interleaver stage is either blocked or operating in a linear region to allow the second interleaver stage to act as a passive current switch.

Abstract: A high voltage transmission switch comprises a switching block coupled between a connection terminal to a load and a low voltage output terminal and comprising at least a first switching transistor and a second switching transistor coupled between the connection terminal and the low voltage output terminal and interconnected at a first circuit node; and a driving circuit coupled between a positive low voltage supply reference and a negative high voltage supply reference and having an output terminal connected to the switching block. The driving circuit including at least a first driving transistor coupled between the positive low voltage supply reference and the output terminal and a second driving transistor coupled between the output terminal and the negative high voltage supply reference.

Abstract: A semiconductor device includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.

Abstract: A power switch circuit includes a pulse width modulation (PWM) control circuit having a first frequency control terminal and a second frequency control terminal for outputting predetermined frequency signals, a first switch circuit, a second switch circuit, a first resistor connected between the first frequency control terminal and the first switch circuit, a second resistor connected between the first frequency control terminal and the second switch circuit, a first filtering circuit having a third resistor and a first capacitor, and a second filtering circuit having a fourth resistor and a second capacitor. A first terminal of the first capacitor is connected to the first switch circuit and a second terminal of the first capacitor is grounded via the third resistor. A first terminal of the second capacitor is connected to the second switch circuit and a second terminal of the second capacitor is grounded via the fourth resistor.

Abstract: A switching circuit according to one embodiment includes: a switching element that has a first terminal and a second terminal, and is driven by a pulse signal to switch a conduction state between the first and second terminals; a power source section that supplies a voltage to the first terminal; a load circuit that is connected in parallel with the power source section; a passive circuit section that is connected between a connection point between the power source section and the load circuit, and the first terminal, and suppresses a current flowing from the connection point to the switching element at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse signal; and a resonant circuit section that is connected between the passive circuit section and the connection point, and resonates at the frequency of N times.

Abstract: The present disclosure relates to a high voltage switch which may comprise a chain of MOS field-effect transistors (MOSFETs). The current of the individual MOSFETS, and hence the chain, can be controlled by means of adding a current measuring resistance into the source path of the transistors and transmitting the voltage arising there via a capacitor to a gate connector of the transistors.

Abstract: A switching circuit includes a switching device including the first and second main electrodes and a control electrode; and a driver including: a first rectifying device having an anode terminal connected to the first main electrode of the switching device; a first driving device having a first main electrode connected to a cathode terminal of the first rectifying device and a second main electrode connected to the control electrode of the switching device; a second driving device having a first main electrode connected to the control electrode of the switching device and a second main electrode connected to the second main electrode of the switching device; and input terminals receiving control signals inputted to a control electrode of the first driving device and a control electrode of the second driving device.

Abstract: A semiconductor device 101 in a bi-directional switch includes: a first electrode 109A, a second electrode 109B, a first gate electrode 112A, and a second gate electrode 112B. In a transition period: when the potential of the first electrode 109A is higher than the potential of the second electrode 109B, a voltage lower than the first threshold voltage is applied to the first gate electrode 112A and a voltage higher than the second threshold value voltage is applied to the second gate electrode 112B; and otherwise, a voltage higher than the first threshold value voltage is applied to the first gate electrode, and a voltage lower than the second threshold value voltage is applied to the second gate electrode.

Abstract: Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.

Abstract: Methods and apparatus for receiving high voltage signals using a receiver designed in a low supply voltage technology are disclosed. One embodiment of an integrated circuit includes a single ended driver including an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor. An input pass gate is coupled to the single ended driver, and is configured as a PMOS pass gate coupled in parallel with the NMOS transistor in the single ended driver. In a low voltage mode, the NMOS transistor and the PMOS pass gate form a first pass gate for transmitting the input signal to the receiver. In a high voltage mode, the PMOS pass gate is disabled, and the NMOS transistor and PMOS transistor form a second pass gate for transmitting the input signal to the receiver.

Abstract: A gate drive circuit capable of turning on a semiconductor switching element at high speed, which includes: a buffer circuit including a turn-on-drive switching element and a turn-off-drive switching element that are complementarily turned on and off, for driving the semiconductor switching element; a first DC voltage supply including a positive electrode connected to the source or emitter of the turn-on-drive switching element and a negative electrode connected to a reference potential; and a second DC voltage supply including a positive electrode connected to the source or emitter of the turn-off-drive switching element and a negative electrode connected to the reference potential.

Abstract: In a first aspect, an RF switch includes a main transistor and a gate-to-source shorting circuit. When the RF switch is turned off, the gate-to-source shorting circuit is turned on to short the source and gate of the main transistor together, thereby preventing a Vgs from developing that would cause the main transistor to leak. When the RF switch is turned on, the gate-to-source shorting circuit is turned off to decouple the source from the gate. The gate is supplied with a digital logic high voltage to turn on the main transistor. In a second aspect, an RF switch includes a main transistor that has a bulk terminal. When the RF switch is turned off, the bulk is connected to ground through a high resistance. When the RF switch is turned on, the source and bulk are shorted together thereby reducing the threshold voltage of the main transistor.

Abstract: A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal of the switching device with reference to an emitter control terminal or a source control terminal of the switching device, and a unit for detecting a temperature of the switching device. The temperature of the power semiconductor switching device is detected, and a gate drive voltage or a gate drive resistance value is changed based on the detected temperature.

Abstract: This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.

Abstract: A circuit includes a high-side switch, a low-side switch, a diode, a transformer having a primary winding and a secondary windowing, and an input connected to a first terminal of the primary winding. The high-side switch has a source, a gate connected to a drive source and a drain connected to a second terminal of the primary winding. The low-side switch has a source connected to ground, a gate connected to a drive source and a drain connected to the source of the high-side switch. The diode is connected between the gate of the high-side switch and the first terminal of the primary winding. The diode forms a current loop with the primary winding and the high-side switch to circulate current when low side switch is off until the high side switch turns off.

Abstract: A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current.

Abstract: A double pole double throw switch device is provided. The device includes a first path circuit, a second path circuit, a third path circuit and a fourth path circuit. The first terminals of the first and second path circuits are coupled to a first port, and the second terminals of the first and second path circuits are respectively coupled to a third port and a fourth port. The first terminals of the third and fourth path circuits are coupled to a fourth port, and the second terminals of the third and fourth path circuits are respectively coupled to the second port and the third port. Each path circuit includes a switch module and a functional switch circuit. When a switch module is turned on, its corresponding functional switch circuit is turned off, and when the switch module is turned off, its corresponding functional switch circuit is turned on.

Abstract: An electronic control apparatus includes a switching element having a control terminal; an ON-drive constant-current circuit for supplying a constant current to the control terminal, thereby charging the control terminal of the switching element with electrical charge; an OFF-drive switching element for discharging electrical charge from the control terminal of the switching element by being turned ON; and a control circuit adapted to control the ON-drive constant-current circuit and the OFF-drive switching element in response to a drive signal being inputted, thereby controlling the voltage of the control terminal of the switching element to drive the switching element. The ON-drive constant-current circuit includes a current control transistor and a current detection element.

Abstract: Embodiments of radio frequency switching systems, modules, and methods with improved high frequency performance are described generally herein where the switching module may include a first switch module coupled in series to a second switch module, and a third switch module coupled between the first and the second module and ground. A controllable element of the second module may have a lower off capacitance than a controllable element of the first module. Other embodiments may be described and claimed.

Abstract: A method for operating a load switch, wherein a charge pump drives a gate of the load switch, comprises the steps of: controlling a charge pump frequency as a function of states of the load switch; generating a charge pump output as a function of the charge pump frequency; and providing the charge pump output to the gate of the load switch.

Abstract: The present invention relates to circuits and methods for limiting the operating area of a transistor in a constant current source. The circuits and methods use a detector and a driver to limit the operating area of a transistor. The detector and driver have parameters selected so that, when the voltage at the drain of the transistor satisfies a reference condition, the driver causes drain current of the transistor to decrease. The reference condition is determined relative to the maximum safe drain-to-source voltage at the design drain current of the constant current source.

Abstract: An identifying circuit is connected between a Universal Serial Bus (USB) interface and a controller. The identifying circuit includes first to fourth electronic switches. When a power adapter connects to the USB interface, the first and fourth electronic switches are not turned on, and the second and third electronic switches are turned on. An identification pin of the controller receives a low level signal and determines that the power adapter connects to the USB interface. When a computer connects to the USB interface, the first and fourth electronic switches are turned on, and the second and third electronic switches are not turned on. The identification pin receives a high level signal and determines that the computer is connected to the USB interface.

Abstract: A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.

Abstract: A switching circuit suitable for a low power oscillator circuit includes control and output circuits, the control circuit arranged to control the output circuit, the control circuit having input and output terminals, the output circuit having input and output terminals and control terminals; wherein the input terminal of the control circuit is connected to the input terminal of the output circuit, and the control terminal of the output circuit is connected to the output terminal of the control circuit, the output circuit first switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time, and the control circuit has second switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time.

Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.

Abstract: A server rack includes a main body, an electronic scale, and an alarm. The main body is used for receiving a number of servers. The electronic scale includes a pressure sensor and a microcontroller. The main body presses on the pressure sensor so that the pressure sensor can measure the pressure from the main body to obtain a pressure signal. The microcontroller analyzes the pressure signal to calculating the total weight of the main body and the servers. The alarm stores a predetermined weight threshold, which is the total weight of the main body and the maximum servers that the main body can bear. The alarm also compares the measured total weight with the predetermined weight threshold. When the measured total weight is larger than the predetermined weight threshold, the alarm alarms.

Abstract: A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.

Abstract: A circuit includes an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well. The input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor.

Abstract: A high-frequency switch module includes a switch IC. An impedance matching circuit is connected to the antenna port of the switch IC. The impedance matching circuit includes a high-pass filter and a low-pass filter. The high-pass filter is disposed on the side of the antenna port, and is a substantially L-shaped circuit including a capacitor and an inductor. The antenna port is connected to the ground by the inductor.

Abstract: A motor load control apparatus capable of suppressing heat generation of an electronic switch and suppressing occurrence of noise associated with rotation of a fan and vibration of the fan is provided. A switch section (17) in which a first electronic switch (T1) and a second electronic switch (T2) are connected in parallel is provided, and the first electronic switch (T1) is driven by a PWM signal with a predetermined duty ratio and a predetermined frequency and the second electronic switch (T2) is driven in a state of delaying the PWM signal by which the first electronic switch (T1) is driven by a predetermined time. Consequently, as compared with the case of one electronic switch, a heating value of each of the electronic switches can be reduced and radiation measures of the whole apparatus can be reduced. Further, noise or vibration occurring by PWM control can be reduced by changing delay time at random.

Abstract: A switching device includes a first switch disposed between a power source voltage and an intermediate node, the first switch forming a current path on the basis of an input signal, a second switch disposed between the intermediate node and a ground, the second switch forming a current path on the basis of a voltage of the intermediate node, and a transmission gate receiving the input signal, the transmission gate outputting the input signal on the basis of the voltage of the intermediate node.

Abstract: An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type.

Abstract: The described FET switch topology greatly reduces the off state loading experienced by the gate biasing resistors in a stacked FET structure. The FET switch topology evenly distributes the voltage across the FET switch topology which reduces the voltage across the gate biasing resistors when the stacked FET structure is in an off state. Because the off state loading is reduced, there is a corresponding reduction of the current through bias resistors, which permits a reduction in the size of the bias resistors. This permits a substantial reduction in the area attributed to the bias resistors in an integrated solution.

Abstract: In accordance with embodiments of the present disclosure, a circuit may include a transmission switch and a dummy switch coupled at its output to the output of the transmission switch. The transmission switch may be configured to be selectively enabled and disabled based on a control signal received at a gate of the transmission switch. The transmission switch may be further configured to receive a first polarity of a differential signal at its input and pass the first polarity of the differential signal to its output when enabled. The dummy switch may be configured to be disabled and to receive a second polarity of the differential signal at its input, the second polarity of opposite polarity of the first polarity.

Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.

Abstract: A high-frequency switch circuit according to the present invention includes at least a first switch connected between a common terminal and a first terminal, and a second switch connected between the common terminal and a second terminal. Each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate. A compensation capacitance that compensates a parasitic capacitance generated when the first switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the first switch. A compensation capacitance that compensates a parasitic capacitance generated when the second switch is in an off-state is formed between the drain and the body or between the source and the body in the FET of the second switch.

Abstract: A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations.

Abstract: Circuits, methods, and apparatus that provide isolation between receive and transmit circuits in a wireless transceiver. One example provides switches that can be included on an integrated circuit with at least portions of a wireless transceiver. These switches vary the impedance of transmitter and receiver circuits between a termination impedance and a high impedance by inserting or removing components in parallel with matching networks. Signal losses are minimized since these switches are shunt connected to input and output paths on the wireless circuit and are not connected directly in either signal path.