Abstract: A solid-state switching element that works with at least one semiconductor region or a pair of antiserially arranged semiconductor regions having characteristic curves similar to those of FETs. An internal body diode in inverse operation is also provided. In addition to having a drain and a gate, each of the semiconductor regions has two source electrodes, with several cells combined with the electrodes in cell design. One source serves as a load current electrode, called a load source, and the other source is available as a gate electrode, called a control source. The effective semiconductor region of the load source is larger than the effective semiconductor region of the control source.

Abstract: A current source and a semiconductor integrated circuit device for suppressing fluctuations occured in an output current of current sources composed MOS transistors for switching. A back gate voltage of MOS transistors M1, M3 for switching connected in series to a constant current generator 9 is supplied through a power source line 5d independent of a power source line 4d which supplies a driving voltage. The stabilization of the back gate voltage leads the operation of the MOS transistors M1, M3 to be stabilized, thereby suppressing the fluctuations occured in the output currents I.sub.out and I.sub.out current sources.

Abstract: In an FET switch for controllably allowing and inhibiting passage of an input signal in ON state and OFF state, respectively, FETs are connected in a multi-stage configuration. A control voltage adjusting circuit is connected between a gate and one of a drain and a source of each FET. The control voltage adjusting circuit adjusts a gate-source voltage so as to follow the variation of a drain-source voltage. The input voltage applied to the FET switch in OFF state is divided by the plurality of FETs. Since the variation of the gate-source voltage follows the variation of the drain-source voltage, the FET switch is hardly influenced by an amplitude of the input signal.

Abstract: A high-side gate driving circuit, where a current-mode differential error amplifier is used to regulate the current sourced to the gate. A current path is provided from the gate to the source of the power device, and a constant current is provided to the gate. A variable current source is also provided, and this current source is controlled by the output of the error amplifier. Preferably a voltage offset (avalanche breakdown diode) is interposed between the gate and source of the high-side driver; this ensures that the feedback loop will operate in a bistable mode, which avoids instability problems.

Abstract: An integrated semiconductor circuit comprising an output terminal connected to a ground terminal via a series connection of a first switching transistor and a second switching transistor of inverse polarization with respect to the latter, each of said switching transistors having parasitic transistors. Whether the second semiconductor switch means is conducting or not, is dependent on the current flow through a resistor connected between gate and source of the second semiconductor switch means. Whether current flows through this resistor, is dependent on the switching condition of a further switching transistor, which in turn is also determined by the output signal of a comparator circuit by means of which a potential corresponding to the potential present at output terminal is compared to a reference potential.

Abstract: A field effect transistor (FET) includes a first source/drain terminal, a body terminal, and a second source/drain terminal. A bi-directional N-channel FET circuit includes a biasing circuit which couples the body terminal of the bi-directional FET to one of its first and second source/drain terminals having a lesser voltage when the first and second source/drain voltages differ by more than a threshold voltage. When the voltages differ by a threshold voltage or less, the body terminal floats at a voltage no higher than a diode drop above the lesser of the two source/drain voltages, and at a voltage no lower than a threshold voltage below the higher of the two source/drain voltages. An analogous bi-directional P-channel FET circuit is also described. Body effect is reduced because the body terminal of the FET is maintained at a voltage at or near the voltage of the effective source terminal at all times, irrespective of which of the two source/drain terminals is the effective source terminal.

Abstract: In an amplifier for driving a large capacitive load, a boost circuit is included to improve the efficiency of the amplifier where an input to the amplifier has a small signal swing. The amplifier comprises a stack of series-connected charge-storage capacitors serving as secondary power sources. During a charging of the capacitive load, charge is obtained from voltage nodes between the stack capacitors. One or more low-voltage power supplies are connected to the capacitive load in the boost circuit. With these power supplies, during a discharge of the capacitive load, the latter appears to be charged to a higher voltage than it actually is so as to return some charge to the highest voltage node from where a portion of its charge was obtained. As a result, the power consumption in the amplifier is substantially reduced.

Abstract: A constant current source is connected to a first node that connects on the one hand to a predetermined potential via a first switching transistor with a control electrode thereof connected to a signal input terminal, a second node, and a resistive conduction member, and on the other hand to a current output terminal via a second switching transistor with a control electrode thereof connected to the second node to constitute a current switching circuit operable without an external reference bias and with a reduced number of components.

Abstract: A bidirectional current blocking switch is disclosed. The switch includes a four-terminal MOSFET in which there is no source-body short. The voltages applied to the source and drain terminals are both higher than the voltage applied to the body terminal (for an N-channel) device so that the source-body and drain-body junction of the MOSFET never become forward-biased. The switch of this invention is particularly useful for switching a cascaded set of batteries in a portable computer. Also included is a disclosure of circuitry to protect the switch against a reverse connected battery charger.

Abstract: A switching device has at least a first connection and a second connection, as well as a control connection. The switching device includes at least a first transistor and a second transistor. A load is connected to the second connection of the switching device, and a control unit is connected to the control connection of the switching device. A power supply is normally connected to the first connection, and the second connection is normally connected to ground via the load. The switching device further includes a polarity reversal protection system for protecting the switching device and the load from damage in case of a polarity reversal, which occurs when the power supply is connected to the second connection through the load, and the first connection is connected to ground. The second transistor is connected in series between the first connection of the switching device and the first transistor. The second transistor is operated inversely with respect to the first transistor.

Abstract: A semiconductor relay has two output MOSFET pairs, each of which is series-connected with the other. Each MOSFET pair is comprised of two MOSFETs series-connected oppositely to each other, and these MOSFETs are controlled to turn on or off simultaneously. The semiconductor relay further includes a switch, which is inserted between the ground and the junction of the two MOSFET pairs. When these MOSFETs are in an off condition, said switch is closed in order to release electric charges accumulated on said MOSFETs and to increase the off-resistance of this semiconductor relay. On the other hand, when the MOSFETs are in an on condition, said switch is opened so as to connect both MOSFET pairs in series. As a result, a semiconductor relay having a high off-resistance can be obtained without increasing the on-resistance.

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates, and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device. A low power current steering circuit which can perform dynamic current steering without affecting switching speed performance is also disclosed.

Abstract: A comparator circuit (31) for sensing a voltage difference between a battery voltage and a power supply voltage is coupled to a switch (39). The comparator circuit is capable of accurately sensing a voltage near the power supply voltage. The comparator circuit (31) comprises a first amplification stage (32-36), a second amplification stage (37), and a Schmitt trigger (38). The first amplification stage (32-36) includes a first source follower (32) and a second source follower (33) for generating a differential voltage corresponding to a difference voltage between the battery voltage and the power supply voltage. The first amplification stage (32-36) reduces problems in amplifying voltage near the power supply voltage by level shifting the voltage through the use of source followers and insuring transistors operate in a saturation region of operation. The second amplification stage (37) further amplifies the difference voltage between the battery voltage and the power supply voltage.

Abstract: A low-voltage driven semiconductor device is simple to fabricate, operates at high speed, and consumes low power. The semiconductor device is made of first and second MISFETs connected in series. The MISFETs have channels of the same conduction type. If the conduction type is n, the drain and gate of the first MISFET are connected to the high-potential side of a power source. The source and well of the second MISFET are connected to the low-potential side of the power source. The well of the first MISFET and the gate of the second MISFET are connected to a signal input terminal. A voltage applied to ends of the MISFETs and the potential fluctuation range of a signal supplied to the signal input terminal are each set to be lower than a voltage determined by a built-in potential (a forward withstand voltage) of a pn junction between a well of the first MISFET and a diffusion layer of the same. The diffusion layer is one that is adjacent to the second MISFET.

Abstract: The present invention relates to an output circuit and a semiconductor integrated circuit. It is an object of the present invention to cut off a passage of a current through a forward parasitic diode of a transistor connected to a power supply line and a ground line at a time of suspension of output operation of the relevant circuit, and to raise an output high level to the utmost and lower an output low level to the utmost at time of normal output operation.

Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Abstract: A signal integration circuit having a first MOSFET including a drain connected to a power source and a gate connected to a plural number of the first capacitances in parallel; and an input means connected to each capacitance; in which each input means comprises; the second MOSFET whose source is connected to the first capacitance through a resistance, which receives an input pulse signal, and whose gate is grounded through the second capacitance, and the third MOSFET whose source is connected to a gate of the second MOSFET, whose drain is connected to a power source, and whose gate receives a pulse signal for setting weight; a gate of the first MOSFET receiving a reference saw-tooth signal, a source of the first MOSFET grounded through the third capacitance, and an output pulse signal being output from this source of said first MOSFET.

Abstract: A driver circuit and method for alternately driving first and second power transistors is provided. The driver circuit includes shoot-through reduction circuitry for monitoring the gate-to-source voltages of the two power transistors so as to inhibit the turning-ON of each power transistor until the gate-to-source voltage of the other power transistor has fallen to a voltage level indicative of the other transistor being OFF. Additionally, the driver circuit includes a circuit to prevent transient signals from said power transistors from affecting the operation of the driver circuit.

Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Abstract: A push-pull output stage for driving a motor which provides an auxiliary power supply Vaux above supply voltage Vcc by using highside MOSFETs which do not have source-body shorts, and by connecting a capacitor to the poles of the motor through rectifying diodes which output flyback pulses to the capacitor. Damage to the highside MOSFETs is prevented by limiting the voltage on the capacitor using a zener diode. The push-pull output stage increases the driving potential applied to the motor be eliminating the need for an isolating Schottky diode between the output stage and a power source. Back emf continues to supply energy to Vaux even after Vcc is removed.

Abstract: A transistor (2P) permitted to select whether to operate as a common-source circuit or as a source follower type circuit is connected in series with a transistor (1P) operating as a common-source circuit. This selection is achieved by the control of a switching circuit (SP). Selection is permitted to be made whether to oscillate the amplitude of an output potential over the full range or to limit the amplitude by the amount of a threshold level of the transistor. An MOS transistor output circuit is provided which limits or unlimits the amplitude of the output potential for reducing undesired radiation, malfunctions due to noises and heat generated and for high-speed operation of logic circuits. (FIG.