Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: A display apparatus and a compensation circuit are provided. The display apparatus includes a display screen, a sound reproduction device and a power supply circuit. The power supply circuit includes a rectifier circuit and a compensation circuit. The rectifier circuit is used to convert an alternating current to a direct current. The compensation circuit is used to compensate for a parasitic signal of a synchronous rectification MOSFET in the rectifier circuit, thereby reducing heat generated by the MOSFET.

Abstract: The present invention discloses a power supply stabilizing circuit having noise suppressing mechanism configured to drive a voltage-control oscillating circuit that includes a current-adjusting N-type transistor including a drain, a source and a gate and an adjusting voltage generation circuit. The drain receives a first operation voltage. The source generates a power signal to the voltage control oscillator circuit. The gate receives an adjusting voltage. The adjusting voltage generation circuit operates according to a second operation voltage higher than the first operation voltage and receives a reference voltage that is a division of the first operation voltage to generate the adjusting voltage. The adjusting voltage is a sum of the reference voltage and a threshold voltage of the current-adjusting N-type transistor such that the current-adjusting N-type transistor operates in a saturation region to keep a current variation amount of the power signal smaller than a predetermined value.

Abstract: Disclosed is a light-emitting diode display module, including a first light-emitting diode, a second light-emitting diode, a third light-emitting diode, a scan block, a voltage conversion block, a first sink block, and a second sink block. An operating voltage of the first light-emitting diode is lower than that of the second and third light-emitting diodes. The voltage conversion block provides an auxiliary power supply voltage based on a high power supply voltage and a low power supply voltage. The first light-emitting diode is coupled between the scan block and the first sink block receiving the high power supply voltage and the auxiliary power supply voltage. The second light-emitting diode and the third light-emitting diode are coupled between the scan block and the second sink block receiving the high power supply voltage and the low power supply voltage.

Abstract: Embodiments of the present disclosure provide a temperature sensor that may be integrated into a memory device along with a 1T1C reference voltage generator to enable the 1T1C reference voltage generator to provide a temperature dependent 1T1C reference voltage to a memory core (e.g., F-RAM memory core) of the memory device. The temperature sensor may detect a temperature of the memory core, and output this information (e.g., as a trim) for use by the 1T1C reference voltage generator in providing a temperature dependent 1T1C reference voltage. In this way, both the P-term and U-term margins of the memory core may be maintained even as a temperature of the memory core increases.

Abstract: There is provided a voltage supply circuit, in which a signal output end of a power management integrated circuit, a signal input end of a transmission branch, and a signal input end of a voltage reduction branch are coupled to a first node; a signal output end of transmission branch and a signal output end of the voltage reduction branch are coupled to a second node; the power management integrated circuit supplies an initial voltage to the first node; the transmission branch is coupled to a control signal terminal, and switch between a conducting state and a cutoff state in response to control of a control signal, and write the initial voltage into the second node in the conducting state; and the voltage reduction branch performs voltage reduction on the initial voltage at the first node to obtain a reduced voltage to be written into the second node.

Abstract: A reference voltage buffer circuit is provided, which could improve the reliability of the reference voltage buffer circuit, including: at least one output branch, where each output branch includes a delay control branch, a first MOSFET, and a second MOSFET; and a feedback branch, where in a first time period, the feedback branch is configured to output a first voltage to the delay control branch, and the delay control branch is configured to control the first MOSFET and the second MOSFET to be turned on, such that a source of the first MOSFET continuously outputs a reference voltage; and in a second time period, a voltage output from the feedback branch to the delay control branch is 0, the delay control branch is configured to control the second MOSFET to be turned off before the first MOSFET is turned off.

Abstract: This invention relates to current sensing, in particular for a signal processing circuit (500) for outputting an output signal (Sout) based on an input signal (Sin). An output stage (101) includes an output transistor (102) driven, in use, by a drive signal. A current monitor (501) is configured to monitor, in use, a first current through the output transistor, wherein the current monitor comprises a current sensor (105) having a sense transistor (106) configured to be driven based on the drive signal so as to generate a sense current related to the first current. A compensation controller (301) receives an indication of signal level of the input signal and controllably varies operation of the current monitor (501) so as to at least partially compensate for signal-dependent variation in a relationship between the first current and the first sense current.

Abstract: An example apparatus includes: a compensation circuit including: a current compensation output, a first transistor with a first current terminal and a first control terminal, the first current terminal coupled to the current compensation output, and a resistor ladder with a tap terminal coupled to the first control terminal, a current mirror circuit having a mirror input and a mirror output, the mirror input coupled to the current compensation output, and a rectification circuit having an input coupled to the mirror output.

Abstract: The disclosure provides a temperature compensation circuit that generates a temperature-compensated current and an integrated semiconductor circuit using the temperature compensation circuit. The temperature compensation circuit includes: a first PTAT current source which has a first emitter area ratio and generates a first current, the first current having a first temperature coefficient proportional to the absolute temperature; a second PTAT current source which has a second emitter area ratio and generates a second current, the second current having a second temperature coefficient proportional to the absolute temperature; an adjustment circuit which adjusts the current generated by the first PTAT current source; and a differential circuit which outputs the difference between the current adjusted by the adjustment circuit and the current generated by the second PTAT current source.

Abstract: A memory device includes a voltage generator configured to generate a reference voltage for transmission to at least one component of the memory device. The voltage generator includes a first input to receive a first signal having a first voltage value. The voltage generator also includes a second input to receive a second signal having a second voltage value. The voltage generator further includes a first circuit configured to generate third voltage and a second circuit coupled to the first circuit to receive the third voltage value, wherein the second circuit receives the first signal and the second signal and is configured to utilize the third voltage value to facilitate comparison of the first voltage value and the second voltage value to generate an output voltage.

Abstract: An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

Abstract: A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system.

Abstract: This disclosure relates to systems and methods for current source temperature compensation for use during cryogenic electronic testing. A temperature compensation circuit can provide a temperature compensation signal to a current source circuit configured to provide an electrical current for testing a cryogenic device under test to compensate for temperature effects on the current source circuit based on a time constant adjustment signal. The time constant adjustment signal can adjust a time constant of the temperature compensation circuit to delay by a given amount of time that the temperature compensation circuit compensates for the temperature effects on the current source circuit. A controller can be configured to execute a temperature compensation method to provide the time constant adjustment signal based on at least one temperature signal characterizing a temperature of an environment that includes the current source circuit or a temperature of the current source circuit.

Abstract: Systems and methods as described herein may take a variety of forms. In an example, a circuit includes a first voltage stepdown module and a second voltage stepdown module. The first voltage stepdown module has a supply voltage and a first reference voltage as inputs, and an intermediate stepped down voltage as an output, the intermediate stepped down voltage being electrically coupled to a feedback input of the first voltage stepdown module. The second voltage stepdown module includes a low-dropout voltage regulator having the intermediate stepped down voltage and a second reference voltage as inputs and a target voltage as an output.

Abstract: An internal voltage generation circuit may include: a voltage comparison circuit configured to generate a control voltage by comparing a reference voltage and an internal voltage which is fed back thereto; a voltage driving circuit configured to generate an internal voltage based on the control voltage; and a drivability control circuit configured to control the voltage level of the control voltage based on an enable signal which is activated during an active operation, in order to control drivability of the voltage driving circuit.

Abstract: A high-speed circuit with a high-voltage (HV) driver circuit. The high-speed circuit has a driver circuit and a level shifter. The driver circuit includes HV components which are operated in an HV domain. The level shifter includes low-voltage (LV) components which are operated in an LV domain. The level shifter translates signals from the LV domain to the HV domain to generate control signals for the driver circuit. The high-speed circuit may include a protection voltage generator converting a power supply voltage and a power ground voltage to generate a first direct-current bias voltage (VBP) and a second direct-current bias voltage (VBN) to bias the LV components of the level shifter. The LV components of the level shifter include input transistors and protection transistors. Gate voltages of the protection transistors may be tied to VBP or VBN.

Abstract: An oscillating circuit comprises a constant voltage supply circuit, a constant current supply circuit and an oscillating circuit; the constant voltage supply circuit is configured to output constant voltage; the constant current supply circuit is configured to output constant current; and the oscillating circuit is connected to the constant voltage supply circuit and the constant current supply circuit, and is configured to generate an oscillating signal with a preset frequency according to the constant voltage and the constant current.

Abstract: The present invention discloses a reference circuit with temperature compensation, which is characterized in that a current output circuit is designed to receive a reference voltage from a bias voltage generation circuit, generate two reference currents with opposite temperature variation characteristics, and then merge them into a compensated current with temperature compensation. In addition, a voltage output circuit is designed to receive a reference voltage from a bias voltage generation circuit, which includes several field-effect transistors operating in saturation regions, and a precision voltage increases with threshold voltages of the field-effect transistors to compensate for the temperature variation. Resistors can be incorporated or sizes of the field effect transistors can be changed to adjust the output current, output voltage or the temperature variation characteristics.

Abstract: A sense amplifying device includes a bit line bias voltage adjuster and a sense amplifying circuit. The bit line bias voltage adjuster receives a power voltage to be an operation voltage. The bit line bias voltage adjuster includes a first amplifier, a first transistor and a first current source. The first amplifier, based on the power voltage, generates an adjusted reference bit line voltage according to a reference bit line voltage and a feedback voltage. The first transistor receives the adjusted reference bit line voltage and generates the feedback voltage, wherein the first transistor is a native transistor. The sense amplifying circuit receives the power voltage to be the operation voltage, and generates a sensing result according to the adjusted reference bit line voltage.

Abstract: Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

Abstract: A voltage reduction circuit for a bandgap reference voltage circuit is provided, and the voltage reduction circuit includes a first transistor, a current mirror circuit, a voltage dividing circuit, an output resistor, and a fourth transistor. The first transistor receives an initial bandgap reference voltage from the bandgap reference voltage circuit. The voltage dividing circuit has a voltage dividing node for outputting a first dividing voltage. The fourth transistor receives the first divided voltage. The current mirror circuit forms a first current on the voltage dividing circuit through the first transistor, and mirrors the first current to the output resistor to form a second current. The voltage dividing circuit and the output resistor each have a first temperature characteristic, the first transistor and the fourth transistor each have a second temperature characteristic, thereby generating, a reference voltage independent of temperature and lower than the initial bandgap reference voltage.

Abstract: An integrated circuit includes a driving circuit and an enable control circuit. The driving circuit is configured to perform a setup operation based on a first driving current and perform a preset operation, using different driving currents, based on a first enable signal and a second enable signal. The enable control circuit is configured to generate the first and second enable signals.

Abstract: An activation circuit which can realize both of area reduction and current consumption reduction by more preferred embodiments. The activation circuit has an N-type MOS transistor having a gate terminal connected to a ground and having a threshold voltage in a vicinity of 0 V and a resistor interposed between a source terminal of the MOS transistor and a ground, wherein an electric potential of a drain terminal of the MOS transistor is controlled depending on a first signal output from a device serving as a drive target, and transmission of a second signal for activating the device is controlled depending on the electric potential of the drain terminal.

Abstract: A current flow control device includes a plurality of semiconductor switches disposed between a power source and a load and that are connected in parallel with each other, and the current flow control device being configured to control the flow of current between the power source and the load by turning on and off the semiconductor switches. The plurality of semiconductor switches include a first and a second semiconductor switch. The current flow control device includes a driving circuit configured to apply, to the first semiconductor switch, a voltage that is higher than a voltage output from the power source, to turn on the first semiconductor switch, a switch control unit configured to turn on the second semiconductor switch, and a resistor that is connected in series with a terminal on the power source side of the second semiconductor switch, the resistor lowering a voltage applied to the terminal.

Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

Abstract: A starting circuit capable of further reducing an influence of a variation in the threshold voltage of a transistor is proposed. The starting circuit includes an N-type first MOS transistor whose threshold voltage is near 0 V, a resistor interposed between a source terminal of the first MOS transistor and a ground, and a control circuit controlling a gate voltage of the first MOS transistor. An amount of first current transmitted to a device to be driven and starting the device is controlled according to the control of the gate voltage.

Abstract: An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for current sensing and current limiting. An example apparatus includes a first main transistor including a first main transistor gate terminal coupled between an output terminal and an intermediate node; a second main transistor including a second main transistor gate terminal coupled between the intermediate node and a ground terminal; a first amplifier including a first amplifier output coupled to the first main transistor gate terminal; a second amplifier including a second amplifier output coupled to the second main transistor gate terminal; and a third amplifier including a third amplifier inverting input coupled to the intermediate node, a third amplifier non-inverting input coupled to a sense transistor, and a third amplifier output coupled to a third gate terminal of a third transistor.

Abstract: A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system.

Abstract: A memory device including a voltage boosting circuit, a switching circuit and a word line driving circuit is provided. The voltage boosting circuit is activated in a sleep mode. The voltage boosting circuit, based on an activation signal, performs a voltage boosting operation on a power voltage of a power voltage rail to generate a boosting voltage and transmit the boosting voltage to a control voltage rail. The switching circuit is turned on or cut-off according to a first mode selection signal. The word line driving circuit generates a plurality of word line signals according to the boosting voltage in the sleep mode; in addition, the word line driving circuit generates the word line signals according to the power voltage in a normal mode.

Abstract: Disclosed are devices, systems, and methods for the use of memory including a data table configured to store a plurality of elements, wherein the plurality of elements are arranged into a plurality of buckets and each of the plurality of buckets comprising a plurality of entries. A first power domain can be associated with an entry of each bucket or with a first bucket. A second power domain can be associated with a second entry of each bucket or a second bucket. Processing logic can be configured to search for a particular value stored in an element of the plurality of elements by selecting buckets of the plurality of buckets and selecting at least one entry of each of the buckets. A programmable register can be used to select a powered state of the second power domain based on a configuration of the programmable register.

Abstract: A voltage reference includes a flipped gate transistor coupled between a first node configured to carry an operating voltage and a second node configured to carry a negative supply voltage. A first transistor and a second transistor are coupled in series between the first node and the second node, a gate of the first transistor is coupled with a gate of the flipped gate transistor, and a gate of the second transistor is configured to receive the negative supply voltage. An output node between the first transistor and the second transistor is configured to output a reference voltage, and a current source coupled between the output node and the second node is configured to supply a current through the first transistor based on a current through the flipped gate transistor.

Abstract: An apparatus is provided which includes: a first supply node; a second supply node; a first transistor coupled to the first supply node, the first transistor is to provide a first current which is complementary to absolute temperature (CTAT); a second transistor coupled to the first supply node, the second transistor is to provide a second current which is proportional to absolute temperature (PTAT); a resistive device coupled in series at a node with the first and second transistors, and coupled to the second supply node, wherein the node is to sum the CTAT and the PTAT currents.

Abstract: A charging circuit for an electrical energy storage system having electrical energy storage units. The charging circuit includes a first input and a second input for electrically connecting to an energy source, a first output and a second output, and first pole connections and second pole connections. The pole connections are connected in an electrically conductive manner to corresponding pole connections of the electrical energy storage units. In addition, the charging circuit includes first switches, second switches, and third switches.

Abstract: The reference voltage generation device includes a constant current circuit which includes a first MOS transistor, and a voltage generation circuit which includes a second MOS transistor. The first MOS transistor includes a gate electrode, a source region, a drain region, and a channel impurity region which have a first conductivity type and has a first channel size. The second MOS transistor includes a gate electrode of a second conductivity type, and a source region, a drain region, and a channel impurity region which have the first conductivity type and has a second channel size different from the first channel size. The channel impurity regions have different impurity concentrations.

Abstract: A power converter can include: first and second terminals; N A-type switching power stage circuits, each having a first energy storage element, where N is a positive integer, a first terminal of a first A-type switching power stage circuit in the N A-type switching power stage circuits is coupled to the first terminal of the power converter, and a second terminal of each of the N A-type switching power stage circuits is coupled to the second terminal of the power converter; one B-type switching power stage circuit; and N second energy storage elements, each being coupled to one of the N A-type switching power stage circuits, and the B-type switching power stage circuit is coupled between a terminal of one of the N second energy storage elements corresponding to the B-type switching power stage circuit and the second terminal of the power converter.

Abstract: The present invention provides a driving system operating in a first or second modes. The driving system includes first and second resistance adjusting circuits, a divider, a controller and a driver. The divider divides a second resistance adjusting signal generated by the second resistance adjusting circuit by a standard value to generate a first control signal. The controller receives the first control signal and generates a second control signal. When the driving system operates in the first mode, the driver receives the second control signal, according to the second control signal, the driver adjusts an output impedance of itself and adjusts equalization amplitude of a first differential output signal generated by itself. When the driving system operates in the second mode, the driver generates a second differential output signal and adjusts the output impedance according to a first resistance adjusting signal generated by the first resistance adjusting circuit.

Abstract: A current regulating apparatus capable of regulating an electrical current with a high level of precision and over a wide range of voltages includes a first depletion mode field-effect transistor (FET), a second depletion mode FET, and a fixed resistor. The second depletion mode FET and fixed resistor are connected in series and across the gate-source terminals of the first depletion mode FET. The first depletion mode FET operates as an adjustable current source while the second depletion mode FET is controlled to operate as a voltage controlled resistor. The magnitude of current regulated by the current regulating apparatus is determined based on both the resistance of the fixed resistor and a current-setting control voltage applied to the gate of the second depletion mode FET. Various precision values of regulated current can be realized by simply changing the current-setting control voltage.

Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit.

Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.

Abstract: An apparatus includes transistor and a set of one or more serially-connected diodes coupled to the transistor. The transistor includes a gate, and first and second terminals. A first diode in the set of serially-connected diodes has a first terminal connected to the second terminal of the transistor. At least one of the diodes includes a first layer including silicon having a first type of carrier as its majority carrier, a first terminal, and a second terminal. The first terminal includes a second layer formed on the first layer, a third layer comprising amorphous hydrogenated silicon having a second type of carrier as its majority carrier formed on the second layer, and a conductive layer formed on the third layer. The second terminal includes a fourth layer comprising crystalline hydrogenated silicon of the first carrier type formed on the first layer, and a conductive layer formed on the fourth layer.

Abstract: Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include converter circuitry that operates to provide a drive current. The integrated circuit may include process detector circuitry having multiple drive strength devices that are driven by the drive current from the converter circuitry. The multiple drive strength devices may provide multiple drive strength signals based on the drive current. The integrated circuit may include comparator circuitry having a comparator that receives the multiple drive strength signals from the multiple drive strength devices, detects a voltage difference between the multiple drive strength signals, and provides an output signal based on the detected voltage difference.

Abstract: An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.

Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Abstract: An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.

Abstract: A method for controlling a brushless direct current (BLDC) motor is disclosed. The method includes: receiving a constant current; comparing the constant current to a reference current; based on the comparison revealing that the constant current is smaller than the reference current, providing a first speed command to the rotational speed control unit to increase a speed of the BLDC motor; based on the comparison revealing that the constant current is larger than the reference current, providing a second speed command to the rotational speed control unit to decrease a speed of the BLDC motor; based on the comparison revealing that the constant current is the same as the reference current, providing a third speed command to the rotational speed control unit to maintain a speed of the BLDC motor; and controlling, by the rotational speed control unit, a speed of the BLDC motor.

Abstract: An ORing circuit is provided. The ORing circuit includes an input port, an output port, an ORing FET, a comparing circuit, a first transistor and a second transistor. The ORing FET is connected between the input port and the output port and comprises a source connected with the input port, a gate and a drain connected with the output port. The comparing circuit is connected with the input port and the gate. The first transistor comprises a first terminal, a second terminal and a third terminal. The first terminal is connected with the input port and the source, and the third terminal is connected with the gate. The second transistor comprises a fourth terminal, a fifth terminal and a sixth terminal. The fourth terminal is connected with the output port and the drain, and the sixth terminal is connected with the second terminal of the first transistor.

Abstract: This invention is an SOC with an integrated single rail power supply that interfaces with the host controller and dynamically changes the host interface supply to 3.3 volts or 1.8 volts based on the sensed card speed grade. The SOC initially selects 3.3 volts to supply to the memory card. The SOC communicates with memory card vis input/output circuits to determine a memory type. The controller selects a 3.3 volt or 1.8 volt supply for the memory card based upon the determination. The SOC powers the input/output circuits at the same supply voltage as the memory card. This invention employs 1.8 volt transistors in the input/output circuits using a bias voltage to protect these transistor from the full 3.3 volt power when the memory card is powered to 3.3 volts.