Abstract: A differential current mode amplifier circuit (5,5′) includes a first circuit leg having a first current source providing a current I1 coupled in series with a first transistor (m1) at a first circuit node (n1). The first transistor has a control terminal for coupling to an input signal potential (Vs). Vs is obtained from a unit cell of a radiation detector array, and is indicative of a magnitude of an integrated, photon-induced charge. The first circuit leg outputs a first output current (Is). A second circuit leg includes a second current source providing a current I2 coupled in series with a second transistor (m2) at a second circuit node (n2). The second transistor has a control terminal for coupling to an input reference potential (Vr). The second circuit leg outputs a second output current (Ir). A resistance (Rs) is coupled between the first circuit leg and the second circuit leg at the first circuit node and the second node.

Abstract: A comparator having a differential amplifier with a signal input to receive an input signal and a reference input to receive a reference voltage, and having a controllable bias current source for supplying to the differential amplifier a bias current that has a low quiescent current or a higher active current as a function of whether the input signal is constant or variable. The controllable bias current source is further configured to adjust the bias current in accordance with the rate of change of the input signal.

Abstract: An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier circuit D1 with two current paths L1 and L2, and an inverter INV. The output section of the current mirror circuit M is used as a constant current source for the differential amplifier circuit. The current mirror circuit M includes a load MOS transistor 1, a MOS transistor 2 constituting an input section, and a MOS transistor 10 constituting an output section. The current path L1 of the differential amplifier circuit D1 includes a load MOS transistor 11, an amplifying depletion type MOS transistor 13, and an input terminal in1. Similarly, the current path L2 includes a load MOS transistor 12, an amplifying depletion type MOS transistor 14, and an input terminal in2. The inverter INV is constructed with a load MOS transistor 3 and a switching transistor 4.

Abstract: A transimpedance circuit adapted for use in a subscriber line interface circuit includes sense resistors installed in closed loop, negative feedback paths of respective sense amplifiers. Voltage drops across the sense resistors are applied to first and second differential coupling circuits for applying differential currents to complementary polarity inputs of an operational amplifier. The inputs of the amplifier are also coupled to a linearity compensator, that is configured to provide sufficient overhead voltages in the presence of worst case voltage swing conditions. The compensator has a differential amplifier configuration, that closes a negative feedback loop from the output of the amplifier and one of its inputs, relative to a reference voltage balancing path coupled to the amplifier's other (complementary) input.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a signal generation circuit which provides a differential current. The resolving circuit is coupled to a latching circuit. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal setup and hold times are inherently very small due to the high intrinsic bandwidth of the receiver. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 m Volt) voltage differences, reduced capacitive loading, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: A circuit and method for reducing a propagation delay associated with a comparator and a comparator employing the circuit or method. In one embodiment, the comparator, includes: (1) an input stage that receives a differential input signal and develops therefrom a threshold signal, (2) an output stage, coupled to the input stage, that develops a level shifted single-ended output signal as a function of the threshold signal, and (3) a speed-up circuit, associated with the input stage, that reduces a time period to develop the determinant signal thereby decreasing a propagation delay in developing the level shifted single-ended output signal from the differential input signal.

Abstract: A level detector enables high speed operation at low voltage with eliminating dependency to fluctuation of a power source voltage and tolerance in a device, and further permits stable operation. The level detecting circuit performs predetermined level shifting of a voltage level of an input signal input from a load voltage generating circuit, with a resistance type potential division by a voltage dividing resistor element using a reference power source voltage independent of a power source voltage to be supplied to own circuit. In this case, a differential amplifier feeds an output depending upon a difference between a level shifted signal from the level shifter and a predetermined reference voltage for leading an output thereof as a detection output. Also, since the reference power source independent of the power source voltage is used, influence of fluctuation of the power source voltage for the circuit is restricted to realize stable operation.

Abstract: This invention relates to source-coupled logic (SCL) which is a functional derivative of emitter-coupled logic (ECL). ECL is widely recognized as having the characteristics of high speed (low propagation delay) and low power supply noise generation. The SCL of the prior art succeeds at maintaining and improving the low noise characteristics of this architecture but does not fulfill the promise of high speed that one would expect from a current-mode logic. In addition, it uses a differential form of logic that is not as flexible and easy-to-use as a reference controlled or “single-ended” logic. The SCL disclosed here has the desired high speed properties and maintains the ease of use that is a property of reference controlled ECL. In addition, the reference controlled SCL of this invention provides new capabilities that make it even more flexible than ECL in generating logical switching functions.

Abstract: A comparator circuit includes a differential input stage, a second differential stage having a differential output, and an output stage transforming an output signal from the differential output of the second differential stage into an output signal having a logic level. The comparator further includes a common mode measuring stage. The common mode measuring stage includes a differential pair of input transistors and a differential pair of complementary transistors biased by respective current generators, and a current mirror summing the differential output currents of the two complementary transistors pairs into a single output current signal. A switching stage is controlled by the differential output nodes of the second differential stage. A common source node of the switch stage is coupled to the output of the common mode measuring stage and to the differential output nodes of the differential input stage.

Abstract: Circuitry is provided for detecting threshold crossings of an input signal which is generally sinusoidal or otherwise periodic, but which is subject to either high-frequency noise which would cause erroneous multiple threshold crossings, or low-frequency noise which would cause erroneous failure to detect a threshold crossing. Two detection elements detect the crossing of two different threshold values and produce detection signals reflecting whether the input signal is above or below their thresholds. For noisy input signals, these detection signals may be bouncy. High- and low-true versions of the detection signals are logically combined to produce a first signal which is active only while the input signal moves in one direction, and is masked from the active state while the input signal moves in the other direction. Likewise, a second signal is produced which is active the opposite way. The first and second signals set and reset a latch, whose output state represents the threshold crossing.

Abstract: A comparator is operable within a wide supply voltage range. A source follower is connected at the output side of a differential amplifier stage, and a switch closes a feedback loop from the source follower to the differential amplifier stage. A diode, which has the same conductivity type as the conductivity type of the transistor used as the switch, is provided in order to set the operating point of the differential amplifier stage.

Abstract: A collector of a transistor Q3 to a base of which an amplifier signal Sa generated from the differential amplifier is input is connected with one end of the resistive element RC1 and one end of a resistive element RC2. Other ends of the resistive element RC1 and RC2 are connected with a power source level Vcc and a base of the transistor Q3, respectively. When the emitter of the transistor Q3 is shorted to a ground level GND, for example, in case that a capacitive element CP is not charged enough, the electric potential of the collector of the transistor Q3 is lowered, and the electric potential of the base of the transistor Q3 is also lowered. Accordingly, inflow of the excess current to the transistor Q3 can be prevented.

Abstract: The invention provides a semiconductor circuit which can accept signals of various levels and operate at a high speed with low power dissipation. The semiconductor circuit includes a PMOS differential circuit having two inputs one of which is connected to a first input terminal and the other of which is connected to a second input terminal, an NMOS differential circuit having two inputs one of which is connected to the first input terminal and the other of which is connected to the second input terminal, and an output circuit operable in response to differential outputs of the PMOS differential circuit and the NMOS differential circuit for preventing, when a current path is formed between an output terminal and a power supply terminal, formation of a current path between a ground terminal and the output terminal, but preventing, when a current path is formed between the output terminal and the ground terminal, formation of a current path between the power supply terminal and the output terminal.

Abstract: An interface circuit includes first and second current mirrors, first and second input circuits, and a reference setting unit. Each of the first and second current mirror circuit has a current input terminal and a current output terminal. The first input circuit has a first transistor having a gate to which an input signal is input and a drain connected to the current output terminal of the first current mirror circuit. The second input circuit has a second transistor having a gate to which a predetermined reference voltage is input and a drain connected to the current output terminal of the second current mirror circuit. The reference setting unit is connected to the current input terminal to set a current amount flowing to the current output terminal as a logic determination level of the first transistor. A method of setting a determination level for the interface circuit is also disclosed.

Abstract: A three input comparator facilitates the comparison of a signal to the greater of two different reference voltages in a manner which mitigates propagation delay. A first differential pair of transistors facilitates comparison of the two reference voltages to one another, while second and third differential pairs of transistors facilitate comparison of the signal to the higher of the two reference voltages.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: The average value of an input signal supplied to an input terminal is generated by an integrating circuit consisting of a series circuit of a capacitor, a constant-current source transistor, and a resistor. The average value is used as the reference voltage for the differential amplifier circuit. Further, to each of differential pair transistors the sources of which are commonly connected, other transistors are cascode connected, respectively. Supplied to each gate of the cascode connected transistors is a divisional voltage of the differential voltage between the average voltage from the integrating circuit and the circuit power supply voltage, which divisional voltage is obtained by a capacitive divider circuit.

Abstract: An input circuit has an inverter and a differential amplifier, which are respectively connected on an input side to an input and on an output side to an output of the input circuit. The input circuit has two operating modes defined by an activation signal, the differential amplifier being activated and the inverter being deactivated in a first operating mode, and the differential amplifier being deactivated and the inverter being activated in a second operating mode. In this manner, the input circuit has the advantage of selective operation with LVTTL or SSTL levels.

Abstract: A differential threshold comparator is provided which includes an input stage and a threshold stage, both supplied with current by a common current mirror. Both stages are differential comparators, with the input stage having terminals for receiving an input signals and the threshold stage having terminals for receiving a threshold voltage. The threshold comparator produces a signal which indicates whether the difference between input signal voltages exceeds the threshold voltage.

Abstract: A voltage shift circuit included in an input buffer for a semiconductor integrated circuit device converts an external reference potential to a first signal of a predetermined potential. A voltage shift circuit converts the external signal obtained by superposing a logic signal of a small amplitude on an external reference potential to a second signal obtained by superposing a complementary signal of the logic signal with small amplitude on the first signal. Differential amplifying circuit compares the potentials of the first signal and the second signal and applies a signal corresponding to the result of comparison to internal circuitry. Therefore, normal operation is ensured even when an arbitrary potential between 1.25 V to 2.9 V is applied as the external reference potential.

Abstract: A circuit configuration for a comparator provides that first and second transistors on an input side are connected jointly by their two control terminals to a first input terminal, and that the first and second transistors have different cutoff voltages. Such a circuit configuration has the advantage that at a zero-volt input voltage, no current is consumed. The circuit configuration can be connected directly to a high-voltage supply without the aid of regulating voltages or high-precision reference voltages.

Abstract: A differential receiver having a precision input referred offset and a wide CMR, wherein a pair of differential-difference amplifiers are used as differential comparators. The differential-difference amplifiers are configured to allow a precision input-referred offset to be set by the use of two reference voltages. The differential comparators each have a common-mode range over a different portion of the rail-to-rail voltage range. A first one of these differential comparators is activated when the input common-mode voltage is above a threshold level. A second differential comparator is activated when the input common-mode voltage is below the threshold. The output of the differential comparator that is selected is to provide a comparison output signal, thereby achieving a wide CMR. The selection of either the first or second differential comparator is made by a selection circuit that includes a differential Schmitt Trigger and a multiplexer.

Abstract: A backlighting circuit for user interface in an electronic device includes at least one light emitting diode optically coupled to the user interface wherein the at least one light emitting diode provides backlighting for the user interface. A current source is electrically coupled in series with the at least one light emitting diode wherein the current source controls a current through the at least one diode. In addition, a brownout detection circuit determines a brownout condition for the user interface responsive to the current through the diode. Related communications devices and methods are also discussed.

Abstract: A differential circuit used in an input interface of a memory device comprises a current mirror including a pair of P-channel transistors, a differential pair including a pair of N-channel transistors for receiving a reference voltage and an input signal voltage, respectively, and another N-channel transistor connected between the common sources of the pair of N-channel transistors and GND line. The another N-channel transistor has a gate maintained at a constant potential irrespective of the fluctuations of the source voltage, thereby suppressing a current increase due to variations of the source voltage and reference voltage. The constant voltage is generated in the memory device itself and used for another purpose.

Abstract: A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.

Abstract: The present invention provides a differential amplifier. The differential amplifier includes first and second inputs and an output. The differential amplifier further includes a lateral bipolar transistor. The lateral bipolar transistor includes a well region that has a base region, an emitter region and first and second collector regions. The first and second collector regions are spaced apart from the emitter. The lateral bipolar transistor also includes a first gate, coupled to the first input, to overlay a space between the emitter region and the first collector region. Furthermore, the lateral bipolar transistor includes a second gate, coupled to the second input, to overlay a space between the emitter region and the second collector region. The differential amplifier further includes first and second load devices coupled to the first and second collector regions.

Abstract: A circuit for controlling the bias current in a differential amplifier is disclosed. A differential amplifier comprising complementary differential input transistor pairs includes variable bias current sources to provide bias currents to the differential input pairs. The variable bias current sources are coupled to an input current control unit that includes one or more programmable switches to vary the amount of bias current supplied to the differential input pairs. The slew rate, differential gain, and common mode input range of the differential amplifier may be varied by adjusting the bias currents to the differential input pairs. A cascode circuit is coupled between the differential input pairs and their respective load circuits to extend the common mode input range to the supply voltage rail values.

Abstract: A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitudes and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output.

Abstract: In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors.

Abstract: An input first stage circuit performing switching between activation and inactivation in response to an input signal includes a differential amplifier for comparing the input signal with a reference voltage and a switching transistor for receiving a power supply disconnection signal to control the power supplied, and a level detection circuit including a low level standby detector for detecting a low level of the input signal and a high level standby detector for detecting a high level of the input signal.

Abstract: A comparator circuit providing for improved symmetry of operation. The circuit includes two delay paths to facilitate rising and falling input transitions. Such paths are made up of an equal number and type of current mirrors. The circuit also includes an input differential pair wherein both delay paths are coupled to a single transistor of the pair.

Abstract: Minimal headroom, minimal area, multi-terminal current steering circuits for steering a current from a current source to any one of a plurality of outputs. The steering circuit provides controls to individual steering transistors so as to turn on the selected one of the plurality of steering transistors responsive to steering control signals. Minimal headroom is required, and beta dependent errors in the current output are minimized, by steering the current source through only a single transistor to the selected output. This also minimizes chip area. Alternate embodiments are disclosed and described.

Abstract: A differential amplifier circuit has a differential amplifier circuit section for amplifying a difference voltage between an inverting input node and a non-inverting input node, and an output buffer circuit for outputting, to an output node, the amplified difference. The differential amplifier circuit section is connected to a first high potential power supply node and a first low potential power supply node, and is driven by potentials applied to the first high potential and first low potential power supply nodes. The output buffer circuit is connected to a second high potential power supply node and a second low potential power supply node, and is driven by potentials applied to the second high potential and low potential power supply nodes.

Abstract: A semiconductor integrated circuit device with a high voltage detection circuit comprises a high voltage step-down circuit for stepping down a high voltage input and outputting the stepped-down voltage, a reference voltage generator for generating plural reference voltages, a reference voltage selector for selecting one of the plural reference voltages, a high voltage detection circuit for comparing the stepped down voltage with the selected reference voltage to detect a high voltage and a control circuit for controlling the voltage drop of the high voltage and selection of the plural reference voltages to set the high voltage to be detected by the high voltage detector.

Abstract: A CMOS output circuit including a differential error amplifier (3) is operated to provide a stable quiescent bias current in an output MOSFET by causing a first current equal to a threshold voltage of a P-channel reference MOSFET (M1) divided by the resistance of a reference resistor (R1) to flow through an N-channel current mirror control MOSFET (M4). A first N-channel current mirror output MOSFET (M6) having a gate coupled to the gate of the N-channel current mirror control MOSFET (M4) and a drain coupled to a drain of the P-channel reference MOSFET (M1) causes a second current proportional to the first current to flow through the P-channel reference MOSFET (M1). The first current is controlled in response to feedback from the P-channel reference MOSFET (M1). A bias current in an error amplifier (3) is controlled in response to the N-channel current mirror control MOSFET (M4).

Abstract: A high-speed, differential pair input buffer is constructed from a conventional differential pair having a data input terminal, a reference voltage input terminal, and an output terminal. A voltage source Vsupply and its ground connection are coupled to the differential pair through a first pair of transistors. The first pair of transistors have their enable inputs coupled to the data input terminal so that they are both biased "on" during a transition in a logic signal delivered to the data input terminal. The output terminal of the differential pair is connected through a delay circuit to the enable input terminals of a second pair of transistors, which also interconnect the differential pair to the voltage source V.sub.supply and system ground. Thus, the second pair of transistors provide a feedback path to enable the differential pair to conduct current longer if a load connected to the output of the differential pair slows the transition of the output of the differential pair.

Abstract: A semiconductor device consuming a first voltage includes a voltage-detection circuit which detects a voltage level of the first voltage, and a control circuit which controls the voltage-detection circuit to operate for a predetermined time period in accordance with a timing at which the first voltage is started to be consumed.

Abstract: A differential input buffer (14) and method of construction are provided. The differential input buffer (14) includes a differential amplifier (54, 56, 50, 52, 62, 64) connected to receive an input signal (IN). A local reference voltage generator (68, 70, 72) is connected to the differential amplifier (54, 56, 50, 52, 62, 64) and is connected to receive an external voltage reference (BLR) and to provide a local reference voltage (VREF) to the differential amplifier (54, 56, 50, 52, 62, 64). The local reference generator (68, 70, 72) is adjustable during construction to produce a desired level for the local reference voltage (VREF). The differential input buffer (14) also includes a hysteresis element (66, 74) that is connected to provide feedback to the differential amplifier (54, 56, 50, 52, 62, 64) and includes a buffer stage (76, 78, 80, 82, 84, 86) that is connected to receive an output of the differential amplifier (54, 56, 50, 52, 62, 64) and to drive an output signal (OUT).

Abstract: The circuit arrangement compares a quantity supplied by a first neuron MOS field effect transistor (M1) to a reference quantity that is made available by a reference source (R). A current mirror (SP) is provided therefor, this enabling a comparison of a second current (I.sub.2) supplied by a reference transistor (R) to a first current (I.sub.1) supplied by the first neuron MOS field effect transistor (M1). The evaluator circuit is activated or, respectively, decoupled by a first switch unit (S1) and a second switch unit (S2). What is thereby achieved is that no current flows in the evaluator circuit in the quiescent condition. The comparison result is applied to an inverter unit (IS). Since the inverter unit (IS) is decoupled from the evaluator circuit by the first switch unit (S1), an undefined level is never adjacent at the output (AIS) of the inverter unit (IS). This can be advantageously utilized in the further data processing in following stages.

Abstract: An input buffer includes an n-channel FET having a drain region coupled to the V.sub.cc voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. A bias circuit maintains a voltage at the source of the n-channel FET which is greater than the V.sub.SS supply voltage when a logic low voltage is applied to the input terminal.

Abstract: A window comparator includes a differential circuit stage and a load circuit stage. The differential circuit stage produces a pair of differential currents from an input voltage, the differential currents varying depending on the input voltage with having a maximum and a minimum when the input voltage is a reference voltage. The load circuit stage produces an output voltage from a reference current and a current corresponding to a selected on of the differential currents. The reference current and the current are produced such that a voltage range is determined around the predetermined voltage depending on whether the second current is greater than the reference current. Since a window of the window comparator is formed based on the current and the reference current, the output voltage changes in level depending on whether the input voltage falls into the voltage range.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: A differential comparator is provided with an extended input range. In one embodiment, a differential amplifier is provided with a differential input buffer that allows for differential detection even with input voltage signal levels that extend two or more volts beyond the power supply voltage. A first transistor and a first resistor coupled in series are coupled in parallel with a second transistor and a second series resistor. The transistor drain terminals are both coupled to the power supply voltage, and a current source draws current from the common node of the resistors. Input voltages are supplied to the gates of the transistors, and the differential output voltages are provided from the transistor source terminals. A differential amplifier receives the differential output voltages and provides a single output voltage.

Abstract: A voltage comparator for comparing a first input voltage to a second input voltage includes a first transistor having a gate to which the first input voltage is applied and a second transistor having a gate to which the second input voltage is applied. Third and fourth transistors, coupled to the first and second transistors respectively, each conduct a first current in response to a first reference voltage being applied to a gate of each transistor. A fifth transistor is coupled to the first and second transistors and has a gate to which a second reference voltage is applied to maintain a sum of currents conducted by the first and second transistors equal to a second current. A reference generation circuit is coupled to the third, fourth and fifth transistors and is configured to generate the first and second reference voltages having magnitudes which set the second current equal to twice the first current.

Abstract: In a sample-and-hold circuit, an input is tracked at an output during a tracking period and the input is held during an holding period, the tracking period and holding period defined by a clock signal input to the sample-and-hold circuit, wherein the output is a differential output having a positive output node and a negative output node with the output signal represented by a voltage difference from the negative output node to the positive output node. During the tracking period, an equalizing transistor between the output nodes is turned on to bring the output to a common mode level for the output. During the holding period, the equalizing transistor is turned off and a regenerative circuit drives the output nodes apart, thus amplifying the input signal.

Abstract: An electrical input buffer circuit is provided for receiving an input signal such as an electronic spark timing signal and providing an output signal despite the presence of noise. The input buffer circuit receives a control signal and a reference voltage signal, and the voltage potential therebetween provides a differential input. A voltage divider network is coupled between the inputs for producing a first voltage potential and a second voltage potential in response to the differential input. A differential pair of NPN type transistors compares the control signal to a threshold value. The input buffer circuit produces an output high or low signal as a function of the input control voltage and is allowed to operate above and below local ground.

Abstract: A level comparator has a first and a second input terminal, an output terminal and a first and a second power terminal. In the comparator, the gate of a first MOS transistor is connected to the first input terminal. The gate of a second MOS transistor is connected to the second input terminal and the source of the second MOS transistor is connected to the source of the first MOS transistor. A current source is connected between the source of the first MOS transistor and the first power terminal. The drain and gate of a third MOS transistor are connected to the drain of the first input terminal and the source of the third MOS transistor is connected to the second power terminal. The drain of a fourth MOS transistor is connected to the drain of the second MOS transistor. The gate of the fourth MOS transistor is connected to the gate of the third MOS transistor. And the source of the fourth MOS transistor is connected to the second power terminal.

Abstract: An output circuit comprising a pair of input-stage transistors supplied with an input signal, a pair of output-stage differential transistors constructing an output-stage differential circuit, a pair of wiring lines having first ends connected to the input-stage transistors, respectively, and second ends connected to the bases of the output-stage differential transistors and connecting the input-stage transistors and the output-stage transistors, respectively, a pair of input-stage constant current sources connected to the bases of the output-stage differential transistors, respectively, at the second terminals, and an output-stage constant current source connected to the output-stage differential transistors.

Abstract: Briefly, in accordance with one embodiment of the invention, a circuit includes: at least one differential amplifier. The differential amplifier is coupled in a circuit configuration so that the differential output voltage signal of the differential amplifier circuit includes a scalable second-order harmonic component of the differential input voltage signal applied to the differential amplifier circuit. Briefly, in accordance with another embodiment of the invention, a method of applying a differential input voltage signal to a differential amplifier circuit to produce a differential output voltage signal includes the step of: driving the differential amplifier circuit so that the differential output voltage signal of the differential amplifier circuit includes a second-order harmonic component of the differential input voltage signal.

Abstract: A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.