Abstract: A first demodulator for generating a demodulated signal by demodulating first and second baseband signals obtained from a received frequency shift keying signal, comprises: a first mixer for mixing the first baseband signal with the second baseband signal; a frequency divider for 1/2-frequency-dividing an output of the first mixer; a second mixer for mixing the first baseband signal with an output of said frequency divider; and a frequency judging circuit for judging whether or not a frequency of an output of the second mixer is larger than a reference value to generate the demodulated signal. In order to effect the frequency judging by the frequency judging circuit always at a high frequency, there may be further provided a first inverter after the first mixer, a second inverter after the frequency judging circuit for compensating the inverting of the first inverter, and a frequency comparing circuit for detecting the frequency of the output of the first mixer.

Abstract: An FSK radio receiver of direct conversion type, which derives baseband in-phase and phase quadrature signals from a received FSK RF signal in respective mixers by applying local oscillator signals to the mixers differing in phase by 90.degree., in which wide-band baseband 90.degree. phase shifting circuits formed of only digital logic elements phase shift the in-phase and phase quadrature signals to enable a demodulated digital data signal to be obtained by subsequent digital processing. In that processing, signals having a frequency that is double that of the in-phase and phase quadrature signals are derived and used to derive the demodulated data signal, ensuring high accuracy of detection and lowering the accuracy required for the local oscillator frequency.

Abstract: In the modulation and demodulation of a plurality of frequency separated channels on a radio frequency carrier by digitally coded speech or data, the speech or data is modulated on a digitally generated sub-carrier by quadrature phase shift keying and after conversion to analogue form the modulated sub-carrier is mixed with an RF carrier of fixed frequency to produce the signal for transmission. Reception and demodulation of the transmitted signal are effected by the reverse processes. Frequency multiplication is effected after the digital to analogue conversion by producing analogue samples of very short duration and applying them to a suitable filter. Frequency division during the analogue to digital conversion is effected by sub-sampling.

Abstract: A digital FSK demodulator used in e.g. a telephone loop produces unequal amplitudes in detected mark and space tones. The inequality or offset must be cancelled so that a proper timing signal can be recovered from the FSK signal. The demodulator includes a digital compensation circuit for offset cancellation in which peak amplitudes of digital 0 and digital 1 signals are continuously monitored. The peak amplitudes are then averaged to obtain an offset estimation which is subtracted from the output of the demodulator for offset compensation.

Abstract: A demodulator (414) for improving bit error rate performance where alternating bit patterns produce the worst occurrences of bit errors. The demodulator (414) consists of a zero threshold comparator circuit (502), a first threshold detector circuit (508), and a second threshold detector circuit (504). The zero threshold comparator circuit (502) receives a frequency information signal and slices it into a plurality of bits (522). The first threshold detector circuit (508) compares the frequency information signal to a predetermined threshold, which is selected to optimize bit error rate performance. The second detector threshold circuit (504) is used to ensure that an alternating bit pattern has occurred.

Abstract: An FSK signal receiving device is constituted by a first phase shifting circuit for applying a first phase shift to a first reception base band signal of first and second reception base band signals having orthogonal phases to generate a third base band signal, and generating a fourth base band signal having a phase orthogonal to the phase of the third base band signal, a second phase shifting circuit for applying the first phase shift to the second base band signal to generate a fifth reception base band signal, and a logical gate circuit for performing an exclusive OR operation on the third and fourth base band signals to obtain a first output signal, on the third and fifth base signals to obtain a second output signal, and on the first and second output signals to generate a detection signal.

Abstract: A frequency-shift keying (FSK) signal detector splits an FSK signal into two paths. In one path, a phase-altering circuit having a variable frequency characteristic between the two encoding frequencies of the FSK signal provides either a phase lead or a phase lag depending upon the instantaneous frequency of the FSK signal. The phase-altered signal is sampled in response to the signal in the second path to decode a digital signal.

Abstract: A digital FSK receiver includes a zero-crossing detector which detects the zero crossings in an FSK signal having at least two signal frequencies. The time interval between zero crossings is then measured with a first interval value corresponding to one of the signal frequencies and a second interval value corresponding to the other signal frequency. An accumulator outputs a digital signal which depends on whether the interval is at the first value or the second value, the digital signal including logical zeros and ones.

Abstract: An FSK demodulator for demodulating first and second baseband signals obtained from a received frequency shift keying signal, the first and second baseband signals having a quadrature relation therebetween, a lead and lag relation between the first and second baseband signals being changed in accordance with frequency shift from a carrier frequency of the frequency shift keying signal, comprises: a voltage change judging circuit for judging whether a magnitude of the first baseband signal increases or decreases within a predetermined interval; and an inverting circuit responsive to an output of the voltage change judging circuit and the second baseband signal for outputting a demodulated signal produced by inverting the second baseband signal in accordance with the output of the voltage change judging circuit.

Abstract: A data receiving system comprising an I base-band signal and a Q base-band signal which are used in a quadrature demodulation operation. Zero-crossing points of respective base-band signals are detected and a control signal is generated in response to each zero-crossing point. A phase-shift switching circuit alternately selects either the I base-band signal or the Q base-band signal in response to the control signal to generate an I/Q base-band signal. And, a demodulation operation is executed on the basis of the I/Q signal.

Abstract: An MSK signal demodulating circuit including a carrier reproducing circuit for reproducing a carrier phase-synchronized with a component of a mark frequency or a space frequency of an MSK signal, a detector for performing synchronous detection of the MSK signal by means of the reproduced carrier, an identification circuit for converting an analog output from this detector into serial digital data, and a serial-parallel conversion circuit for converting the serial digital data into I, Q parallel data.

Abstract: A receiver for FSK signals produces quadrature related first and second frequency down-converted difference signals (I and Q), which are amplitude limited to form respectively first and second square wave signals. The first and second square wave signals are sampled at changes in polarity of the second and first square wave signals, combined and fed to a memory, for example a hysteresis circuit, responsive to a change in polarity in the combined signal for producing a first substantially constant dc output until the next following change in polarity is detected whereupon a second substantially constant dc output is produced. By using a memory rather than a filter, reactive components are avoided making it less expensive to integrate. Also, a fixed level bit slicer can be used.

Abstract: Digital FSK demodulators to be used in the telephone environment are disclosed. The demodulator according to one embodiment uses the sequential processing of a digital signal encoded in the fractional two's complement numeric representation. The use of multipliers is largely eliminated, thus enabling extensive use of simple shift registers and adders. Consequently the hardware complexity requirement is greatly reduced, thus resulting in very low cost products.

Abstract: A frequency error detecting apparatus for an FSK signal communication system in which data symbols are represented by frequencies displaced from a center frequency, includes a counter for counting the number of each type of data symbol in a received signal over a specific period of time, and a multiplier for multiplying the counted number of symbols by the displacement frequency for each symbol to produce a correction value. A counting unit counts the total number of cycles of the received signal over the specific time period to output a counted number which is proportional to the center frequency of the received signal. The correction value is subtracted from this counted number so that a corrected center frequency may be produced which is then compared with the internal center frequency of the receiver, so that a frequency error may be determined.

Abstract: An external digital phase locked loop for use in connection with a conventional serial communication controller is driven by a clock whose frequency is ten times the nominal data rate. Bit cells are divided into ten contiguous states. An adjustment window encompasses two states on either side of the nominal bit cell boundary. If a data transition is detected in either of two states later than the cell boundary, the bit cell timing is extended by one full state. On the other hand, if a data transition is detected in either of two states earlier than the nominal bit cell boundary, the bit cell timing is decreased by one full state.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.

Abstract: A data receiver includes first and second mixers mixing an input RF signal and a local oscillator signal and generating first and second quadrature baseband-frequency output signals. A phase shifter shifts a phase of the first baseband-frequency output signal by 90 degrees. A third mixer mixes an output signal from the phase shifter and the first baseband-frequency output signal. A fourth mixer mixes the first and second baseband-frequency output signals. A demodulator performs data demodulation by use of output signals from the third and fourth mixers.

Abstract: The apparatus is for digitizing demodulated frequency shift key modulated data signals, and comprises a differentiating circuit arranged to receive the demodulated data signal, and produce differentiated pulses at an output thereof. First and second comparators are arranged to receive the differentiated pulses, and compare the pulses with respective reference voltages to generate output pulses when pulses above and below the respective reference voltages are detected. The outputs of the comparators are connected to the set and reset inputs respectively of a flip-flop, causing a digitized form of the input demodulated signal to be generated at an output of the flip-flop.

Abstract: A digital FSK trunk dialing converter including M and E lead control is disclosed. The dialing converter further includes an FSK detector which is responsive to consecutive half period intervals of a received FSK signal, and a digital signal-to-noise (S/N) detector or estimator which operates to inhibit or keep the E-wire signal lead deactivated in the presence of noise signals which are received from the communications link in absence of acceptable FSK signals. The FSK detector is comprised of two digital circuits which generate pulses indicative of whether the received FSK signal is greater or less than the FSK center frequency. The pulses are integrated and used to trigger a flip-flop which provides a demodulated digital FSK output indicative of a received high or low FSK analog frequency. An E-wire control signal is generated in the receive logic circuitry in response to the demodulated FSK output.

Abstract: A carrier detection circuit is provided for reliably detecting the presence of a carrier signal. The carrier detection circuit operates on a carrier signal which includes a first symbol exhibiting a first frequency representing a logic 1 and a second symbol exhibiting a second frequency representing a logic 0. A first carrier detect pulse exhibiting a first logic state is generated each time the carrier signal exceeds a predetermined threshold voltage. A plurality of consecutive first carrier detect pulses are checked to determine the logic state of each. A second carrier detect pulse is generated if it is determined that each of the plurality of consecutive first carrier detect pulses exhibit the first logic state.

Abstract: An FSK demodulation circuit which receives as input an FSK modulated reception signal, obtains two quadrature pulse trains, i.e., a first pulse train and a second pulse train, from a phase detection circuit, is provided with at least two sampling means which use the edge of one of the pulse trains and sample the logic of the other pulse train, produces two or more sample outputs at different timings, and determines the logic of the reproduced data from a combination of the logics "1" and "0" of the sample outputs.