Abstract: An output signal pulse width error correction circuit and method wherein errors in a data signal conforming to a communications protocol having a prescribed duty cycle are corrected by monitoring a duty cycle of the data signal, comparing the duty cycle to a duty cycle reference voltage corresponding to the prescribed duty cycle, and adjusting a pulse width of the data signal to conform to the prescribed duty cycle of the protocol. An embodiment is shown that low pass filters the input data signal to introduce greater slope to the input data signal which is then compared to a pulse width control voltage in order to generate an output data signal. The pulse width control voltage is produced by integrating the output data signal to obtain an average value corresponding to the duty cycle of the output data signal and comparing the average value to a duty cycle reference voltage corresponding to the prescribed duty cycle for the communications protocol.

Abstract: A circuit for digitally monitoring a duty cycle of a pulse width modulated signal is provided. The circuit includes a counter portion, a digital filter, and a data storage device. The counter portion is connectable to receive the pulse width modulated signal and is operable to monitor the pulse width modulated signal for a predetermined time period during which a count value is established. The digital filter is connected to receive the count value established by the counter portion and is also connected to receive a stored count value from the storage device, the digital filter being operable to establish a filtered count value based upon the count value and the stored count value input thereto. The storage device is connected to receive the filtered count value established by the digital filter. Multiple pwm signals may be also be monitored by including multiple counters, multiple storage devices, and one or more multiplexers.

Abstract: A method of recovering a finite duration of N symbols of a digitally-modulated signal, wherein a received signal is sampled at a period T.sub.1, generating a batch of K.sub.1 samples, wherein K.sub.1 is chosen to be an integer multiple of the N symbols. The K.sub.1 time-domain samples are input to a discrete fourier transform (20) providing a first batch of K.sub.1 frequency-domain samples. The first batch of K.sub.1 frequency-domain samples are multiplied by a set of frequency-domain K.sub.1 complex gains to provide a second batch of K.sub.1 frequency-domain samples. The second batch of K.sub.1 frequency-domain samples are broken into K.sub.1 /N batches of N samples. The K.sub.1 /N batches are added, generating a single batch of N samples which is input to an inverse fast fourier transform (24) to obtain N time-domain samples.

Abstract: A demodulator for a pulse width modulated signal comprises a counter arranged to count in one direction when the PWM signal is "high" and in the opposite direction when the PWM signal is "low" to arrive at a count representative of a duty cycle. As a result, a value representative of the duty ratio of the PWM signal can be obtained from the up/down counter. In a further embodiment, the up/down counter is clocked by the output of a frequency multiplier, the output of the frequency multiplier having a frequency determined by the pulse width modulated signal frequency multiplied by a predetermined factor. The value of the duty ratio of the PWM signal can then be found regardless of the frequency of the PWM signal.

Abstract: A method of modulating the pulse width of a pulse width signal in response to an analog signal. The steps include changing the analog signal to a digital signal, changing the digital signal to a number of counts, changing the number of counts to a time delay, and then using the logic circuit to combine the time delay with a pulse with modulated input to change the pulse width of an output signal.

Abstract: A data output portion transmits a pulse signal having a pulse width according to a value of transmit data on a predetermined cycle. An H pulse width counter and an L pulse width counter measure a length of a high level period and a length of a low level period in the received pulse signal by using a clock signal having the same frequency as that of the clock signal used in the data output portion. A comparing portion compares the sum of both the measured lengths of the periods with the predetermined cycle, and outputs an error signal in case of a mismatch. In a PWM communication system, it is also possible to detect a signal delay or an error of the clock signal, which is temporarily caused within one cycle.

Abstract: A gain control circuit utilizes a PWM having its transfer function characteristics determined by a ramp and a DC supply voltage. An input signal modulates the PWM and an integrating circuit at the output of the PWM recovers a replica of the input signal. Changing one or more of the transfer function characteristics of the PWM results in a change in the amplitude of the recovered replica of the input signal. Changing the ramp frequency may also be used to effect gain control. An arrangement in a television deflection circuit with raster correction is shown.

Abstract: A circuit for measuring a pulse width of a remote control signal comprises a receiver for receiving a remote control signal exhibiting at least one pulse; an amplifier for shaping and amplifying the received remote control signal to produce a corresponding output signal; a counter having an output which changes from first to second logic states in response to reception of a falling edge of a first pulse of the output signal and simultaneously making a first count of clock pulses that is cleared at the falling edge of each pulse of the output signal; and a microprocessor. When the value of the first count reaches a first predetermined value equivalent to an output signal pulse period and a selected delay, the output changes back to the first logic state. The selected delay is set longer than the period of each pulse so that the first count does not reach the first predetermined value before arrival of another pulse within a waveform of the output signal.

Abstract: The technique of measuring the duty cycle of a digital signal of known repetition rate is disclosed. It makes use of the fact that the probability of the digital signal being at the high level is related to its duty cycle when the signal is sampled at a frequency incoherent with the repetition rate. The apparatus in one embodiment includes a random sampler for sampling the digital signal under measurement, and digital counters which count the total number of samples and the number of samples whose values are at one of the two digital levels.

Abstract: A transceiver device for use with a microcontroller and a symbol encoder decoder device (forming a node in a communications network) for transmitting and receiving variable pulse width modulated (VPWM) analog signals containing symbol messages over a communications bus. The transceiver accepts digital VPWM signals from the symbol encoder decoder device which were generated by the microcontroller and converts the digital signals into VPWM analog signals and then transmits the analog signal over the bus to other nodes. The transceiver also receives VPWM analog signals placed on the bus by other nodes of the network and transfers the signals in digital form to the symbol encoder decoder device which, in turn, communicates the decoded messages to the microcontroller. The transceiver contains a ground translation circuit for transferring transmitted signals to an independent bus ground return before a bus driver circuit sources message signals in the form of pulse currents over the bus.

Abstract: A digital demodulator provides efficient demodulation of frequency modulated, pulse-width modulated, and other temporally modulated signals. Without employing an analog-to-digital converter, modulating signal information is extracted from a modulated signal as numerical information. For frequency demodulation, a high gain stage is applied to an incoming FM signal to produce a corresponding sequence of square waves. The period between zero-crossings of the square waves is accurately measured to within one clock pulse using a high-speed clock and at least one counter to produce a demodulated signal.

Abstract: A digital demodulator provides efficient demodulation of frequency modulated, pulse-width modulated, and other temporally modulated signals. Without employing an analog-to-digital converter, modulating signal information is extracted from a modulated signal as numerical information. For frequency demodulation, a high gain stage is applied to an incoming FM signal to produce a corresponding sequence of square waves. The period between zero-crossings of the square waves is accurately measured to within one clock pulse using a high-speed clock and at least one counter. Period information is then provided to a signal processor that serves to convert the sequence of period measurement values into a demodulated signal with a high signal-to-noise ratio.

Abstract: An improved binary data communication system employs an improved VPSK encoding procedure wherein each input data bit has a bit period of M clock periods, and the data bit polarity changes are phase shift key coded with waveform widths of M/M, M+1/M, and M+2/M bit periods wherein M is an even integer greater than 3. Each of the data bits (except the last one in an encoding cycle) is encoded in an encoding signal which switches back and forth between "1" and "0" polarities and has assigned widths representing whether or not the polarity of the data bit is changed from that of the previous data bit, and whether it is the last (M-1th) polarity change in the encoding cycle. At the receiving end, a complementary procedure is used to decode the encoded signal. For transmission, the encoded signal is filtered for higher order harmonics and integrated in order to provide a sine wave output shifted 90 degrees in phase.

Abstract: A digital demodulator provides efficient demodulation of frequency modulated, pulse-width modulated, and other temporally modulated signals. Without employing an analog-to-digital converter, modulating signal information is extracted from a modulated signal as numerical information. For frequency demodulation, a high gain stage is applied to an incoming FM signal to produce a corresponding sequence of square waves. The period between zero-crossings of the square waves is accurately measured to within one clock pulse using a high-speed clock and at least one counter. Period information is then provided to a numerical processor, wherein it is at least scaled and low-pass filtered to produce a high-quality demodulated signal with a high signal-to-noise ratio.

Abstract: A PWM signal demodulation method measuring the leading edge period of a modulated signal and a time between adjoining leading and trailing edges of the signal and finding the modulation factor in terms of the ratio of the period to the time. Reliable demodulation is ensured even if the carrier frequency of the modulated signal varies significantly. This novel method eliminates one disadvantage of the prior art demodulation method encountered when a varying carrier frequency exceeds the linearity domain of an integrator in its integrating characteristic, causing unreliable demodulation.

Abstract: A skew code generator for digitally quantizing the width of a pulse. A series connected string of identical voltage controllable delay elements is supplied with the pulse, which is sensed as it passes through each of the delay elements. Output signals are developed in response to the leading edge of the pulse and are latched in response to the trailing edge of the pulse. An encoder generates a binary output from the latched output signals, which is indicative of the width of the pulse.