Abstract: A switching transformer includes a primary circuit and a secondary circuit. The primary circuit includes a first input/output (I/O) terminal, a plurality of primary windings, and primary switching circuitry including at least one switch configured to selectively connect the plurality of primary windings in series or in parallel. The secondary circuit includes a second I/O terminal, a plurality of secondary windings, and secondary switching circuitry including at least one switch configured to selectively connect the plurality of secondary windings in series or in parallel.

Abstract: A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.

Abstract: A high-speed high-linearity time-interleaved dynamic operational amplifier circuit includes a first current channel and a second current channel. The first current channel includes a first MOS transistor, a second MOS transistor and a third MOS transistor which are sequentially connected in series between a high level and a ground level. The first MOS transistor and the second MOS transistor have opposite conductivity types. A control end of the first MOS transistor is connected to a control end of the second MOS transistor. The second current channel includes a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor which are sequentially connected in series between the high level and the ground level. The fourth MOS transistor and the fifth MOS transistor have opposite conductivity types. A control end of the fourth MOS transistor is connected to a control end of the fifth MOS transistor.

Abstract: A transceiver that may be implemented in low-voltage differential signaling (LVDS) transmission system or a multipoint LVDS transmission system, and corresponding systems are disclosed herein. The transceiver can filter a common-mode component of a differential input signal input into the transceiver while maintaining a high impedance for a differential-mode component of the differential input signal. The transceiver utilizes teeter-totter circuitry to maintain the high impedance for the differential-mode component of the differential input signal.

Abstract: A capacitance detection circuit, a touch control chip and an electronic device can effectively extract a capacitance change without increasing costs of a circuit. The capacitance detection circuit includes: a CCA circuit, a first input end and a second input end of the CCA circuit are connected to a capacitance to be measured and a cancellation capacitance, respectively, a third input end of the CCA circuit is connected to a coding voltage, and a first output end and a second output end of the CCA circuit output a first current and a second current, respectively, where the cancellation capacitance is smaller than an initial value of the capacitance to be measured; a PGA circuit, two input ends of the PGA circuit are connected to two output ends of the CCA circuit, respectively.

Abstract: Various examples are directed to amplifier circuits and methods for operating amplifier circuits. The amplifier circuit may comprise a first amplifier stage. The first amplifier stage comprises a first amplifier, a first feedback resistance, a second amplifier, a second feedback resistance, and a gain resistance. A first current source may be electrically coupled to provide a first current across the gain resistance in a first direction. A second current source may be electrically coupled to provide a second current across the gain resistance in a second direction opposite to the first direction.

Abstract: An active common mode filter is configured to be positioned between a power supply and a switching converter-device/load for reducing common mode noise. The active common mode filter includes an active capacitor that has a sensing stage including one or more sensing capacitors, an amplifying stage including a common collector amplifier for mitigating an input voltage divider effect coupled to a common emitter amplifier for providing high gain, and an injection stage including one or more injection capacitors. Depending on the required attenuation in different applications, a multistage active common mode filter may be formed with a necessary number of stages, each stage including an active capacitor and an inductor.

Abstract: A transceiver includes a radio-frequency (RF) front-end circuit, a dedicated RF front-end circuit, and a switchable matching circuit. The RF front-end circuit deals with communications of at least a first wireless communication standard. The dedicated RF front-end circuit deals with communications of a second wireless communication standard only. The switchable matching circuit is coupled to the RF front-end circuit, the dedicated RF front-end circuit, and a signal port of a chip. The switchable matching circuit provides impedance matching between the signal port and the RF front-end circuit when the RF front-end circuit is in operation, and provides impedance matching between the signal port and the dedicated RF front-end circuit when the dedicated RF front-end circuit is in operation. The RF front-end circuit, the dedicated RF front-end circuit, and the switchable matching circuit are integrated in the chip.

Abstract: A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

Abstract: In one embodiment, a method for detecting functional state of a microelectromechanical (MEMS) sensor is described. The method includes monitoring an input common-mode feedback (ICMFB) voltage generated by an ICMFB circuit coupled to the MEMS sensor through a plurality of nodes. The method also includes determining, using the monitored ICMFB voltage, whether all of the plurality of nodes of the MEMS sensor are electrically connected to the ICMFB circuit.

Abstract: A measuring current generation circuit coupled to a setting resistor is disclosed. The generation circuit includes a first measuring terminal, a second measuring terminal, a first transconductance amplifier, a second transconductance amplifier and an output circuit. The first transconductance amplifier has a first input terminal and a second input terminal. The first input terminal is coupled to one terminal of the setting resistor. The second input terminal is coupled to another terminal of the setting resistor and coupled to the first measuring terminal. The second transconductance amplifier has a third input terminal and a fourth input terminal. The output circuit is coupled to output terminals of the first transconductance amplifier and the second transconductance amplifier respectively and has a first output terminal and a second output terminal. The first output terminal is coupled to the first input terminal. The second output terminal is coupled to the second measuring terminal.

Abstract: An electronic circuit for a micro-electro-mechanical systems gyroscope is disclosed. The electronic circuit includes a current buffer, a transimpedance amplifier coupled with the current buffer, and a plurality of transistors. An inverting input terminal of the current buffer and a non-inverting input terminal of the current buffer are connected with a plurality of first resistors. The inverting input terminal of the current buffer is connected with a source of one of the plurality of transistors, and the non-inverting input terminal of the current buffer is connected with a source of another one of the plurality of transistors. The plurality of first resistors are connected to a ground. The current buffer is configured to isolate a load in the micro-electro-mechanical systems gyroscope from the transimpedance amplifier.

Abstract: An amplifier circuit comprises a differential input stage and a differential output stage. The differential input stage includes a first differential input transistor pair coupled to a differential input of the amplifier circuit, and a second differential input transistor pair coupled to the differential input and the differential output stage; a degeneration impedance coupled between first transistors of the first and second differential input transistor pairs and second transistors of the first and second differential input transistor pairs; and a feedback circuit coupled to the first and second differential input transistor pairs and the degeneration impedance, wherein output current is provided from the differential input stage to the differential output stage by the feedback circuit and transition current is provided to the output stage by the second differential input transistor pair.

Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.

Abstract: Provided are embodiments for a resistor array. The resistor array includes a plurality of resistor elements, where the plurality of resistor elements includes a redundancy region for a most significant bit of an expected value. The resistor array also includes one or more switches coupled to the plurality of resistor elements, and a first terminal and a second terminal coupled to the plurality of resistor elements. Also provided are embodiments for trimming the resistor array where the resistor array includes a redundancy region for a most significant bit for an expected value.

Abstract: An operational amplifier includes a gain boost circuit. The gain boost circuit includes a first differential gm amplifier of a first stage, and a second differential gm amplifier of a post stage. Phase compensation capacitors are provided between inputs and outputs of a system of the second differential gm amplifier.

Abstract: A circuit that outputs a current which is proportional to an input voltage includes input and output terminals, a comparator, first and second transistors, an inductor, a first resistor, and a differential amplifier. A first input terminal of the comparator is coupled to the input terminal of the circuit, and a second input terminal of the comparator is coupled to an output terminal of the comparator. The first and second transistors are coupled to the output terminal of the comparator. The inductor is coupled to the first and second transistors. The first resistor is coupled between the inductor and the output terminal of the circuit. The differential amplifier includes a first input terminal coupled to a first terminal of the first resistor, a second input terminal coupled to a second terminal to the first resistor, and an output terminal coupled to the first input terminal of the comparator.

Abstract: Systems and methods are provided for differential sensing (DS), difference-differential sensing (DDS), correlated double sampling (CDS), correlated-correlated double sampling (CDS-CDS) and/or programmable capacitor matching to reduce display panel sensing noise. An electronic device may include one or more processors that generate image data according to sensing operations. The one or more processors may reference a sensing pattern as part of sensing operations. Applying test sensing signals based on the sensing pattern may help reduce error associated with sensing operations.

Abstract: An amplifier circuit includes: an amplifier; and a bias circuit that controls an operation point of the amplifier. The amplifier includes: a load resistor; a differential transistor pair electrically coupled to the load resistor; and a tail transistor electrically coupled to the differential transistor pair. The bias circuit includes: a voltage generator circuit that generates a reference voltage corresponding to a sum of a threshold voltage of a transistor in the differential transistor pair and a saturation drain voltage of the tail transistor; and a current generator circuit that generates a reference current that is proportional to a difference between a power supply voltage of the amplifier circuit and the reference voltage by using a reference resistor. The current generator circuit is electrically coupled to the amplifier such that a tail current that flows through the tail transistor is proportional to the reference current.

Abstract: Amplifier configuration for load-line enhancement is described herein. In some implementations, an apparatus includes an amplifier. The amplifier includes at least one plus transistor stack, at least one minus transistor stack, and at least one inductor. The at least one plus transistor stack is coupled to a plus amplifier node and a plus input node. The at least one minus transistor stack is coupled to a minus amplifier node and a minus input node. The at least one inductor is coupled between the plus amplifier node and the minus amplifier node, with the at least one inductor including an inter-inductor node. The amplifier also includes a minus power switch coupled between the minus amplifier node and one or more supply voltages and an inductor power switch coupled between the inter-inductor node and at least one supply voltage.

Abstract: An organic light-emitting display can include a display panel including sensing lines connected to pixels; a current integrator configured to receive current from a pixel through a sensing line connected to a first input terminal, receive a reference voltage through a reference voltage line connected to a second input terminal, and swap a path through which the current applied through the first input terminal flows and a path through which the reference voltage applied through the second input terminal is supplied; a sampling part including a first sample and hold circuit for sampling a first output voltage of the current integrator and a second sample and hold circuit for sampling a second output voltage of the current integrator, subsequent to the first output voltage, which outputs the first and second output voltages sampled by the first and second sample and hold circuits simultaneously through a single output channel.

Abstract: A differential power amplifier having first and second amplifiers with first and second signal output terminals along with bias circuitry in communication with the first and second amplifiers is disclosed. The differential amplifier further includes a first output clamp coupled to the first signal output terminal and a bias control terminal of the bias circuitry, wherein the first output clamp is configured to limit voltage at the first signal output terminal to a first predetermined voltage magnitude and lower bias current to the first amplifier in response to an overvoltage at the first signal output terminal. A second output clamp is coupled to the second signal output terminal and is configured to limit voltage at the second signal output terminal to a second predetermined voltage magnitude.

Abstract: Disclosed is a differential transimpedance amplifier (TIA). In the differential TIA, an input end of the first source follower is coupled to the first output end of a first differential amplification circuit. The output end of the first source follower is coupled to the second input end of a second differential amplification circuit with feedback and a first feedback resistor. The input end of a second source follower is coupled to the second output end of the first differential amplification circuit. The output end of the second source follower is coupled to the first input end of the second differential amplification circuit with feedback and a second feedback resistor. A photo diode and a dummy diode are coupled respectively to two input ends of the first differential amplification circuit.

Abstract: Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers (op-amps) in an instrumentation amplifier are disclosed. An automatic calibrating op-amp system is provided that includes an instrumentation amplifier, which includes a front-end amplifier circuit comprising at least one front-end op-amp and a final-stage amplifier circuit comprising a final-stage op-amp. The op-amp(s) can include auxiliary differential inputs for offset voltage cancellation. The automatic calibrating op-amp system also includes an automatic calibration circuit employing a single controller to generate calibration signals on a calibration output to an auxiliary differential input(s) of an op-amp(s) in the instrumentation amplifier for offset voltage cancellation.

Abstract: An electrical stimulation and bio-potential measurement device is provided. The electrical stimulation and bio-potential measurement device comprises at least one electrode module which comes into contact with the scalp of a user, a current supply unit, connected to the at least one electrode module, for supplying a current to the at least one electrode module so that the at least one electrode module can apply electrical stimulation to the user, and a signal processing unit, connected to the at least one electrode module, for processing bio-potential signals detected by the at least one electrode module, wherein the current supply unit comprises at least one switch which is arranged between the at least one electrode module and a voltage source for supplying the current.

Abstract: Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers (op-amps) in an instrumentation amplifier are disclosed. An automatic calibrating op-amp system is provided that includes an instrumentation amplifier, which includes a front-end amplifier circuit comprising at least one front-end op-amp and a final-stage amplifier circuit comprising a final-stage op-amp. The op-amp(s) can include auxiliary differential inputs for offset voltage cancellation. The automatic calibrating op-amp system also includes an automatic calibration circuit employing a single controller to generate calibration signals on a calibration output to an auxiliary differential input(s) of an op-amp(s) in the instrumentation amplifier for offset voltage cancellation.

Abstract: An apparatus is provided which comprises: a low-side switch; at least two high-side switches coupled to the low-side switch; a supply boost circuitry coupled to one of the at least two high-side switches; and a high-side switch selection circuit which is operable to enable one of the at least two high-side switches according to a relative difference between a signal and a threshold.

Abstract: A sensor device includes at least two transducers, a sensor signal processing circuit, and a transducer to sensor signal processing circuit electrical connections, each connecting a respective one of the transducers to the sensor signal processing circuit. The device also includes a differential amplifier connected with two bond wires, the bond wires connected to the differential inputs of the differential amplifier and the amplifier output connected to the sensor signal processing circuit.

Abstract: A driver circuit including a first op-amp, a second op-amp, and a power switching circuit is provided. The first op-amp includes a first input stage circuit for generating a first amplified signal and a first output stage circuit. The second op-amp includes a second input stage circuit for generating a second amplified signal and a second output stage circuit. The power switching circuit includes a first output terminal for outputting one of the first amplified signal and the second amplified signal and a second output terminal for outputting the other of the first amplified signal and the second amplified signal. The power switching circuit is configured to switch a first power supply for both the first input stage circuit and the second input stage circuit between a first supply voltage and a second supply voltage in response to the control signal.

Abstract: A low dropout regulator provided includes: an impedance unit; a differential amplifier being electrically connected to the impedance unit; a current mirror unit being electrically connected to the differential amplifier; and an adaptive bias unit being electrically connected to the differential amplifier and the current mirror unit. The impedance unit is electrically connected to a negative feedback route of the differential amplifier to make a gain of the negative feedback route greater than a gain of a positive feedback route of the differential amplifier.

Abstract: A first circuit unit of an audio amplifier includes a first emitter follower connected to an pre stage input terminal, a second emitter follower connected to an pre stage input terminal, a main transistor connected to an output path of the first emitter follower and an output path of the second emitter follower, a first resistor and a second resistor, which are series-connected between the output path of the first emitter follower and a DC voltage source, and a zener diode connected to a series-connection point between the first resistor and the second resistor. A second circuit unit has a circuit configuration that is complementary to the first circuit unit. A path leading to a collector of each transistor configuring the first and second emitter followers in one of the circuit units is connected to the series-connection point in the other circuit unit.

Abstract: A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.

Abstract: A differential signal offset adjustment circuit may include a first circuit for receiving a first one of a differential input signal and generating a first one of a differential output signal with positive offset based on a differential offset signal. The circuit may further include a second circuit for receiving a second one of a differential input signal and generating a second one of a differential output signal with a negative offset based on the differential offset signal.

Abstract: A programmable gain amplifier includes an active load module, a first differential pair, a second differential pair and a power source module. The first and second differential pairs are electrically connected to the active load module. The power source module is electrically connected to the first current source end of the first differential pair and the second current source end of the second differential pair. The power source module supplies a first current to the first differential pair through the first current source end. The power source module supplies a second current to the second differential pair through the second current source end. The power source module adjusts the potential of the first current, the potential of the second current, or both.

Abstract: An active filter device and a circuit arrangement comprising an active filter device are disclosed. In an embodiment the active filter device includes sensor terminals for applying a sensor signal depending on a sensed noise signal, an output terminal for providing a correction signal that is suitable for reducing the noise signal, a signal source adapted for generating a correction signal and a high-pass filter coupled between the sensor terminals and the signal source, wherein the correction signal is generated with a dependence on a high-pass filtered sensor signal.

Abstract: An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.

Abstract: Embodiments of an amplifier for a constant-current light-emitting diode (LED) driver circuit and a constant-current LED driver integrated circuit (IC) device having the amplifier are described. In one embodiment, an amplifier includes a folded cascode input stage including chopping switch circuits configured to perform frequency chopping to reduce an input offset of the amplifier and a rail-to-rail output stage connected to the folded cascode input stage. The rail-to-rail output stage includes slew rate enhancement circuits.

Abstract: An isolator system has an isolator that generates differential isolator signals and a receiver that generates digital data representative of signals received from the isolator. The system also may include an RC filter coupled between the isolator and the receiver. During operation, the filter may distribute transient signals across various circuit paths in the isolator, only some of which are coupled to the receiver inputs. Over time, the filter may attenuate transient contributions at the receiver inputs. In this manner, the filter may limit effects of these common mode transients.

Abstract: A tunable peaking amplifier circuit including: an input node, an output node, and a feedback node; a first input amplifier having an input connected to the input node and an output connected to the feedback node; a second input amplifier having an input connected to the input node; a coupling capacitor connected between an output of the second input amplifier and the feedback node; an amplifier having an input connected to the feedback node and an output connected to the output node; a feedback circuit including: a base feedback amplifier having an input connected to the output node and an output connected to the feedback node; and a tunable feedback amplifier having an input connected to the output node and an output connected to the feedback node; and a tuning circuit for varying a transconductance of the feedback circuit to adjust an operational frequency of the peaking amplifier circuit.

Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.

Abstract: The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

Abstract: Bias current is supplied to a first differential pair and a second differential pair from a first transistor being a single current source. Bias current is supplied to a third differential pair and a fourth differential pair from a second transistor being a single current source. An input voltage is at a power supply potential, and an input voltage is at a ground potential. When the second differential pair and the third differential pair are turned OFF, the bias current supplied from the first transistor flows to an output stage via the first differential pair, and the bias current supplied from the second transistor flows to the output stage via the fourth differential pair. Therefore, when the second differential pair and the third differential pair are turned OFF, a circuit current is kept constant, and a fluctuation in a frequency characteristic can be restrained.

Abstract: A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.

Abstract: In one example, a circuit includes a voltage source, a pass module, a differential amplifier module, and a control module. The pass module is configured to electronically couple, using a channel having a resistance, the voltage source and a load and to modify the resistance of the channel based on a control signal. The differential amplifier module is configured to generate a differential signal based on a comparison of a voltage reference and a representation of a voltage at the load. The control signal is based on the differential signal. The control module is configured to generate the representation of the voltage at the load according to a transfer function. The transfer function includes a zero positioned substantially at a crossover frequency of the transfer function.

Abstract: A low noise amplifier (LNA) includes a first transistor and a second transistor. A source of the second transistor is connected to a drain of the first transistor. The LNA further includes a feedback transformer. A gate of the first transistor is connected to a primary winding of the feedback transformer and a gate of the second transistor is connected to a secondary winding of the feedback transformer.

Abstract: An active high gain filter includes high value resistances in feedback implemented using a negative resistance circuit configuration. The high value resistance is implemented using two or smaller resistances connected in the negative resistance circuit configuration. This implementation permits integration of the filter circuit using less occupied area while still providing an accurate transfer function response.

Abstract: Techniques and mechanisms for providing signal communication with a configurable transceiver circuit. In an embodiment, an integrated circuit comprises transceiver circuitry including an output stage and current mirror circuitry. The output stage is coupled to receive a differential signal pair and to provide at least one output signal based on the differential signal pair. In another embodiment, configuration logic is operable to select between a first mode and a second mode of the transceiver circuit. The first mode includes the current mirror circuitry being disabled from providing a current signal to the output stage, and a first circuit path being closed to provide voltage to the output stage. The second mode includes the first circuit path being open and the current mirror circuitry being enabled to provide a current signal to the output stage.

Abstract: Disclosed herein are a method, circuitry and an integrated circuit chip for use in signal processing. The integrated circuit chip comprises an operational amplifier, a reference amplifier, and a control unit. The control unit is coupled to the reference amplifier and to the operational amplifier. The control unit is configured to control the reference amplifier based on a signal received from the reference amplifier.

Abstract: A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.

Abstract: A circuit for blocking undesired input direct current of AC-coupled broadband circuits. The circuit includes a capacitor coupled to an input port and a common node. The input port receives a RF input signal. Additionally, the circuit includes a current source supplying a DC current to the common node leading a bias current to an output port. Further, the circuit includes a variable voltage source through an internal load and a close loop with an application circuit having an input load coupled to the output port to determine various bias voltages to control the bias current at the output port in association with a RF output signal that is substantially free of any input direct current originated from the RF input signal and is associated with an inherent low cut-off frequency independent of the various bias voltages.