Abstract: A method of fabricating a solid state power amplifier (SSPA) having variable output power is provided. The method includes coupling a first transistor device to a second transistor device and biasing a drain input of each of the first and second transistor device. Further, the method includes biasing a gate input of each of the first and second transistor device varying a drain to source current of each of the first and second transistor device to enable the SSPA to maintain high power added efficiency (PAE) and consistent linearity over a range of output power levels.

Abstract: An improved regulator circuit, temperature compensation bias circuit, and amplifier circuit are disclosed.

Abstract: To provide a bias circuit for gain control that can reduce gain variation at low-power output, facilitate setting of output power, and is unlikely to be affected by variation in element values and variations among products. Use in an HPA having three bias circuits serially-connected is assumed. Current of the third bias circuit is varied with a square-law characteristic. The square-law characteristic is amplified by a buffer amplifier including a linear amplifier and a peripheral circuit thereof. Output current of the third bias circuit varies depending on a current drivability coefficient of the diode-connected FET branched from the connection point between a constant current source and the linear amplifier. The output current of the third bias circuit is controlled by providing a circuit that draws a certain amount of current from the current flowing in the FET.

Abstract: A power amplifier comprises: an amplifying transistor for amplifying an input signal; a reference voltage generating circuit which generates a reference voltage; a bias circuit generating a bias voltage based on the reference voltage and supplying the bias voltage to the amplifying transistor; and a booster elevating an enable voltage input from outside and outputting the enable voltage. The reference voltage generating circuit is turned ON/OFF in correspondence with an output voltage of the booster. The booster includes: an enable terminal to which the enable voltage is applied; a power source terminal connected to a power source; a transistor having a control electrode connected to the enable terminal, a first electrode connected to the power source terminal, and a second electrode that is grounded; and a FET resistor connected between the first electrode of the transistor and the power source terminal. A gate electrode of the FET resistor is open.

Abstract: An apparatus for providing a linearity information associated with an amplifier includes an operating state determinator and an evaluator. The operating state determinator is configured to obtain information describing a gain of the amplifier for at least one bias condition of the amplifier. The evaluator is configured to obtain the linearity information based on both the information describing the gain of the amplifier and information about the at least one bias condition of the amplifier using a gain-bias characteristic of the amplifier. A bias circuit including the apparatus for providing the linearity information is also disclosed.

Abstract: A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The amplitude loop may include a variable gain amplifier adjusting the amplitude of the input signal. The amplitude loop can include a compression control block which may be configured either to adjust the gain in the variable gain amplifier or the voltage from the power supply based upon the operating level of the other, in addition to being based upon the amplitude correction signal, thus providing a way of maintaining the depth beyond the PA's compression point and allowing a control of the efficiency of the RF power amplifier.

Abstract: Power amplifier (PA) systems are typically comprised of a signal path integrated circuit (IC) and a power control IC. Advanced CMOS technologies may allow smart integration of such ICs into a single IC and provide an opportunity to improve performance and cost. Specifically, the radio frequency (RF) signal path is designed to enable local biasing of the gain stages that comprise the RF signal path. By using current-mode biasing instead of the prior art voltage-mode biasing significant area reduction is achieved as well as better isolation between the stages which reduces noise, and improves stability.

Abstract: The present invention provides a feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. The invention provides a transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. The invention provides additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions.

Abstract: Systems and methods are described for detecting and correcting saturation in a power amplification circuit. An exemplary circuit comprises a power amplifier that provides an amplified output signal based upon an input signal and a gain control signal; a power detector that provides a detector signal indicative of the amplified signal magnitude; an error amplifier that generates the gain control signal based upon a setpoint signal and the detector signal; and a saturation detector that provides a saturation detection signal indicating whether gain control signal exceeds a reference signal. In another embodiment the circuit comprises an offset generator that provides a correction to the setpoint signal in response to the saturation detection signal indicating that the gain control signal exceeds the reference signal. In still another embodiment the circuit includes an offset cutoff circuit that freezes the correction to the setpoint signal in response to the correction exceeding a threshold.

Abstract: A high-frequency power amplifier which can reduce a variation of power gain due to the dependence on gate length of a power amplification field effect transistor is provided. The high-frequency power amplifier comprises, over a semiconductor chip, a bias control circuit, a bias transistor and an amplification transistor which are coupled so as to configure a current mirror circuit, and a gate length monitor circuit comprising a replicating transistor. The amplification transistor amplifies an RF signal and a bias current of the bias control circuit is supplied to the bias transistor. The transistors are fabricated by the same semiconductor manufacturing process, and have the same variation of gate length. The gate length monitor circuit generates a detection voltage depending on the gate length. According to the detection voltage, the bias control circuit controls the bias current, thereby compensating the gate length dependence of transconductance of the amplification transistor.

Abstract: Disclosed is a CMOS power amplifier. A temperature compensation circuit of a CMOS power amplifier may include: a bias circuit unit supplying a gate bias voltage to a power amplification circuit part; a bias detection unit determining a class type of the power amplification circuit part according to the gate bias voltage; a temperature detection unit detecting a temperature-proportional voltage in proportion to ambient temperature; a temperature compensation control unit generating a compensation control value according to the temperature-proportion voltage in the class type determined by the bias detection unit; and a conversion unit converting the compensation control value of the temperature compensation control unit into a linear bias control value and providing the linear bias control value to the bias circuit unit, wherein the bias circuit unit compensates the gate bias voltage according to the linear bias control value of the conversion unit.

Abstract: Systems, devices and techniques relating to power amplifier protection include, in some implementations, a circuit including: attenuation circuitry to couple with an output of detection circuitry that provides a protection signal and to couple with an input of power amplifier circuitry; turn off circuitry to couple with the power amplifier circuitry, the turn off circuitry configured to turn off the power amplifier circuitry responsive to the protection signal; and the attenuation circuitry configured to reduce a gain of the power amplifier circuitry responsive to the protection signal, the attenuation circuitry comprising a delay stage configured to continue attenuating an RF input signal of the power amplifier circuitry until after the power amplifier circuitry turns on.

Abstract: The present invention provides a method and apparatus for compensating the output of a transmitter stage (50) of a communications system. A communications apparatus has a transmitter stage (50) providing a variable control voltage which varies the power of the transmitter stage. The impedance at the output of the transmitter stage. (50) varies as the power varies. A control generation circuit compares a reference voltage to the variable control voltage to produce a control signal (VvswrC). A compensated load (40) coupled to the output of the transmitter stage (50) has active component (s) whose' impedance varies in response to the control signal (VvsweC) so as to compensate for the impedance at the output of the transmitter stage (50).

Abstract: A variable gain amplifier may include a master amplifier that may be configured to generate a first current and a diode coupled with the master amplifier so that the first current passes through the diode which, when the first current is passing through the diode, generates a diode voltage signal. According to embodiments, an error amplifier may include a first input configured to receive a gain control voltage signal and a second input configured to receive the diode voltage signal. The output of the error amplifier may provide a feedback signal. The amplifier may include a circuit configured to generate at least one voltage control signal based on the feedback signal and a slave amplifier configured to adjust a gain amount based on the at least one voltage control signal.

Abstract: A variable gain amplifier includes a source-grounded transistor, to a gate of which an input signal is supplied; a plurality of first cascode transistors, sources of which are connected to a drain of the source-grounded transistor; a second cascode transistor, a source of which is connected to the drain of the source-grounded transistor; a first gate-grounded transistor, a source of which is connected to drains of the plurality of first cascode transistors, and to a gate of which a constant voltage is applied; and an output load connected to a drain of the first gate-grounded transistor wherein the plurality of first cascode transistors and the second cascade transistor are put into a conducting state or a non-conducting state such that a drain current of the source-grounded transistor is constant and moreover a fraction of the drain current supplied to the plurality of first cascade transistors changes.

Abstract: An amplifying device includes a selecting section that selects one of a first power source potential and a second power source potential which are different from each other, a potential generating circuit that generates a third power source potential from the power source potential selected by the selecting section, an amplifier that operates with supply of the first power source potential and the third power source potential, and a controlling circuit that variably controls a target to be selected by the selecting section in accordance with at least one of an amplitude of a signal on an input side of the amplifier, an amplitude of a signal on an output side of the amplifier, and the third power source potential.

Abstract: A transceiver includes a harmonic termination circuit that receives a tunable harmonic voltage from a power amplifier control. The harmonic termination circuit includes a variable capacitor that is capable of adjusting its capacitance in response to the tunable harmonic termination voltage to achieve at least two modes of operation. The at least two modes of operation may be EDGE mode and GSM mode. In this embodiment, the harmonic termination circuit allows for linearity specifications of EDGE to be met, while not degrading the efficiency of the transceiver when operating in GSM mode. In one embodiment, the harmonic termination circuit further includes an inductive element in series with the variable capacitor.

Abstract: The present invention relates to audio amplifier and a method for protecting the audio amplifier. The audio amplifier includes a pre-amp circuit, an output stage power amplifier, a temperature detector and a gain adjusting circuit. The pre-amp circuit receives an audio signal for amplifying the audio signal to generate an amplified audio signal. The output stage power amplifier receives the amplified audio signal to drive a load. The temperature detector is used for detecting a temperature of the output stage power amplifier to output a temperature signal. The gain adjusting circuit adjusts amplitude of the amplified audio signal of the pre-amp circuit according to the temperature signal.

Abstract: A power amplifier circuit including a first transistor, a second transistor, and a power control circuit. The first transistor includes a first input and a first output. The second transistor includes a second input coupled in series with the first output of the first transistor. The input circuit is coupled to the first input of the first transistor. The power control circuit is coupled to the second input of the second transistor. The control circuit includes a time delay circuit and a variable source.

Abstract: An emitter-follower bias circuit supplying a bias voltage to the base of an amplification transistor includes: a depletion mode FET boosting a reference voltage; and an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET.

Abstract: A step gain amplifier has an amplifier with an input and an output, and a bias circuit connected to the input and to a bias node. A passive feedback circuit using only passive elements connects the output to the input. A control circuit is connected to the bias circuit at the bias node.

Abstract: A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element.

Abstract: A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal.

Abstract: Systems and methods for providing a self-mixing adaptive bias circuit that may include a mixer, low-pass filter or a phase shifter, and a bias feeding block. The self-mixing adaptive bias circuit may generate an adaptive bias signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit increases the bias voltage or bias current such that the amplifier will save current consumption at low power operation levels and obtain better linearity at high power operation levels compared to conventional biasing techniques. Moreover, the adaptive bias output signal can be used to cancel the third-order intermodulation terms (IM3) to further enhance the linearity as a secondary effect.

Abstract: A multiple electronic device power supply, battery charger, and USB docking system has a plurality of power ports for charging/powering electronic devices and a plurality of USB ports for coupling peripheral devices to a computer or large electronic device. Electronic devices which may be charged using the present invention can require current from less than 500 mA to approximately 6 A. Voltage setting resistors in specialized adapters serve to set the voltage needed for individual devices in order to manage current and voltage distribution throughout the present invention, particularly when large and mid-sized electronic devices are connected to the present multiple device charger and docking system. Default settings set the voltage output at 24 volts if not otherwise directed.

Abstract: The RF power amplifier circuit including multiple amplification stages has a previous-stage amplifier, a next-stage amplifier and a controller. The previous-stage amplifier responds to an RF transmission input signal. The next-stage amplifier responds to an amplification signal output by the previous-stage amplifier. In response to an output-power-control voltage, the controller controls the former- and next-stage amplifiers in quiescent current and gain. In response to the output-power-control voltage, the quiescent current and gain of the previous-stage amplifier are continuously changed according to a first continuous function, whereas those of the next-stage amplifier are continuously changed according to a second continuous function. The second continuous function is higher than the first continuous function by at least one in degree. The RF power amplifier circuit brings about the effect that the drop of the power added efficiency in low and middle power modes is relieved.

Abstract: A radio frequency amplifier system is disclosed in which the amplifier bias supply and power supply voltages are instantaneously modulated with signals derived from the envelope voltage of the input signal. Separate non-linear mapping functions are used to derive the supply and bias voltages. The two mapping functions are optimised jointly to achieve particular system performance goals, such as optimum efficiency, constant gain, constant phase, or minimum spectral spreading. An optimisation of particular interest is that which achieves best RF amplifier power added efficiency subject to achieving constant amplifier gain. In this way the need for pre-distortion linearization may be reduced or eliminated.

Abstract: Aspects of a method and system for precise current matching in deep sub-micron technology may include adjusting a current mirror to compensate for MOSFET gate leakage currents by using feedback circuits. The feedback circuits may be implemented from active components to create active feedback circuits. If the reference current to be mirrored is noisy, a smoothing effect may be achieved by introducing a low-pass filter coupled to the current mirror design. The active feedback may comprise amplifiers, which may comprise one or more amplifier stages. The amplifier may amplify either a bias voltage error or a bias current error. Furthermore, a transimpedance amplifier may be utilized in the feedback loop. The output bias current of the current mirror may be stabilized dynamically during adjusting. Multiple current sources may be utilized in the current mirrors.

Abstract: Aspects of a method and system for polar modulating QAM signals with discontinuous phase may include amplifying a signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain. The setting of the coarse amplitude gain and/or said amplitude offset gain may be adjusted dynamically and/or adaptively. The signal may be generated by phase-modulation of a radio-frequency carrier. The combined gain of the plurality of amplifiers may be controlled based on a desired amplitude modulation. The plurality of amplifiers may be integrated within an integrated circuit (IC) or chip.

Abstract: An RF power amplifier has a final-stage amplifier stage which generates an RF transmit output signal, a signal detector which detects an RF transmit output level, a first detector, a second detector and a control circuit. The final-stage amplifier stage includes a transistor and a load element and performs saturation type nonlinear amplification and non-saturation type linear amplification. The first detector and the control circuit maintain the RF transmit output signal approximately constant with respect to a variation in load at an antenna at the saturation type nonlinear amplification. The second detector and the control circuit reduce an increase in the output voltage of the final stage transistor with respect to an overload state of the antenna at the non-saturation type linear amplification.

Abstract: Disclosed are CMOS-based devices for switching radio frequency (RF) signals and methods for biasing such devices. In certain RF devices such as mobile phones, providing different amplification modes can yield performance advantages. For example, a capability to transmit at low and high power modes typically results in an extended battery life, since the high power mode can be activated only when needed. Switching between such amplification modes can be facilitated by one or more switches formed in an integrated circuit and configured to route RF signal to different amplification paths. In certain embodiments, such RF switches can be formed as CMOS devices, and can be based on triple-well structures. In certain embodiments, an isolated well of such a triple-well structure can be provided with different bias voltages for on and off states of the switch to yield desired performance features during switching of amplification modes.

Abstract: Disclosed are high linearity CMOS-based devices capable of passing large signal and quiescent power amplifier current for switching radio frequency (RF) signals, and methods for biasing such devices. In certain RF devices such as mobile phones, providing different amplification modes can yield performance advantages. For example, a capability to transmit at low and high power modes typically results in an extended battery life, since the high power mode can be activated only when needed. Switching between such amplification modes can be facilitated by one or more switches formed in an integrated circuit and configured to route RF signal to different amplification paths. In certain embodiments, such RF switches can be formed as CMOS devices, and can be based on triple-well structures.

Abstract: There is provided a variable gain circuit system which is inductorless and capable of achieving a high gain and a wide band by elements for achieving variable gain to prevent decreasing a gain or deteriorating the band. The variable gain circuit includes: transistors; a resistor connected as a load of each transistor; a voltage source applying a bias voltage to each gate of the transistors; a switch selectively connecting the voltage source or a ground potential to each gate of the transistors in accordance with gain setting; and a current source connected to a common input. A drain of each transistor is connected to an input of a circuit in a subsequent stage.

Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.

Abstract: An adaptive bias circuit which provides a more sensitive adaptive bias current with respect to power level is used for biasing an electronic circuit. The adaptive bias circuit has a first transistor coupled to a power supply, a voltage bias circuit coupled to the first transistor and the power supply biasing the first transistor, and a first power coupling module coupled to the first transistor and the electronic circuit for coupling a portion of input signal power to the first transistor. A second transistor is coupled to the first transistor and the power supply to increase the current gain of the adaptive bias circuit, and a second current coupling module is coupled to the second transistor and the electronic circuit to provide adaptive bias current to the electronic circuit.

Abstract: CMOS power amplifiers (PAs) are disclosed having one or more integrated one-time programming (OTP) memories that are utilized to control at least in part operation of the CMOS PAs. The integrated OTP memories within the CMOS power amplifiers (PAs) allow adjustments, such as one-time factory trimming, of CMOS PA integrated circuits to optimize or improve performance. With this capability, for example, the tuning and biasing of stages within a multi-stage amplifier within a CMOS PA can be measured during factory test and adjusted by setting one or more bits in the OTP memories, as desired. Further, the operation of other circuitry within the PA can also be controlled at least in part with parameter settings stored in the OTP memories.

Abstract: Circuits and methods for compensating for an input-dependent gain error in a buffer and/or amplifier circuit, including applying a dynamic current to the input transistor. Circuits generally include a dynamic current supply coupled to a terminal of the input transistor, the dynamic current supply providing a compensating current. The compensating current can have a magnitude equal to the output impedance of the input transistor times a magnitude of the output voltage. The compensating current can be provided via a current mirror, or directly to a terminal of the input transistor. Methods generally include regulating variations in the current through the input transistor by sinking or sourcing a static current and a dynamic current at a terminal of the input transistor. The dynamic current can be regulated in response to a variation in the input signal.

Abstract: A transmitting power level controller of a communication system includes a radio-frequency unit for generating a communication signal and a power amplifier for amplifying the communication signal to generate a transmitting signal. The transmitting power level controller has a temperature sensor, a power detector, and an automatic level controller. The temperature sensor senses temperature of at least one of the RF unit and the PA to generate a detected temperature signal. The power detector detects a transmitting power of the transmitting signal to generate a detected power signal. The automatic level controller is coupled to the temperature sensor and the power detector. The power detector adjusts the transmitting power of the transmit signal according to the detected power signal when a maximal transmitting power is in a predetermined range, and adjusts the transmitting power according to the detected temperature signal otherwise.

Abstract: A power amplifier system with power control function provides accurate and efficient power control by controlling a bias voltage and a bias current of the power amplifier at the same time.

Abstract: An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified output signal. The output stage (330) includes a gain stage and a bias circuit. The gain stage has an input forming the input of the output stage, an output for providing the amplified output signal, and a first bias terminal. The bias circuit has a first output terminal coupled to the first bias terminal of the gain stage. During a turn-on period the bias circuit gradually ramps the first bias terminal from a first initial voltage to a first bias voltage.

Abstract: A circuit and method are provided for reducing dynamic EVM of a power amplifier (PA) used for RF communication. A temperature dependent boost bias signal is applied to the bias input port of amplifier circuitry of the PA in dependence upon a temperature of the amplifier circuitry to compensate for transience in the gain or phase response of the PA while components of the PA is differentially warming-up, advantageously taking into account an actual temperature of the amplifier circuitry.

Abstract: An electronic component for high frequency power amplification realizes an improvement in switching spectrum characteristics. The gain of an amplifying NMOS transistor is controlled by a bias voltage on which a bias control voltage is reflected. Further, a threshold voltage compensator compensates for a variation in threshold voltage with variations in the manufacture of the amplifying NMOS transistor. The threshold voltage compensator includes an NMOS transistor formed in the same process specification as the amplifying NMOS transistor and converts a variation in current flowing through the NMOS transistor depending on the variation in the threshold voltage of the amplifying NMOS transistor to its corresponding voltage by a resistor to compensate for the bias voltage. It is thus possible to reduce variations in so-called precharge level brought to fixed output power in a region (0 dBm or less, for example) low in output power.

Abstract: Provided are a detector circuit which has a simple circuit configuration, is capable of indicating an accurate power according to a load fluctuation of a radio frequency power amplifier or a difference in a modulation mode, and can be easily incorporated in the radio frequency power amplifier, and a wireless communication system using the detector circuit. The detector circuit 10 includes a detecting resistor 11 for detecting a part of a current flowing from a bias circuit 6, and a current-voltage conversion circuit 12 for converting a current obtained through the detecting resistor 11 into a voltage.

Abstract: A bias control signal generation unit detects ON and OFF of a transmission signal input to an amplifier and having a property of a burst according to burst information. The bias control signal generation unit controls a bias voltage to be applied to an amplifier such that an idle current flowing through the amplifier can be flowing in a larger amount in a transmission OFF period, and can return to a normal level in a transmission ON period.

Abstract: A system and method are provided for reducing dynamic EVM of an integrated circuit power amplifier (PA) used for RF communication. In a multistage PA, the largest amplification stage is biased with a high amplitude current pulse upon receipt of a Tx enable, before receipt of the RF signal data burst. The high amplitude current pulse causes a large portion of the total ICQ budget of the multistage PA to pass through the largest amplification stage causing the entire integrated circuit to rapidly approach steady-state operating conditions. A smoothing bias current is applied to the largest amplification stage after the pulse decays to compensate for transient bias current levels while standard bias circuitry is still approaching steady-state temperature.

Abstract: An amplifying circuit includes: an amplifying unit which amplifies an input signal and applies the amplified signal to a designated load; a current detection unit which detects a load current that flows into the designated load upon application of the amplified signal; an estimating unit which calculates, based on the voltage level of the input signal, an estimated value of the load current to be supplied to the load; and an adjusting unit which adjusts an input bias, to be applied to the amplifying unit, in such a manner so as to reduce a difference value representing a difference between the estimated value and the load current detected by the current detection unit.

Abstract: The present invention relates to a synchronization circuit for an integrated amplifier provided with a bandwidth control in accordance to a bandwidth control signal, wherein said synchronization circuit comprises a control terminal for a control signal and rank selector means connected to an internal control signal and being configured to emboss said internal control signal to said control terminal, if said internal control signal has a higher rank in accordance to a predetermined ranking criteria in comparison to said control signal. Further, the present invention relates to a respective synchronization method for continuously communicating and synchronizing of a common control signal for multiple circuits. One preferred application of the invention is in temperature protection by a synchronized bandwidth control for multiple class-AB amplifiers by means of only one additional terminal pin per amplifier.

Abstract: The present invention relates to a bias control circuit and method for supplying a bias signal to at least one stage of an amplifier circuit, wherein a dual bias control is provided by generating a bias current and additionally using this bias current to derive a control signal for limiting a supply voltage of the at least one amplifier stage in response to the control signal. Thereby, a compression of the output signal of the amplifier stage, which results from the voltage limitation, can be realized in addition to the base current steering. This leads to a decrease in small signal gain and thus reduced output noise.

Abstract: Low noise amplifier circuit. The low noise amplifier circuit includes an amplifier that amplifies an input to provide an output. The amplifier is coupled to an input terminal. The circuit also includes a device in a cascode connection with the amplifier. The circuit further includes a tuning circuit coupled to the device to phase shift the output. Further, the circuit includes a feedback circuit that is responsive to a phase-shifted output to enhance gain of the amplifier. The feedback circuit is coupled to the tuning circuit and the amplifier.

Abstract: A power amplifier and bias circuit includes a combination circuit in which a voltage drive bias circuit and a current drive bias circuit are connected in a parallel relationship with each other. The power amplifier bias circuit also includes an idle current control circuit which uses the collector voltage of amplifier transistors. When the collector voltage of the amplifier transistors is lower than the threshold voltage of a first transistor (approximately 1.3 V), the first transistor is turned off. At that time, since the reference voltage (2.4-2.5 V) is higher than the voltage for turning on both a second transistor and a diode (namely, approximately 1.3 V plus 0.7 V), a current flows and the first transistor turns on. As a result, a current is drawn from the bases of the amplifier transistors to GND through two resistances, so that the idle currents of the amplifier transistors decrease.