Abstract: A differential amplifier circuit receives a pair of input signals to develop an output signal. First and second MOS transistors have commonly-connected gates and sources. A third MOS transistor has a drain connected to the commonly-connected gates, and a source connected to the first MOS transistor's drain. The third MOS transistor's gate is connected to a constant voltage source. A constant current source is connected to the third MOS transistor's drain. A first terminal, connected to the first MOS transistor's drain and to the third MOS transistor's source, provides an input current. A second terminal, connected to the first and second MOS transistors' commonly-connected sources, provides a common reference. A third terminal, connected to the second MOS transistor's drain, provides an output current.

Abstract: An amplifier comprises an input terminal that inputs an AC voltage signal; an amplifying unit having a transistor for amplifying the input AC voltage signal; a current detecting unit connected internally of said amplifying unit; and a control-current source controlled by said current detecting unit that drives an input stage of the transistor.

Abstract: An RF mixer provides extended dynamic range with reduced noise by utilizing degeneration inductors in the RF input section of a doubly balanced mixer. Degeneration inductors are also utilized in a mixer having a class AB input section. A current mirror in the class AB input section is also inductively degenerated for further noise reduction. The input section is biased by an all-NPN bandgap reference cell which is tightly integrated into the input section so as to reduce the power supply voltage required for the reference cell. The mixer can be optimized for wide input voltage ranges or low distortion.

Abstract: The variable transconductance circuit includes: a voltage-current conversion circuit for outputting a current signal linear with an input voltage signal; first and second MOS transistors for converting the current signal received to a square-root compressed voltage signal; and third and fourth MOS transistors for converting the square-root compressed voltage signal to a linear current signal. A bias current at the first and second MOS transistors and a bias current at the third and fourth MOS transistors are varied to control transconductance.

Abstract: A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.

Abstract: There is provided an amplifier circuit includes: an amplifying transistor; a first transistor having a DC current amplification factor generally equal to the DC current amplification factor of the amplifying transistor and constituting a current mirror circuit in conjunction with the amplifying transistor; and a current source circuit being operable to supply a current to the first transistor and including a second transistor having opposite conductivity type to the conductivity type of the first transistor. The second transistor is operated in a saturation region at a power supply voltage lower than an operating voltage range so that the DC current amplification factor of the amplifying transistor can be detected.

Abstract: A power amplifier bias circuit having a controllable current profile includes a first transistor device configured as a switch, and configured to receive a non-regulated system voltage, and a plurality of resistors configured to provide a current and configured to determine an amount of a bias current that flows through a second transistor device, where the second transistor device is part of a current mirror comprising a third transistor device and the amount of bias current flowing through the second transistor device determines a power output of the third transistor device.

Abstract: A high gain stacked cascade amplifier includes a first amplifying element, a second amplifying element, a current mirror bias element, and a dynamic bias adjustment element. The first and second amplifying elements are coupled in series to form the high gain stacked cascade amplifier configuration. The current mirror bias element provides a bias to the first and second amplifying elements. The dynamic bias adjustment element is coupled to the second amplifying element. The dynamic bias adjustment element is configured to increase a gain compression point of a composite filter, formed by the first and second amplifying elements, in response to a determination that an input signal causes gain compression in the first amplifying element.

Abstract: A circuit includes a first transistor in a common-collector configuration and a heterojunction bipolar transistor (HBT) in a common-emitter configuration. The first transistor has a base coupled to an input node for receiving a pulsed signal. A collector of the first transistor is coupled to a first voltage source node. A base of the HBT is coupled to an emitter of the first transistor. A collector of the HBT is coupled to a second voltage source node configured to bias the HBT normally off. The HBT operating isothermally when the pulsed signal has a short-pulse width and a low duty cycle. The first transistor drives the HBT when the pulsed signal is received at the base of the first transistor to output an amplified pulsed signal at the collector of the HBT.

Abstract: A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit and a second Class AB amplifier circuit. A current mirror circuit is in communication with the first Class AB amplifier circuit. A bias circuit is in communication with the current mirror circuit. A frequency compensation circuit is arranged between the bias circuit and the second Class AB amplifier circuit. A common-mode feedback circuit is in communication with the second Class AB amplifier circuit. The common-mode feedback circuit is configured to generate a feedback signal.

Abstract: An output stage for an amplifier is provided. The amplifier generally provides for compensation of an error current generated by the base-collector (or gate-drain) capacitance of a common base (or gate) amplifier transistor. The stage accomplishes this by utilizing a three transistor Wilson current mirror to combine the error current with a mirrored bias current to reduce the load current on the common base (or gate) amplifier transistor.

Abstract: In an mode of this invention, a digital/analog conversion circuit, includes: a digital/analog conversion portion which outputs a first current according to an input digital signal; and a first current mirror circuit which generates a mirror current according to the first current and outputs the mirror current as an analog signal, the digital/analog conversion circuit converting the digital signal into the analog signal, and further including: a second current mirror circuit, which generates a first mirror current according to the first current; and a third current mirror circuit, which is connected to a reference voltage, and to which the first mirror current is input, and which generates a second mirror current equal to the first current, according to the first mirror current, between the digital/analog conversion portion and the second current mirror circuit.

Abstract: A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit configured to receive an input signal. A bias circuit is configured to receive an output of the first Class AB amplifier circuit. A second Class AB amplifier circuit is in communication with the bias circuit. The second Class AB amplifier circuit is configured to generate an output signal. A current mirror circuit is arranged between the first Class AB amplifier circuit and the bias circuit. A common-mode feedback circuit is configured to generate a feedback signal based on the output signal.

Abstract: A high gain stacked cascade amplifier includes a first amplifying element, a second amplifying element, a current mirror bias element, and a dynamic bias adjustment element. The first and second amplifying elements are coupled in series to form the high gain stacked cascade amplifier configuration. The current mirror bias element provides a bias to the first and second amplifying elements. The dynamic bias adjustment element is coupled to the second amplifying element. The dynamic bias adjustment element is configured to increase a gain compression point of a composite filter, formed by the first and second amplifying elements, in response to a determination that an input signal causes gain compression in the first amplifying element.

Abstract: An amplifier with bias stabilizer includes first to forth transistors, an amplifier unit and a resistor. The first transistor and the second transistor are connected in series between first and second power supplies and generate a first current. The third transistor is connected in a current mirror configuration to the second transistor and generates a second current corresponding to the first current. The amplifier unit generates an output signal based on an input signal and includes a fourth transistor, the fourth transistor generating a control voltage according to the second current so as to control the first transistor. The resistor is connected in series to at least one of the first to fourth transistors.

Abstract: A multi-input operational amplifier comprises two transconductors, two current mirrors, and a current source. Each transconductor generates a current according to a corresponding voltage difference. When the voltage difference is less than or equal to zero, the current is a constant. When the voltage difference exceeds zero, the current is proportional to the voltage difference.

Abstract: Techniques for detecting jammer signals in a received signal are described. In one aspect, high-speed current mirror resistive compensation circuits and output impedance boosting circuits are utilized to increase amplifier bandwidth in an improved wideband amplifier circuit. In another aspect, a dual transistor configuration including common source topology, averaging capacitors and a comparator circuit is utilized to improve the sensing of signal peaks in a peak detector block, which can be used together with the wideband amplifier circuit and a digital jammer detection circuit to detect jammer signals. The digital jammer detection circuit aids in the determination of the presence of jammer signals within the received signal, the determination of which may be variable due to programmability of the digital jammer detection circuit as described.

Abstract: An amplifier/comparator includes a multitude of output stages all sharing the same input stage. One or more of the output stages are amplification stages and have compensated output signals. A number of other output stages are not compensated and provide comparison signals. Each uncompensated output stage is adapted to switch to a first state if it detects a first input signal as being greater than a second signal, and further to switch to a second state if it detects the first input signal as being smaller than the second signal. By varying the channel-width (W) to channel-length (L) ratio (W/L) of the transistors disposed in the output stages, the trip points of the comparators and/or the electrical characteristics of the amplifiers are selectively varied.

Abstract: A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.

Abstract: The present invention relates to a circuit configuration for detecting and rapidly limiting large current increase based on high current injection at the output terminal (out). In particular, a gate-controlled switching device (PO), controlled by a driver circuit (40) through a low resistive element (RO) and passed through by a current overshoot, will be alternatively driven by the circuit of the present invention while having its control terminal charged by the high injected current. Thus, when large voltage increase generated by a steep front impulse with a positive slope is detected by the capacitor (C) and transmitted to the gate terminal (GateN), the circuit of the present invention bypasses the driver circuit (40) while injecting a significant current peak issued from the transistor (P3) towards the gate terminal (GateP) of the gate-controlled switching device (PO), whereas the capacitor (C) is discharging very slowly through the gate terminal (GateN).

Abstract: An operational amplifier includes an amplifying circuit and a bais current generating circuit. The bias current generating circuit generates a bias current to the amplifying circuit. The amplifying circuit comprises a current adjusting unit and a current mirror. The current adjusting circuit has a storage element, receives a reference current and generating a passing current. The passing current is gradually adjusted utilizing the storage element according to a control signal. The current mirror receives the passing current to generate the bias current.

Abstract: In an output stage of an operational amplifier, first and second transistors each provide a collector current under quiescent conditions to first and second current sources. A resistor receives a portion of one the collector currents and produces a resistor voltage in response. An output transistor provides a quiescent current having a value calculated as a function of the resistor voltage and a base-emitter voltage of the second transistor.

Abstract: A signal receiving device includes: a first conversion unit comprising a first input terminal to which a signal including a voltage signal and a reference voltage is inputted, and a first output terminal which output a first current signal voltage-current converted from the signal; a second conversion unit comprising a second input terminal to which the reference voltage is inputted, and a second output terminal which output a second current signal voltage-current converted from the reference voltage; a current mirror circuit comprising a third input terminal to which the second current signal is inputted, and a third output terminal which output a third current signal corresponding to the second current signal; and an output unit connected to both the first and third output terminals.

Abstract: A buffer amplifier has high input impedance and is less affected by temperature by supplying independent bias power to each of amplification units. The buffer amplifier includes a bias supply unit supplying bias power having a preset voltage level, an amplification unit receiving preset driving power and the bias power from the bias supply unit to amplify an input signal, and a compensation unit compensating for current unbalance of the driving power supplied to the amplification unit.

Abstract: An amplifying device includes a cascode amplifier and a biasing circuit. The cascode amplifier is configured to receive an input signal and to output an amplified output signal corresponding to the input signal. The biasing circuit is configured to bias the cascode amplifier, the biasing circuit including a first current mirror and a second current mirror stacked on the first current mirror. The biasing circuit improves linearity of the cascode amplifier across a wide temperature range.

Abstract: A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor.

Abstract: Embodiments of the invention show a bias circuit for providing a biasing signal at a bias connection. The bias circuit includes a bias transistor and a feedback node, wherein the feedback node is coupled to a control terminal of the bias transistor via a first impedance element. The feedback node is furthermore coupled to the bias connection via a second impedance element. The control terminal of the bias transistor is coupled to the bias connection via a bypass-coupling path, which bypasses the first impedance element and the second impedance element, such that there is a feedback path via the bypass-coupling path and via the bias transistor from the bias connection to the feedback node.

Abstract: This invention describes new and improved phased shifted injection oscillator, a phased shifted injection locked push-push oscillator and a phased array antennas (PAA). The PAAs in accordance with an exemplary embodiment of the present invention are low cost, and therefore can be used in various commercial applications, such as wireless communication or satellite mobile television.

Abstract: A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.

Abstract: A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current mirror and a controller. A capacitor is coupled to the current mirror. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.

Abstract: According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.

Abstract: A device and a method including current measurement and/or amplification is disclosed. One embodiment provides supplying a current to be measured to a current amplifier. The current is amplified by the current amplifier. The amplified current or a current generated is fed back therefrom to the current amplifier. The current amplifier may include a current mirror. Furthermore, at least one delay means may be used by which the process of current amplification and/or current feedback may be delayed correspondingly.

Abstract: There is provided an amplifier circuit includes: an amplifying transistor; a first transistor having a DC current amplification factor generally equal to the DC current amplification factor of the amplifying transistor and constituting a current mirror circuit in conjunction with the amplifying transistor; and a current source circuit being operable to supply a current to the first transistor and including a second transistor having opposite conductivity type to the conductivity type of the first transistor. The second transistor is operated in a saturation region at a power supply voltage lower than an operating voltage range so that the DC current amplification factor of the amplifying transistor can be detected.

Abstract: According to some embodiments, an apparatus may comprise an amplifier, wherein the amplifier comprises: an output stage formed of a positive output terminal providing a positive output voltage and a negative output terminal providing a negative output voltage; a load tank coupled in parallel with the output stage and configured to filter signals received at the amplifier; and a negative resistance block coupled in parallel with the output stage and the load tank.

Abstract: An amplifier circuit is disclosed having an output transistor for driving a complex load over a drive frequency range, wherein in the lower part of the range an inductive component of the load dominates and in the upper part the inductive component does not dominate. The amplifier circuit includes a current mirror circuit that is connected upstream of the output transistor and has a shunt path to a second potential, for the purpose of relatively reducing a DC current flowing through the output transistor in comparison with an AC current flowing through the latter.

Abstract: A circuit and a method for biasing a compound cascode current mirror (CCCM) that enables high-voltage swing at the output and accurate current mirroring is presented. The CCCM has mirror transistors and cascode transistors which may be of a different technology kind. The drain-source voltage Vds of the mirror transistor on the input leg of the CCCM is held at a voltage Vov that is generated by the biasing circuit; Vov is the overdrive voltage of the input mirror transistor of the CCCM and the value of Vov is maintained by the bias circuit and a feed-back amplifier such that the mirror transistor remains on the edge of its active region, over manufacture deviations and tracks even over operational conditions such as temperature and supply variations. The feed-back amplifier drives the gates of the cascode transistors and uses its feedback node to hold the Vds at Vov.

Abstract: An all-NPN bipolar junction current mirror circuit for mirroring an input reference current is disclosed. The circuit includes an input stage for providing an input reference current to the current mirror circuit, a reference stage for mirroring the input reference current and an output stage electrically connected to the reference stage for providing the mirrored input current to at least one load.

Abstract: The present invention relates to an trans-conductance amplifier, cooperating with a digital programmable current mirrors, can be applied to digital programmable current-mode integrated circuits, voltage control oscillators, adaptive frequency adjust mechanism, adaptive continuous analog filters via the corresponding trans-conductance adaptation controlled by the digital control signals. The present invention disclosed a digital programmable current mirror suitable for the second stage of the trans-conductance amplifier so as to reform the fixed gain trans-conductance amplifier to be digitally programmable.

Abstract: A transconductance compensating bias circuit is disclosed that includes a first field-effect transistor (FET) having a first electrode, a second electrode, and a gate connected to the first electrode, wherein a reference current flows through the first and second electrodes; a second FET having a first electrode, a second electrode, and a gate connected to the gate of the first FET, wherein a bias current flows through the first and second electrodes; a resistor connected to the second electrode of the first or second FET; and a comparison part configured to output a signal corresponding to the result of comparison of the first potential of the first electrode of the first FET and the second potential of the first electrode of the second FET. The reference current and the bias current are controlled by the output signal of the comparison part so as to equalize the first and second potentials.

Abstract: An operational amplifier includes an amplifying circuit and a bais current generating circuit. The bias current generating circuit generates a bias current to the amplifying circuit. The amplifying circuit comprises a current adjusting unit and a current mirror. The current adjusting circuit has a storage element, receives a reference current and generating a passing current. The passing current is gradually adjusted utilizing the storage element according to a control signal. The current mirror receives the passing current to generate the bias current.

Abstract: A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area.

Abstract: A first transistor is provided on a current path for a phototransistor. A first resistor is provided between one terminal of the first transistor and the power supply line. A second transistor forms a current mirror circuit in cooperation with the first transistor, which amplifies with a predetermined amplification factor the current that flows through the first transistor. A charge capacitor, one terminal of which is connected to a fixed electric potential, is charged with the current thus amplified. A second resistor is provided between one terminal of the second transistor and the power supply line.

Abstract: The present invention relates to an all n-type transistor current mirror for mirroring an input current to an output current. The current mirror comprises an input n-type transistor (T4, QO, T1) interposed between a positive supply plane (VCC) and an input node (104, 202, 310) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the input node (104, 202, 310). An output n-type transistor (T3, Q1, T2) is interposed between the positive supply plane (VCC) and an output node (106, 204, 314) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the output node (106, 204, 314). A feedback circuit equals base-emitter voltages of the input (T4, QO, T1) and the output transistor (T3, Q1, T2) in order to mirror the emitter current of the input transistor (T4, QO, T1) to the emitter current of the output transistor (T3, Q1, T2).

Abstract: A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage.

Abstract: A high frequency signal detection circuit includes an input terminal for a high frequency signal to be detected, a switch transferring the high frequency signal as intermittent ringing signal to a first node in response to a pulse signal whose frequency is lower than that of the high frequency signal, a transistor amplifying the signal at the first node, and outputting to a second node, a bias generator generating a bias voltage by which the transistor is operated in its weak inversion region, a resonant circuit outputting the bias voltage to the first node, and resonating the high frequency signal, a capacitor removing a high frequency component of the signal at the second node; and a judgment circuit judging whether or not the high frequency signal is inputted by detecting the signal at the second node, which has the same frequency as the pulse signal.

Abstract: A bias circuit 22 in a power amplifier 1 is provided with a VBE-controlled voltage source circuit 20 and a Nagata current mirror circuit 21. The Nagata current mirror circuit 21 includes a transistor Tr5 and a transistor Tr6. The transistor Tr5 has its emitter grounded, its base connected to a control input terminal 17 via a resistor R3, and its collector connected to that base via a resistor R4. The transistor Tr6 has its emitter grounded, its base connected to the collector of the transistor Tr5, and its collector connected to the base of the transistor Tr3. The arrangement is capable of compensating both the temperature characteristics of the gain of the power amplifier 1 and the control input voltage characteristics of the gain of the power amplifier 1. In other words, the arrangement is capable of reducing the temperature dependence and control input voltage dependence of the gain of the power amplifier 1.

Abstract: A circuit (e.g., a reconstruction filtering circuit) may include a single operational amplifier (op-amp) that is arranged to receive a voltage input and that is arranged to have a biasing of constant gmR, a first device capacitor that is operatively coupled to an output of the single op-amp, a first resistor that is operatively coupled to the first device capacitor, a second device capacitor that is operatively coupled to the first resistor, and a mirror device that is operatively coupled to the second device capacitor, where the mirror device is arranged to provide a feedback loop as a feedback input to the single op-amp and that is arranged to provide a current output.

Abstract: A self-biased cascode current mirror circuit, including a first transistor having a first current electrode, a control electrode, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the first current electrode of the first transistor, and a second current electrode coupled to a terminal; a third transistor having a first current electrode configured to provide an output current, a control electrode coupled to the control electrode of the first transistor and the first current electrode of the third transistor, and a second current electrode; and a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to the terminal.

Abstract: In an optical receiver and amplifier and an optical coupler, a technique for stabilize operations at turning on/off of a power supply by a simple configuration is desired. An optical receiver and amplifier includes: a photodiode generates a photocurrent in response to a light input; an output section outputs output voltage being a low level or a high level in response to a magnitude of the photocurrent by using a power supply voltage supplied from a power supply; and an output control circuit controls an input voltage of the output section such that the output voltage is set to the low level when the power supply is turned on or off during a period where the power supply voltage is lower than a predetermined value. The output voltage can be set to the low level so that an additional circuit for preventing malfunction is not needed.

Abstract: Embodiments of apparatuses, articles, methods, and systems for a bias network providing a stable transient response are generally described herein. Other embodiments may be described and claimed.