Abstract: An apparatus comprises a differential amplifier circuit and a current source. The differential amplifier circuit is configured to receive a voltage at an input, wherein the differential amplifier circuit generates an output voltage having a magnitude proportional to the received voltage over a voltage range to be measured at a specified output common mode voltage. The current source is electrically connected to an input of the differential amplifier circuit and is configured to subtract a midpoint of a voltage range of the battery voltage to be measured at the input of the differential amplifier, wherein a circuit supply voltage provided to the differential amplifier circuit and the current source is less than the voltage at the input.

Abstract: A method for operating a vehicle includes: specifying a time-related target power demand for the vehicle to an internal combustion engine; and switching in an additional powering device in addition to the internal combustion engine when a time-related actual power demand of the vehicle on the internal combustion engine deviates from the time-related target power demand. The present invention makes it possible to operate the internal combustion engine in a diagnosis mode largely independently of the specific driving situation.

Abstract: Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal.

Abstract: An amplifier includes a first transformer configured to output first differential signals, a first differential amplifier coupled to the first transformer, a second transformer coupled to the first differential amplifier, a second differential amplifier coupled to the second transformer, a third transformer configured to transform second differential signals output from the second differential amplifier to a single-ended output signal, and a first bias circuit configured to supply a first bias voltage to a first secondary coil of the first transformer, wherein the first bias circuit sets the first bias voltage to a voltage greater than or equal to a first voltage based on the input signal in a first operating area where power of the output signal is greater than or equal to a first power so that power-gain characteristics of the output signal become closer to characteristics where gain of the output signal becomes constant.

Abstract: In certain applications, differential amplifiers with infinite common mode rejection ratios are desirable. However, resistance mismatches due to imperfections in the manufacturing create finite common mode rejection ratio in differential amplifiers degrading their performance. Disclosed are apparatus and method for improving the common mode rejection ratio of practical differential amplifiers.

Abstract: A DC offset cancellation circuit is provided. The DC offset cancellation circuit includes a first operational amplifier and a feedback gain circuit. The first operational amplifier includes a first input transconductance stage, a second input transconductance stage and an output stage. An input terminal of the first input transconductance stage receives an input signal of the first operational amplifier through a first input terminal of the first operational amplifier. An output terminal of the output stage outputs an output signal of the first operational amplifier through an output terminal of the first operational amplifier. An input terminal of the feedback gain circuit is coupled to the output terminal of the first operational amplifier, and an output terminal of the feedback gain circuit is coupled to the input terminal of the second transconductance stage through a second input terminal of the first operational amplifier.

Abstract: A method for enabling AC coupling or DC coupling when receiving burst data signals comprises generating a hold-over pattern, wherein the hold-over pattern is a AC balanced pattern when an AC coupling is required and a low-logic value signal when a DC coupling is required; inputting the generated hold-over pattern to an AC coupling circuit, when no burst data signal is received; inputting only a received burst data signal to the AC coupling circuit, during the reception of such signal; and upon receiving of the entire burst data signal, generating a reset signal causing to input the generated holdover pattern to an AC coupling circuit.

Abstract: A multi-power domain operational amplifier includes an input stage circuit, a power domain transforming circuit and an active load. The input stage circuit is configured to transform a set of input voltages into a set of input currents in a first power domain. The power domain transforming circuit is configured to transform the set of input currents into a set of output currents in a second power domain. The active load is configured to generate an output voltage according to the set of output currents. A common mode range of the output voltage is shifted as compared with a common mode range of the set of input voltages.

Abstract: In some embodiments, a pilot signal generation circuit is provided including a buffer and a differential amplifier responsive to an output of the buffer. A first transistor is connected to control a reference voltage at an input of the buffer in response to a pulse width modulated logic signal and a second transistor connected to control a reference voltage at an input of the differential amplifier based on the pulse width modulated logic signal such that the second transistor is connected so as to turn on when the first transistor is turned off and to turn off when the first transistor is turned on. The differential amplifier is configured to provide at an output a pilot signal proportional to a gain of the differential amplifier.

Abstract: A high fidelity current dumping audio amplifier in which for achieving the best performance are combined the feedforward error correction and the negative feedback. The principle of feedforward error correction in a balanced bridge in A.C. is used, including the whole audio frequency amplifier, combined with a classical negative feedback that includes the items of the amplification chain likely to introduce distortions. The amplifier can be built in a current amplifier structure or in a voltage amplifier structure. The current amplifier structure contains an operational amplifier used as a voltage-current converter and signal de-phasing, two low power symmetrical current amplifiers operating in “A” class with a current mirror structure and a power stage in “B” class, with no quiescent current. The voltage structure of the amplifier contains an operational voltage amplifier, a low power amplifier operating in “A” class, and a power stage operating in “B” class.

Abstract: A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.

Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.

Abstract: An instrumentation amplifier includes a first amplifier having one input connected to a first input of the instrumentation amplifier, a second amplifier having one input connected to a second input of the instrumentation amplifier, and a feedback network. The feedback network including an active filter having a first low pass filter characteristic with a first cut-off frequency in respect of differential mode signals at the first and second inputs of the instrumentation amplifier, and a second low pass filter characteristic with a second cut-off frequency in respect of common mode signals at the first and second inputs of the instrumentation amplifier. The disclosure also relates to a device for acquiring biopotential signals and a signal amplification method.

Abstract: A common mode bias circuit may include a weak common mode bias generator and a common mode bias capacitance. During a first state of the common mode bias circuit, the weak common mode bias generator may be coupled to the common mode bias capacitance and may impart to them a predefined common mode signal level. During a second state of the common mode bias circuit, the common mode bias capacitance may be coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier.

Abstract: A circuit can include operational amplifier having a first input, a second input, and an output, first and second resistors in series between the output of the op-amp and a ground, and multiple switches configurable to toggle the circuit between a positive phase and a negative phase.

Abstract: A linear amplifier that comprises a signal input terminal that receives an input signal having a first common mode voltage, a voltage amplifier having a non-inverting input terminal that receives a second common mode voltage, a first and a second input resistance connected in series from the signal input terminal to the inverting input terminal of the voltage amplifier, a feedback resistance connected between the inverting input terminal and the output terminal of the voltage amplifier, and a constant current source. The constant current source supplies a constant current to a middle node between the first and the second input resistances. The constant current generates a voltage drop, which is equal to a difference between the first and the second common mode voltages, across the first input resistance. Accordingly, the common mode voltage of the output signal is directly determined by the second common mode voltage.

Abstract: A semiconductor device includes: an amplifier circuit that has an inverting input terminal, a non-inverting input terminal, and an output terminal; a first variable voltage source that generates a first bias voltage having a voltage value corresponding to a first set value; a second variable voltage source that generates a second bias voltage having a voltage value corresponding to a second set value; a first resistor whose one end is connected to the inverting input terminal; a second resistor that is connected between the output terminal and the inverting input terminal; a third resistor whose one end is connected to the non-inverting input terminal; and a fourth resistor that is connected between the second variable voltage source and the non-inverting input terminal. The first bias voltage is provided to the other end of the first resistor. An input signal is provided to the other end of the third resistor.

Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from ?(2n-1?1) to +(2n-1?1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.

Abstract: A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.

Abstract: This document discusses, among other things, an amplifier circuit including first and second amplifiers configured to receive an input signal and to provide a differential output signal using a feedback loop including a transconductance amplifier. A non-inverting input of a first amplifier can be configured to receive an input signal. The feedback loop can be configured to receive the outputs from the first and second amplifiers and to provide a feedback signal to the non-inverting input of the second amplifier, for example, to reduce a DC offset error or to increase a dynamic range of the amplifier circuit.

Abstract: This invention provides a multi-stage amplifier incorporating DC offset cancellation. The amplifier has a plurality of series-connected gain stages each of which comprises a differential amplifier unit generating a pair of differential outputs from a pair of differential inputs. In particular, a trailing stage in the plurality of gain stages comprises a digital DC offset cancellation module configured to compensate for a DC offset of the trailing stage's differential amplifier unit. The digital DC offset cancellation module comprises a comparator coupled to the pair of differential outputs of the trailing stage's differential amplifier unit for receiving such differential outputs as inputs for the comparator. Preferably, the comparator has an inherent DC offset that is substantially small. It is preferable that a non-trailing stage of the amplifier comprises an analog DC offset cancellation module for compensating for a DC offset of the non-trailing stage.

Abstract: A signal level conversion circuit 1 includes a first differential amplifier circuit 10 and a second differential amplifier circuit 20. The first differential amplifier circuit 10 multiplies a potential difference between a first input signal and a second input signal by G1 thereby providing an output signal. The second differential amplifier circuit 20 multiplies a potential difference between the output signal of the first differential amplifier circuit 10 and the second input signal by G2 thereby providing an output, where the two gains satisfy the relation of G1×G2<0 and 0<?(G1+1)×G2<2.

Abstract: A system and method for adjusting a common mode output voltage in an instrumentation amplifier is provided. In one aspect, the common mode output voltage is increased or decreased with respect to the common mode input voltage to enable high amplification of the signal input to the instrumentation amplifier. Moreover, the common mode output voltage can be driven to (or approximately to) a target voltage value such as, but not limited to, half the supply, even if the common mode input voltage is close to supply or ground rail voltage. Thus, a high amplification of the differential input voltage can be obtained and utilized for various applications requiring rail to rail input.

Abstract: A semiconductor integrated circuit includes: a first capacitance element and a second capacitance element; a first amplification circuit that amplifies a potential difference of a first voltage signal and a second voltage signal supplied via the first capacitance element and the second capacitance element, respectively, to output a first amplification signal and a second amplification signal; a first resistance element that feeds back the first amplification signal to one input terminal of the first amplification circuit; a second resistance element that feeds back the second amplification signal to another input terminal of the first amplification circuit; a voltage generator that generates a predetermined voltage; and a third resistance element that transmits the predetermined voltage generated by the voltage generator to each input terminal of the first amplification circuit.

Abstract: A comparator circuit comprising an operational amplifier configured to compare a difference between a switching voltage and a reference voltage, and a dynamically adjustable bias current generator coupled to the operational amplifier. A method of conserving power in a comparator circuit includes estimating a switching regulator load current value, communicating the value to a current bias generator, enabling the bias generator with a signal from a switching regulator PFM logic circuit, and establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling.

Abstract: A bias voltage source for a differential circuit has low output impedance at DC, but considerably higher output impedance within the frequency band of the differential signal being processed, to provide an accurate, well-matched common-mode bias voltage to each component of a differential signal path, while providing a low noise current, minimizing the conversion between common-mode and differential modes, and preserving available headroom, and all without requiring the use of large resistors.

Abstract: A control circuit is for generating upper and lower voltages that define a range of a data voltage for controlling a driving transistor of an electroluminescent component coupled to a supply line through the driving transistor. The control circuit may include a first input terminal configured to have a common voltage, and a pair of amplifiers coupled together at the first input terminal and configured to generate the upper voltage and the lower voltage to correspond to a difference between the common voltage and, respectively, first and second analog intermediate voltages representing respective threshold values of the upper voltage and of the lower voltage. The control circuit may include an auxiliary amplifier configured to adjust the upper voltage and the lower voltage based upon fluctuations of an input voltage, and generate the common voltage to correspond to the difference between the input voltage and a reference voltage.

Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, a method of electronic amplification includes amplifying a differential input voltage signal to generate a feed-forward signal, chopping the feed-forward signal at a chopping frequency to generate a chopped feed-forward signal, notch filtering the chopped feed-forward signal at the chopping frequency to generate a notched signal, generating an input offset correction signal based at least partly on the notched signal, and amplifying the differential input voltage signal using a signal amplification block to generate an output signal. Amplifying the differential input voltage signal using the signal amplification block includes chopping the input signal at the chopping frequency to generate a chopped input signal and combining the chopped input signal and the offset correction signal to reduce input offset error of the signal amplification block.

Abstract: When a switch is set to off, and a switch is set to on, the voltage of a SigOut terminal is stabilized with a reference voltage, and a bias voltage is applied to a capacitor. Changing the switch from on to off, with the bias voltage retained in the capacitor, a detection signal which is input via a SigIn terminal is amplified with the reference voltage as a reference, and an amplified signal is output from the SigOut terminal.

Abstract: An auto-zero amplifier is disclosed, having an amplifying circuit, a switch, and a difference signal generating circuit. The amplifying circuit receives a first input signal for generating a first output signal, and receives a second input signal for generating a second output signal. The switch is coupled between the amplifying circuit and a capacitor. The switch is conducted for charging or discharging the capacitor to a voltage with the first output signal, and the switch is not conducted for keeping the capacitor at the voltage. The difference signal generating circuit is coupled with the amplifying circuit and the capacitor for generating a difference signal of the first output signal and the second output signal, a multiple of the difference signal, a part of the difference signal, and/or a digital output value for the difference signal.

Abstract: An amplifier circuit capable of reducing load of a circuit at the previous stage by providing increased input impedance producing less noises. The amplifier circuit includes a fully-differential operational amplifier composed of an inverting input terminal, a non-inverting input terminal receiving a signal different from a signal to be input to the inverting input terminal, an inverting output terminal with the same polarity of the inverting input terminal, and a non-inverting output terminal with reverse polarity; an input impedance element with one end connected to the inverting input terminal; an input impedance element with one end connected to the non-inverting input terminal; and positive feedback impedance elements, with one end of connected to the other end of the input impedance element and the other end connected to the inverting output terminal or to the non-inverting output terminal.

Abstract: In some embodiments, a pilot signal generation circuit is provided including a buffer and a differential amplifier responsive to an output of the buffer. A first transistor is connected to control a reference voltage at an input of the buffer in response to a pulse width modulated logic signal and a second transistor connected to control a reference voltage at an input of the differential amplifier based on the pulse width modulated logic signal such that the second transistor is connected so as to turn on when the first transistor is turned off and to turn off when the first transistor is turned on. The differential amplifier is configured to provide at an output a pilot signal proportional to a gain of the differential amplifier.

Abstract: Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal.

Abstract: A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.

Abstract: A multi-mode OPAMP-based circuit is provided. An input amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. An output amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is disposed in a first negative feedback loop of the output amplifying stage. A second capacitor is disposed in a second negative feedback loop of the output amplifying stage. A third capacitor is selectively disposed in a first positive feedback loop of the output amplifying stage or coupled to the first capacitor in parallel according to a control signal. A fourth capacitor is selectively disposed in a second positive feedback loop of the output amplifying stage or coupled to the second capacitor in parallel according to the control signal.

Abstract: In one embodiment, a method includes applying, by a transimpedance amplifier at a receiving end of a communication link, equalization to a signal carried by the communication link at the receiving end of the communication link.

Abstract: An amplifier with improved noise reduction is disclosed. In one implementation, an amplifier is provided that includes a main output stage configured to output an amplified signal at a main output terminal, a secondary output stage configured to output a copy of the amplified signal at a secondary output terminal, and a signal coupler configured to provide a variable resistance coupling between the secondary output terminal and the main output terminal to reduce noise at the main output terminal.

Abstract: An amplifier arrangement constituted of: a first input lead; a second input lead; a difference amplifier; a first buffer, the input of the first buffer coupled to the first input lead, the output of the first buffer coupled to a first input of the difference amplifier; a second buffer, the input of the second buffer coupled to the second input lead, the output of the second buffer coupled to a second input of the difference amplifier; and a transconductance amplifier, the non-inverting input and the non-inverted output of the transconductance amplifier coupled to the first input of the difference amplifier, the inverting input and the inverted output of the transconductance amplifier coupled to the second input of the difference amplifier. The input signals are thus buffered and the offset of the buffers are compensated for.

Abstract: A communications system includes a communications device having a plurality of access modules each having a port and connected to a communications line and a plurality of transmitters with the respective transmitter associated in one-to-one correspondence with the communications line of an access module. Each transmitter has a line driver and is configured to couple communications signals to a respective communications line. A voltage source is connected to the line drivers and configured to provide a bias voltage to the line drivers that varies depending on a selected minimum power level. A controller is connected to the voltage source and has logic configured to change the bias voltage to the line drivers. The controller is responsive to a minimum data rate for each bias voltage.

Abstract: Apparatus and methods reduce increase the common mode range of a difference amplifier. A circuit uses one or more floating powers and one or more floating grounds coupled to an input stage of an amplifier to increase the common mode range of a difference amplifier. The floating power can be configured to select from the greater of the voltage level of one of the differential signals and the system power high source. The floating ground can be configured to select from the lesser of the voltage level of one of the differential signals and the system power low source.

Abstract: Systems and methods are disclosed to provide automatic power control for a driver circuit. Embodiments disclosed herein enable a driver circuit to automatically decrease the gain of amplified input signals when output power exceeds a threshold. Further, embodiments disclosed herein enable a driver circuit to automatically increase the gain of amplified input signals when battery supply voltage drops to avoid unwanted output signal distortion. By using reference signals for battery power and amplified signal input, the amplifiers of the driver circuit can be automatically adjusted until an equilibrium is reached.

Abstract: When a time difference is amplified by a time difference amplifier, slew rates of internal output voltages are changed according to a phase combination of digital input signals so that a time gain is determined by a ratio between the slew rates and the slew rates can be controlled from an outside. After a voltage is charged to the level of a power supply voltage in first and second charging capacitors, the charged voltage of the first charging capacitor is decreased with a first slew rate when a first digital input signal transitions, and both charged voltages of the first and second charging capacitors are decreased with a second slew rate when a second digital input signal transitions so that both first and second digital input signals are changed from initial phases, while being compared with a reference voltage to generate first and second digital output signals.

Abstract: A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.

Abstract: An adjustable gain audio power amplifying circuit includes an input unit, an audio amplifying unit connected to the input unit, a gain adjusting unit connected to the audio amplifying unit, a controlling unit connected to the gain adjusting unit, a comparing unit connected between the gain adjusting unit and the controlling unit and an output unit connected to the audio amplifying unit. The comparing unit compares an outputted signal of the output unit with a common-mode reference voltage, outputs a gain adjustment controlling signal and sends the gain adjustment controlling signal into the controlling unit. When the outputted signal equals the common-mode reference voltage, the gain adjustment controlling signal turns over and then the controlling unit detects the turnover and sends a received gain adjustment signal into the gain adjusting unit. Based on the received gain adjustment signal, the gain adjusting unit controls gains of the adjustable gain audio power amplifying circuit.

Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

Abstract: This application describes a system for minimizing the common mode voltage drift at the input of a fully differential amplifier. An impedance component is coupled to the inputs and outputs of the differential amplifier. The impedance component optimizes the common mode resistance or impedance to ground without significantly affecting the differential impedance, matches the input common mode voltage to the output common mode voltage and reduces the input common mode voltage drift in presence of leakage currents.

Abstract: A bias voltage source for a differential circuit has low output impedance at DC, but considerably higher output impedance within the frequency band of the differential signal being processed, to provide an accurate, well-matched common-mode bias voltage to each component of a differential signal path, while providing a low noise current, minimizing the conversion between common-mode and differential modes, and preserving available headroom, and all without requiring the use of large resistors.

Abstract: In various embodiments, a pilot signal generation circuit is provided having an operational amplifier buffer connected via a first resistor to receive a source reference voltage. A differential amplifier is connected at a first input to receive the source reference voltage and at a second input to an output of the operational amplifier buffer. A first shunt transistor is connected to shunt the source reference voltage at the operational amplifier buffer in response to pulse width modulated signal. A second shunt transistor is connected to the differential operational amplifier so as to shunt the source reference voltage in response to an output of the first shunt transistor. The output of the differential amplifier provides a pulse width modulated bipolar signal at precision voltage levels in response to the pulse width modulated signal.

Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, a method of electronic amplification includes amplifying a differential input voltage signal to generate a feed-forward signal, chopping the feed-forward signal at a chopping frequency to generate a chopped feed-forward signal, notch filtering the chopped feed-forward signal at the chopping frequency to generate a notched signal, generating an input offset correction signal based at least partly on the notched signal, and amplifying the differential input voltage signal using a signal amplification block to generate an output signal. Amplifying the differential input voltage signal using the signal amplification block includes chopping the input signal at the chopping frequency to generate a chopped input signal and combining the chopped input signal and the offset correction signal to reduce input offset error of the signal amplification block.

Abstract: An optical transceiver and/or optical network, and methods of monitoring optical transceivers, may be useful for increasing the dynamic range and/or determining the received signal strength and/or link budget of the optical transceiver and/or a different optical transceiver in the optical network. The circuitry generally comprises a photodiode configured to generate a first current responsive to an optical signal, a current mirror configured to produce a second current equal or proportional to the first current, and a nonlinear element configured to produce a first voltage from the first current.