Abstract: A system and method for frequency hopping precalibrates a subset of a plurality of channels, storing the channels' associated curves in a computer readable medium. Before hopping to a new channel, decision making circuitry can access the precalibrated curves. If the destination channel has an associated curve, then the system can use the values from that curve when hopping to a new channel. If the destination channel does not have an associated precalibrated curve, then the system can identify a closely situated channel with a precalibrated curve and use an offset value to settle at the destination channel. According to another aspect of the present invention, the offsets can be updated. According to a further aspect of the invention, the updated can be done dynamically.

Abstract: The present invention relates to a narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver comprises an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop.

Abstract: This disclosure includes systems and methods for frequency synthesis using a voltage-controlled oscillator (VCO) with a programmable array of capacitors. A suitable setting for the capacitor array may be derived through a non-successive iterative numerical technique. In one aspect, the iterative numerical technique may apply Newton's method to an equation relating frequency generated by the VCO and the capacitor setting of the first programmable array of capacitors. In another aspect, a secant method may be applied to determine a capacitor array setting based on previously and currently applied capacitor settings and the corresponding measured frequencies.

Abstract: An apparatus, and an associated method, for synthesizing a discrete-valued oscillating signal. Input parameters are provided that are determinative of the frequency, gain, and phase characteristics of the resultant, oscillating signal. The discrete-valued, oscillating signal is combinable with another signal to form a mixed signal of a desired frequency, gain, and phase characteristic using a single complex multiplication operation.

Abstract: A radio frequency circuit and a signal transmission method are provided. The radio frequency circuit comprises a primary antenna, a secondary antenna and a radio frequency integrated circuit. The primary antenna is electrically coupled to the radio frequency integrated circuit to transmit and receive at least one transmission/reception signal. The secondary antenna is electrically coupled to the radio frequency integrated circuit to receive at least one diversity reception signal. The radio frequency integrated circuit is configured to receive a specific diversity reception signal via the primary antenna and to transmit and receive a specific transmission/reception signal via the secondary antenna.

Abstract: Disclosed is a statistical reference oscillator that includes: a stochastic reference clock generator which receives an input data outputs a reference signal obtained by dividing the received input data at a first frequency division ratio; a frequency divider which divides the frequency of an output signal at a second frequency division ratio and outputs a feedback signal; a frequency detector which outputs a difference signal based on a difference between the reference signal and the feedback signal; and an output signal generator which outputs the output signal based on the difference signal.

Abstract: An oscillation apparatus corrects a setting value for an output frequency based on a detection result of an environmental temperature. The oscillation apparatus includes a first crystal unit, a second crystal unit, an integrated circuit chip, and a container. The first crystal unit includes first excitation electrodes on respective surfaces of a crystal element. The second crystal unit includes second excitation electrodes on respective surfaces of a crystal element. The integrated circuit chip includes a first oscillation circuit, a second oscillation circuit, and a correction unit. The container houses the first crystal unit, the second crystal unit, and the integrated circuit chip. Assuming that distances from a gravity center position of the integrated circuit chip to respective gravity center positions of the first excitation electrodes and the second excitation electrodes in plan view are denoted by D1 and D2, D1/D2 is within a predetermined range close to 1.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±?/2), the phase information dynamic range is divided by a factor (e.g., by 2), and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator performs gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +? (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal.

Abstract: A current reuse voltage controlled oscillator with improved differential output is disclosed. In an exemplary embodiment, an apparatus includes a PMOS transistor and an NMOS transistor coupled together for current reuse and configured to provide differential oscillator outputs. The apparatus also includes a common mode rejection (CMR) circuit coupled between the PMOS and the NMOS transistors, the CMR circuit includes an inductor having a least one tap that can be selectively coupled to a ground to reduce common mode signals at the differential oscillator outputs.

Abstract: In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path.

Abstract: The embodiments described herein provide a voltage controlled oscillator (VCO). The VCO may include, but is not limited to a voltage-to-current converter configured to receive a control voltage and to convert the control voltage to a current, a current bias circuit coupled to the voltage-to-current converter and configured to receive frequency band select digital inputs and to bias the current generated by the voltage-to-current converter based upon the band select inputs, and a ring oscillator coupled to receive the biased current and to output an oscillating signal based upon the biased current.

Abstract: In some embodiments, provided are calibration techniques for measuring mismatches between TDL delay stage elements, and in some cases, then compensating for the mismatches to minimize performance degradation.

Abstract: Methods and apparatus for calibration and temperature compensation of oscillators having mechanical resonators are described. The method(s) may involve measuring the frequency of the oscillator at multiple discrete temperatures and adjusting compensation circuitry of the oscillator at the various temperatures. The compensation circuitry may include multiple programmable elements which may independently adjust the frequency behavior of the oscillator at a respective temperature. Thus, adjustment of the frequency behavior of the oscillator at one temperature may not alter the frequency behavior at a second temperature.

Abstract: A current reuse voltage controlled oscillator with improved differential output is disclosed. In an exemplary embodiment, an apparatus includes a PMOS transistor and an NMOS transistor coupled together for current reuse and configured to provide differential oscillator outputs. The apparatus also includes a common mode rejection (CMR) circuit coupled between the PMOS and the NMOS transistors, the CMR circuit includes an inductor having a least one tap that can be selectively coupled to a ground to reduce common mode signals at the differential oscillator outputs.

Abstract: A phase locked loop comprising: an oscillator for generating an output signal of a frequency that is dependent on an input to the oscillator; sampling means for generating a sequence of digital values representing the output of the oscillator at moments synchronized with a reference frequency; a difference unit for generating a feedback signal representing the difference between successive values in the sequence; and an integrator for integrating the difference between the feedback signal and a signal of a desired output frequency; the signal input to the oscillator being dependent on the output of the integrator.

Abstract: The present invention provides a locking method and system, and the method includes: a locking system performing a phase discrimination and conversion process to an input signal Fi of an external standard source and a feedback output signal F0 of a local thermostatic crystal oscillator which pass through a frequency division, to generate a clock signal clk and a signal sign which is used to denote a frequency size relationship between the signal Fi and the signal F0, and performing a filtering process to the signal clk and the signal sign, and performing a voltage controlled oscillation process to a signal ahead used to denote that the frequency of the signal F0 is lower than the frequency of the signal Fi and a signal lag used to denote that the frequency of the signal F0 is higher than the frequency of the signal Fi, to implement a locking of the signal F0 and the signal Fi.

Abstract: A method for processing a signal with a corresponding noise profile includes analyzing spectral content of the noise profile, filtering at least one noise harmonic within the signal based on the analyzed spectral content, and limiting the filtered signal. The noise profile may include a phase noise profile. The signal may include a sinusoidal signal and/or a noise signal. At least one filter coefficient that is used to filter the at least one noise harmonic may be determined. The filtering may include low pass filtering. The limiting may include hard-limiting of the filtered signal. A phase difference between the limited signal and a reference signal may be detected.

Abstract: A modulation section including a feedback circuit configured to conduct feedback control of an output signal from a voltage controlled oscillator based on an inputted modulation signal, and a feed-forward circuit configured to calibrate the modulation signal and outputting the calibrated modulation signal to the voltage controlled oscillator; a signal output section configured to output, to the modulation section, a predetermined reference signal instead of the modulation signal when a calibration is conducted; and a gain correction section configured to, in a state where the feedback circuit is forming an open loop, calculate a frequency transition amount of the reference signal outputted by the voltage controlled oscillator, and correct a gain used for calibrating the modulation signal at the feed-forward circuit based on the calculated frequency transition amount.

Abstract: Provided is a device and a method for adjusting a loop filter gain in an automatic frequency controller, which can allow the automatic frequency controller to operate while maintaining an optimal performance. The device includes a velocity estimator for estimating a change in velocity in accordance with a movement of a terminal; a loop filter gain controller for controlling a loop filter gain in accordance with a change in velocity received from the velocity estimator; and a loop filter gain unit for multiplying a loop filter gain received from the loop filter gain controller and a frequency error for output. Further, there is provided a method for adjusting a loop filter gain in an automatic frequency controller, having the steps of: estimating a change in velocity in accordance with a movement of a terminal; adjusting a loop filter gain in accordance with the estimated change in velocity; and multiplying the adjusted loop filter value and a frequency error for output.

Abstract: A method and apparatus is disclosed for voltage-controlled oscillator selection in a multi-mode system having multiple voltage-controlled oscillators. Part of oscillator selection is a calibration operation that utilizes maximum and minimum capacitance limits for a voltage-controlled oscillator, which translates to a frequency range, to calculate overlap regions. Overlap regions comprise frequency ranges that overlap such that the overlap region may be generated by two voltage-controlled oscillators with adjacent frequency ranges. One voltage-controlled oscillator selection routine comprises a real time voltage-controlled oscillator calibration and selection routine that executes every time the system requests a new frequency. Another selection routine comprises a start-up routine that executes only at power up or periodically.

Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Abstract: An oscillator includes a nominal frequency output unit, a frequency adjustment amount output unit, a gain output unit, a multiplier, and an adder. The nominal frequency output unit is configured to output a first digital value corresponding to the nominal frequency. The frequency adjustment amount output unit is configured to output a second digital value corresponding to a rate of frequency in order to set a frequency adjustment amount with respect to the nominal frequency using the rate of frequency. The gain output unit is configured to output a third digital value corresponding to a gain to be multiplied by the second digital value. The multiplier is configured to multiply the second digital value by the third digital value, thus outputting a fourth digital value. The adder adds the first digital value and the fourth digital value to output the added result as a setting signal of frequency.

Abstract: An oscillating signal generator utilized in a phase-locked loop (PLL) includes: an oscillating circuit arranged to generate an oscillating signal according to at least a first control signal; and a control circuit, arranged to adjust the first control signal according to a temperature; and the first control signal is tuned between a first boundary and a second boundary, and when the temperature is closer to a first temperature boundary than a second temperature boundary, and the control circuit is arranged to make the first control signal to be closer to the first boundary than the second boundary such that the oscillating circuit outputs the oscillating signal of a predetermined frequency in a locked mode of the PLL.

Abstract: A local oscillation generator (LO-GEN) maintains a fixed bandwidth using a voltage controlled oscillator (VCO) calibration module and gain calibration module that together compensate for variations in the VCO gain based on the oscillation frequency. During an open loop calibration of the LO-GEN, the VCO calibration module programs the VCO gain to an initial coarse value based on the oscillation frequency and then the gain calibration module adjusts the charge pump current to compensate for VCO gain changes.

Abstract: An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component.

Abstract: A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

Abstract: A voltage-controlled oscillator (VCO) control circuit, used for controlling a VCO to process phase locking procedure after receiving a frequency locking signal, comprises an operating frequency controller and a judgment unit. The operating frequency controller, coupled to the VCO and the judgment unit, generates one of a first control code and a second control code to the VCO. The judgment unit, coupled to an input end of the VCO, generates a phase locking signal according to a voltage control signal inputted to the VCO. When the operating frequency controller receives the frequency locking signal, the operating frequency controller generates a first control code to control the VCO to switch from a first candidate VCO curve to a second candidate VCO curve. When the operating frequency controller receives the phase locking signal, the operating frequency controller generates a second control code to control the VCO to switch from the second candidate VCO curve to the first candidate VCO curve.

Abstract: An integrated CMOS clock generator with a self-biased phase locked loop circuit comprises a phase-frequency detector with a reference signal input, a feedback signal input and an output. A first charge pump of the clock generator has an input connected to the output of the phase-frequency detector and an output that supplies a control voltage. A loop capacitor is connected to the output of the first charge pump. The clock generator further has a second charge pump with an input connected to the output of the phase-frequency detector and an output. In particular, the clock generator has two oscillator blocks.

Abstract: Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter.

Abstract: Systems, methods, and circuits provide a time to digital converter comprising a sigma-delta modulator. The sigma-delta based time to digital converter may receive an analog signal representing a phase error between a reference clock signal and a feedback clock signal and generate a digital signal representing the phase error. The sigma-delta modulator may comprise a subtractor, an integrator, a feedback path, and a quantizer. The subtractor may receive the analog signal and subtract a feedback signal from the analog signal and the integrator may integrate the output of the subtractor. The sigma-delta modulator may accumulate a voltage or a charge over a capacitor as pulses are received from the analog signal and after a number of clock cycles, the capacitor may be discharged to generate a pulse in an output signal.

Abstract: A limiter circuit in a voltage controlled oscillator (VCO) includes a first control circuit, a second control circuit and a driving circuit having a pull-up transistor and a pull-down transistor. The first control circuit generates a first driving control signal for controlling the pull-up transistor based on an AC input signal and a first DC bias voltage. The second control circuit generates a second driving control signal for controlling the pull-down transistor based on the AC input signal and a second DC bias voltage. The driving circuit generates an output signal based on the first driving control signal and the second driving control signal. The output signal swings between a first voltage at the pull-up transistor and a second voltage at the pull-down transistor.

Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: A PLL including an adaptive loop filter. The PLL includes a feedback circuit which provides a feedback signal based on an output signal and a phase detector generating an adjust signal based on a frequency of the feedback signal compared with a reference frequency. A charge pump receives the adjust signal and provides a control voltage. The adaptive loop filter includes a capacitor and an adaptive resistance with a current control input. A VCO has an output providing the output signal based on a voltage level of the control voltage. A bias generator converts the control voltage to a loop bias current, and has a bias output based on the loop bias current coupled to the current control input of the adaptive resistance. The bias output of the bias generator may also be used to control the charge current and the VCO using currents proportional to the loop bias current.

Abstract: A circuit includes a controllable oscillator and a controller coupled to the controllable oscillator. The controller is configured to provide a current control and a gain control to the controllable oscillator. The gain control is configured to change a gain of the controllable oscillator during a calibration process.

Abstract: A circuit includes a first path including a first transistor and a first current source. The first transistor is responsive to a tuning voltage. The circuit also includes a tuning voltage range extension circuit responsive to the tuning voltage. The tuning voltage range extension circuit is configured to selectively change current supplied by the first path as the tuning voltage exceeds a capacity threshold of the first transistor.

Abstract: Microelectromechanical resonators include a resonator body with a built-in piezoelectric-based varactor diode. This built-in varactor diode supports passive frequency tuning by enabling low-power manipulation of the stiffness of a piezoelectric layer, in response to controlling charge build-up therein at resonance. A resonator may include a composite stack of a bottom electrode, a piezoelectric layer on the bottom electrode and at least one top electrode on the piezoelectric layer. The piezoelectric layer includes a built-in varactor diode, which is defined by at least two regions having different concentrations of electrically active dopants therein.

Abstract: A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency.

Abstract: An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (?fmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.

Abstract: A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.

Abstract: A digital compensation phase locked loop circuit of a semiconductor device includes a phase locked loop circuit including a voltage controlled oscillator having capacitors at oscillation nodes and consecutively controlled by an applied voltage, and a digital compensation circuit which variably controls the capacitors at the oscillation nodes of the voltage controlled oscillator in accordance with an input phase difference. A gain of the conventional voltage controlled oscillator whose gain is determined by an applied voltage is discretely changed by a control signal of the digital compensation circuit. The digital compensation circuit dynamically controls the gain so as to secure the optimum phase margin by applying a load (capacitor) to the oscillation node of the voltage controlled oscillator with respect to a phase lead and decreasing the load (capacitor) with respect to a phase delay.

Abstract: In an embodiment, a primary charge pump and replica charge pump may be coupled to matching control mechanisms and loads. In an embodiment, the replica charge pump may produce an error current originating from charge pump timing mismatches in a steady locked loop state. The error current produced by the replica charge pump may be measured by a difference amplifier to adjust at least one current source to compensate for the error current originating from the timing mismatches. To adjust the current sources, the amplifier may cause the current source to produce an equal but opposite current to cancel the effects of the error current, resulting in a constant output voltage.

Abstract: A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop.

Abstract: A method and apparatus for compensating for temperature variation in a phase locked loop (PLL) includes receiving an error signal by a controller in which the error signal representative of an instantaneous frequency difference between a reference frequency signal and an output frequency signal of a voltage controlled oscillator of the PLL, and determining when a voltage of the error signal is outside of a predetermined voltage range. When the voltage is outside the predetermined voltage range, the method includes generating a new digital compensation signal based upon a previous digital compensation signal, and converting the new digital compensation signal to be an analog compensation signal. The method further includes filtering the analog compensation signal by a filter to produce a filtered analog compensation signal, and adjusting the output frequency of the voltage controlled oscillator in accordance with the filtered analog compensation signal.

Abstract: A PLL frequency synthesizer provides improved phase noise characteristics. In an ADPLL frequency synthesizer, a frequency characteristic adjusting unit compares a predetermined threshold to the difference between the fractional portion of a DCO control signal and the closest integer value, and generates an adjustment signal. A supplementary varactor shifts the oscillating frequency characteristics based on the adjustment signal. By setting the predetermined threshold to a value defining the range in which the possibility of incrementing or decrementing is high, the oscillating frequency characteristics are shifted in cases when the target value of the fractional portion of the DCO control signal is in the range in which the possibility of incrementing or decrementing is high. By shifting the oscillating frequency characteristics, the target value of the fractional portion of the DCO control signal are shifted to a range in which the possibility of incrementing or decrementing is low.

Abstract: A digital to analog converter (DAC) that reduces sub-threshold leakage current in PLLs includes three series connected transistors, a unity gain buffer, and a switch. The system is connected between the voltage-to-current converter and a current-controlled oscillator. The DAC receives and accurately mirrors a current signal generated by a voltage-to-current converter.

Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided having an output signal having a frequency responsive to a tuning signal. The VCO includes: a plurality of inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, each inverter stage including a plurality of switched-capacitor circuits configured to control a signal delay through the inverter stage response to the tuning signal so as to control the frequency of the output signal; and a bias circuit configured to generate the bias voltage responsive to a reference signal such that an amplitude of the output signal is substantially independent of the output signal frequency and depends upon the reference signal.

Abstract: Embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic frequency modulation. In one embodiment, an apparatus comprises a first cell comprising a chaotic signal generator to generate a chaotic signal and a phase-locked loop (PLL) to generate a modulated output signal based at least on an un-modulated reference signal and the chaotic signal.

Abstract: A digitally-controlled oscillator circuit receives a digital value and generates a driving signal for driving an oscillator at a frequency according to the received digital value. A time-to-digital converter circuit receives a detection signal of oscillation of the oscillator, receives the driving signal, and detects a phase difference between the detection signal and the driving signal. A control circuit receives the detected phase difference and controls the frequency of the driving signal generated by the digitally-controlled oscillator circuit, such that the detected phase difference coincides with a predetermined resonant phase difference to resonate the oscillator.