Abstract: A method of controlling a clock signal with a print controller is provided. In response to receiving an external signal, the print controller determines the number of cycles of a clock signal generated by a ring oscillator of the print controller during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and outputs the determined number of cycles to an external circuit. In response to receiving a trim value from clock trim circuitry of the print controller which trims the frequency of the clock signal based on the determined number of cycles from the external circuit, the trim value is stored in memory of the print controller. The clock trim circuitry is controlled to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

Abstract: A method for reducing a phase noise in a digital fractional-N phase lock loop (PLL) is disclosed. The method comprises: quantifying a time difference between a reference clock and a feedback clock into a time difference signal; generating a residual error signal according to the time difference signal and an instantaneous error signal; filtering the residual error signal to generate a control code; controlling an oscillator using the control code to generate an output clock; receiving a fractional number between 0 and 1 to generate the instantaneous error signal; and dividing down the output clock by a divisor value according to the fractional number.

Abstract: A method of calibrating oscillators is disclosed that includes searching, in an array storing an operational characteristic of the oscillator, for an index value that is associated with an output of the oscillator; determining that the output is within a predetermined accuracy as compared to a desired output; and generating the output based the index value. An apparatus for performing the method is also disclosed herein.

Abstract: An embodiment of the invention is a circuit for adaptive phase noise cancellation for a fractional-N PLL. A preferred embodiment employs a split loop filter architecture. Two loop filter halves separately drive half-sized parallel varactors in a voltage controlled oscillator (VCO) and also drive a differential-input lowpass frequency selective circuit, e.g., a differential-input integrator in a least mean squared (LMS) feedback loop. The output of the differential-input lowpass frequency selective circuit controls the gain matching of a phase noise cancellation path to minimize phase noise arising from quantization error associated with the sequence of divider modulus values in the fractional-N PLL. The two varactor capacitances add together in the VCO tank, so the VCO frequency depends on the common-mode loop filter voltage and is relatively insensitive to differential-mode voltage.

Abstract: An oscillator control apparatus has a digitally-controlled oscillator which outputs an oscillation signal having an oscillation frequency in response to an oscillator adjusting signal, a counter which counts the oscillation signal and outputs a count in response to a reference signal in synchronism with the oscillation signal, a time-to-digital converter which calculates a phase difference between the oscillation signal and the reference signal, an adder which adds the count and the phase difference and outputs the added value as first phase information, a corrector which corrects the first phase information in response to a phase control signal for setting an oscillation frequency of the digitally-controlled oscillator when a time difference between a rising-up timing of the oscillation signal and a rising-up timing of the reference signal is less than a predetermined time, and outputs second phase information, and a filter for smoothing a difference between the phase control signal and the second phase info

Abstract: An apparatus for providing Phased-Locked Loop (PLL) synthesis comprises a phase detector, at least one switchable filter, an oscillator controlled by a control voltage (uPLL) and a divider. The controlled oscillator has two inputs, wherein the control voltage (uPLL) is coupled to a first input, and a selection voltage (uSET) for rough frequency adjustment is coupled to a second input. Both voltages establish the frequency of the oscillator.

Abstract: A digital apparatus for phase aligning output signals of a silicon device to an applied input clock signal in same device allows synchronization of data transfers between the device and another device such as a controller. It includes a digital or analog oscillator of higher frequencies than the applied clock and in multiples of powers 2n where n=1, 2, 4, etc., with provisions for synchronization and control by the applied input clock. The main oscillator frequency is subdivided to lower frequencies. An internally derived duplicate frequency clock is phase shifted by either 45 or 22.5 degrees. The system measure both a desired coarse delay, and a fine delay to be applied to the path to phase align the output signal to the phase of the applied input clock.

Abstract: A circuit, such as, but not limited to, a digital phase-locked loop (PLL) or a transport timing loop, uses a fractional-N modulator and a fractional-N clock synthesizer to generate a clock signal, such as a transmit clock signal, from a reference clock signal. One embodiment uses a recovered clock signal derived from serial received data as a positive input to a feedback loop, and uses the transmit clock signal as a negative input to the feedback loop. After digital phase detection and digital filtering, a filtered error signal s is generated and used to control a modified fraction for control of the fractional-N synthesizer. Disclosed techniques advantageously exhibit jitter attenuation and have relatively little jitter accumulation, which are useful characteristics in telecommunication and data communication network clocking applications. Embodiments can be applied to loop timing, clock regeneration, and transport timing applications, and can be used when clock holdover is desirable.

Abstract: A self-biased PLL includes a first charge pump and a second charge pump, an output terminal of the first charge pump is connected with a discharge-charge capacitor to output a control voltage, an output terminal of the second charge pump is connected with an output terminal of a bias generator for outputting a first bias voltage equal to the control voltage, wherein, a current output from the first charge pump is equal to a value obtained through dividing the production of a first constant with a bias current of a voltage control oscillator by a frequency division factor of a frequency divider; a current output from the second charge pump is equal to a value obtained through dividing the bias current of the voltage control oscillator by a second constant; and a multiple relation exists between an output resistance of the bias generator and an equivalent resistance of a differential buffer delay stage in the voltage control oscillator.

Abstract: A VCO circuit includes a temperature detector circuit, a voltage generator circuit, a switch, a resonance circuit and an oscillator. The temperature detector detects a temperature, and the voltage generator circuit generates a voltage for coarse adjustment corresponding to the detected temperature and outputs the same voltage. The switch selects one of a DC voltage for fine adjustment and the voltage for coarse adjustment. The resonance circuit includes a varactor diode having a capacitance value adjusted based on the voltage selected by the switch, capacitors and an inductor, and has a predetermined resonance frequency. The oscillator generates an oscillation signal having an oscillation frequency corresponding to the resonance frequency by using the resonance circuit and outputs the same signal.

Abstract: A digital PLL frequency synthesizer characterized by fast-locking and low-jitters is presented. The PLL comprises a phase detector, a controllable oscillator, a loop filter having an automatically-adjusted loop gain, a feedback phase integration circuit, and a reference phase integration circuit. Fast-locking is achieved by dynamically adjusting forward-path gain and integral-path gain according to the output of the phase detector and the output of the integral-path during phase tracking. A skew-compensated counter circuit is proposed, which incorporates an asynchronous counter, a data register and a sample phase generator and features high-speed and low-power operation.

Abstract: A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).

Abstract: The oscillating circuit (100) includes a variable frequency oscillating circuit (10) for generating a clock signal (CK) whose frequency increases in response to an up-signal (UP) and decreases in response to a down-signal (DOWN), the frequency going up and down continuously between an upper-limit frequency and a lower-limit frequency. An up/down control circuit (20) outputs the down-signal when a duration of a low level of the clock signal drops below a first delay time and outputs the up-signal when the duration exceeds a second delay time longer than the first delay time.

Abstract: A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.

Abstract: The present relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof.

Abstract: An object is to provide a PLL having a wide operating range. Another object is to provide a semiconductor device or a wireless tag which has a wide operating range in a communication distance or temperature by incorporating such a PLL. The semiconductor device or the wireless tag includes a first divider circuit; a second divider circuit; a phase comparator circuit to which an output of the first divider circuit and an output of the second divider circuit are provided; a loop filter to which an output of the phase comparator circuit is supplied and in which a time constant is switched in accordance with an inputted signal; and a voltage controlled oscillator circuit to which an output of the loop filter is supplied and which supplies an output to the second divider circuit.

Abstract: A technique involves the use of an electronic device having a real-time clock (RTC) circuit. In particular, the technique involves obtaining an RTC value from the RTC circuit. The RTC value is based on a previous time value and being arranged to represent current time. The technique further involves generating an adjustment factor arranged to adjust for imperfection in an oscillator of the RTC circuit, and providing a new time value based on the RTC value and the adjustment factor. The new time value represents current time at least as accurately as the RTC value.

Abstract: A signal generating circuit and method are disclosed that do not require a phase-locked-loop and a low frequency temperature-stable oscillator. The method may include generating an oscillating output signal responsive to a feedback signal, where the feedback signal controls a frequency of the oscillating output signal, generating a current output signal having a magnitude corresponding to the frequency of the oscillating output signal, and then comparing the current output signal to a reference signal to generate the feedback signal. The signal generating circuit may include an oscillator circuit responsive to a feedback signal and a frequency-to-current conversion circuit configured to generate a frequency dependent current signal that is compared to a reference current to generate an output signal corresponding to the frequency of the oscillating output signal. A feedback conversion circuit compares the output signal with a reference signal to generate the feedback signal to the oscillator circuit.

Abstract: A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.

Abstract: A delta-sigma fractional-N frequency synthesizer having a charge pump with error canceling circuitry eliminates a non-linear term from the charge pump transfer function. The charge pump includes a matched pair of charging current sources, each supplying a first current IP1 to a common node, when enabled. The charge pump also includes a matched pair of discharging current sources, each sinking a second current IN1 from the common node, when enabled. The error canceling circuitry includes a charging current source, which supplies a current equal to the second current IN1 to the common node, when enabled. The error canceling circuitry also includes a discharging current source, which sinks a current equal to the first current IP1 from the common node, when enabled. The charging and discharging current sources of the error canceling circuitry are both enabled when either one of the matched pairs of charging and discharging current sources is enabled.

Abstract: In one example, a method of tuning an oscillator of a phase-locked loop (PLL) circuit includes adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator. The method includes adjusting a fine control signal to select a position on the selected frequency tuning curve. A frequency of the oscillator is determined by the coarse control signal and the fine control signal. The method includes attempting to detect a lock between a feedback signal and a reference signal. A frequency of the feedback signal is determined by the frequency of the oscillator. The method includes comparing the fine control signal to a reference value if the lock is detected. The method includes adjusting the coarse control signal to select a different one of the frequency tuning curves if the selected position on the selected frequency tuning curve is outside a desired tuning range.

Abstract: The present invention provides a phase locked loop circuit including: a voltage controlled oscillator; a variable frequency-dividing circuit; a phase comparing circuit for comparing a phase of the frequency-dividing signal a charge pump circuit; a loop filter; a voltage supplying circuit; a frequency measuring circuit; and a voltage measuring circuit.

Abstract: A voltage-controlled oscillator (VCO) circuit includes a level shifter, and a semiconductor device includes the VCO circuit. The VCO circuit includes an input voltage receiver, a current mirror, and a frequency oscillator. The input voltage receiver receives a first voltage input to the VCO circuit so as to generate a first current. The current mirror copies the first current so as to generate a second current. The frequency oscillator oscillates in response to the second current. The input voltage receiver includes a level shifter and a first current generator. The level shifter shifts a voltage level of the first voltage to a voltage level of a second voltage. The first current generator generates the first current corresponding to the second voltage.

Abstract: A method for correcting time error in an oscillator operated clock according to one aspect of the invention includes at selected times determining at least one of a time error in the clock and a frequency difference between the oscillator and a reference oscillator by detecting a time reference signal. A change in the at least one of the time error and the frequency difference between a first one and a second one of the detecting the time reference signals is determined. A frequency of the oscillator is adjusted so as to substantially cancel a cumulative time error between the second one of the detecting the time reference signal and a selected detecting the time reference signal.

Abstract: An embodiment of the present invention is a technique for timing recovery. A frequency acquisition loop locks a voltage controlled oscillator (VCO) clock of a multi-band VCO to a reference clock. The frequency acquisition loop generates first and second feedback clocks from the VCO clock. A data lock phase loop generates a driving signal corresponding to a phase error signal from interleaved partial response signal (PRS) samples based on the second feedback clock. The driving signal controls the multi-band VCO in a data phase lock mode. A lock detect controller detects a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode based on the first feedback clock and the reference clock.

Abstract: An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.

Abstract: A phase lock loop (PLL) circuit is provided. A voltage controlled oscillator (VCO) generates an output clock signal based on a control voltage. A controller provides a first digital control word, a second digital control word and a loop factor. A frequency modifier is coupled to the output clock signal, controlled by the controller to divide the output clock signal by the loop factor to generate a feedback frequency. A charge pump is controlled by the up signal and down signal to generate a charge pump current, comprising a first digital to analog converter (DAC) to generate a first current based on the first digital control word when the up signal is asserted. A second DAC generates a second current based on a second digital control word when the down signal is asserted. The controller defines a first relationship between the first digital control word and the loop factor, and the controller defines a second relationship between the second digital control word and the loop factor.

Abstract: Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time.

Abstract: A systems and methods for providing phase lock conditions detection, such as a quality of phase lock and loss of lock detection, are described herein. One exemplary method comprises detecting an output frequency, comparing the output frequency with a first reference signal, providing a first signal and a second signal as a function of the output frequency and first reference signal comparison, receiving a predetermined threshold from a second reference signal, monitoring a deviation of the first and second signals from the predetermined threshold, generating a third signal as a function of the deviation, comparing the third signal to a window threshold wherein the window threshold is set based on a predetermined loop variable, generating a fourth signal a function of the third signal and the window threshold comparison, and providing an alarm based on the fourth signal.

Abstract: The invention relates to a method for carrying out a frequency change whilst retaining the phase relationship between several devices, in particular, network analyzers. Each device has at least one signal generator for stimulating an object for measurement and at least one local oscillator, connected to at least one mixer, for receiving a measuring signal obtained from the object for measurement by the superposition principle. On changing frequency, in a first step, only the frequency of the local oscillators of all devices is changed and the frequency of the signal generators of all devices remains unchanged. In a second step, only the frequency of at least one signal generator is changed and the frequency of the local oscillators of all devices remains unchanged.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: Disclosed is an oscillator including a reference voltage generator generating a reference voltage, and a logic combination circuit generating complementary first and second internal clock signals in response to the reference voltage and complementary first and second output voltages. One of the first and second output voltages—the one going high—is provided to the logic combination circuit before the other one of the first and second output voltages—the one going low.

Abstract: A receiver is provided. The receiver includes a differential amplifier amplifying differential input signals input to input terminals and outputting differential output signals through output terminals and an oscillator connected to the output terminals of the differential amplifier. The differential amplifier and the oscillator operate alternatively in response to an enable signal.

Abstract: Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter.

Abstract: The present invention relates to a mixed mode electronic circuit that implements a PLL cell that employs an auto-range algorithm to lock to a wide range of input reference signals.

Abstract: In a voltage-controlled oscillator capable of broadening a variable frequency range while suppressing increase of conversion gain, a converter (12) converts an input voltage to a first physical quantity, a variable converter (13) supplies a second physical quantity that accords with the status of each switch of a switch group (13a). another variable converter (14), when the input voltage is contained within a prescribed voltage range, supplies a third physical quantity that accords with the input voltage and the status of each switch of another switch group (14a), and a variable-frequency oscillator (15) supplies a signal of a frequency that accords with the first physical quantity, the second physical quantity, and the third physical quantity.

Abstract: A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below ?80 dBc.

Abstract: An apparatus for implementing a digital phase-locked loop includes a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control voltage. Detection means generates counter control signals, including count up signals and count down signals, to indicate a current relationship between the primary clock signal and a reference signal. An up/down counter then either increments or decrements a counter value in response to corresponding counter control signals. The counter value is then converted by a digital-to-analog converter into the VCO control voltage for adjusting the frequency of the primary clock signal generated by the voltage-controlled oscillator. In alternate embodiments, the foregoing up/down counter may be utilized to adjust the frequency of the voltage-controlled oscillator in proportion to the counter value by utilizing appropriate techniques other than generating a VCO control voltage with a digital-to-analog converter.

Abstract: The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency or set of frequencies and a predetermined amplitude. The energizing signal is coupled to the sensor via magnetic coupling and induces a current in the sensor which oscillates at the resonant frequency of the sensor. The system receives the ring down response of the sensor via magnetic coupling and determines the resonant frequency of the sensor, which is used to calculate the measured physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal.

Abstract: A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.

Abstract: A broadband frequency synthesizer including a VCO for supplying a high frequency output signal, a dual mode divider circuit, a means for selecting a division mode of the divider circuit, a phase detector and a low pass filter. The divider circuit divides the frequency of the output signal by a first division facto N1 in a first mode M1or by a second factor N2 different from the first factor N1 in a second mode M2 to provide the divided frequency signal (Fdiv). The selection means selects by determined time period the first or second division mode of the divider circuit as a function of the programmed frequency of the output signal in the frequency band defined by the first and second division factors N1 and N2. If this frequency is dose to the center of the frequency band, the dual mode divider divides the output signal frequency by a third factor N3 in a first mode M1 or by a fourth division factor N4. different from N3, in a second mode M2 according to the programming of the selection means.

Abstract: A frequency phase correction system and method are described that provides a receiver with a greater ability to lock onto relatively weak radio frequency signals by determining and estimating an amount of frequency error in a local frequency reference of the receiver, and using the error estimate to maintain frequency coherence with a received signal, thereby allowing tracking over a longer period of time, enabling longer integration times to capture weaker signals without losing frequency coherence.

Abstract: Provided is a low voltage frequency synthesizer using a boosting method for a power supply voltage of a charge pump. The low voltage frequency synthesizer includes a phase/frequency detector (PFD) that receives and compares a reference frequency and a feedback frequency to output a comparison signal, a charge pump that receives the comparison signal to output a current corresponding to the comparison signal, a low-pass filter (LPF) that generates a voltage corresponding to the output current of the charge pump, a voltage controlled oscillator (VCO) that receives the voltage of the LPF, amplifies the voltage to generate a boosting voltage, and outputs a frequency corresponding to the received voltage, and a DC converter that receives the boosting voltage of the VCO, converts the boosting voltage into a DC voltage, and applies the DC voltage as a power supply voltage of the charge pump.

Abstract: Circuits and methods for automated real-time tuning of wide range frequency/delay voltage controlled oscillators (VCO) using a reset mechanism, to account for run-time variations such as power supply, temperature, reference clock frequency and input slew drift etc is described. It finds extensive applications in wide range, multi frequency band phase and delay locked loops. In one embodiment, an automated Jump-Down band switching structure and method for use in VCOs with a plurality of frequency bands is described. This involves monitoring the VCO's analog control voltage signal until it reaches a predetermined lower limit, at which time band switching to an overlapping lower frequency band is triggered by an internally generated reset signal, while simultaneously charging the analog control voltage to a limit in a pre-determined range of the lower band, to avoid phase detector malfunctions in the PLL/DLL system at lower control voltages during band switch.

Abstract: Methods and apparatus for calibrating the VCO element of a phase-locked loop to correct for non-linearities are disclosed. The modulation port of the VCO may be characterized to generate a tuning model, which may then be used to generate a correction signal to be combined with an input signal and applied to the VCO modulation port. The tuning model may be based on a third or higher order polynomial generated from a plurality of open-loop frequency measurements of the VCO.

Abstract: This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information.

Abstract: Adjusting a local frequency source is disclosed. A local frequency comparison data is compared with a received frequency comparison data, wherein the local frequency comparison data reflects a difference, if any, between a locally measured AC frequency and a frequency generated using the local frequency source. The local frequency source is adjusted based at least in part on a result of the comparison.

Abstract: A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector.

Abstract: The present invention discloses a two-step VCO calibration method. The two-step VCO calibration method, comprising power-on calibration, used to provide a coarse VCO tuning; real-time calibration, used to provide a fine VCO tuning according to the loaded result of said power-on calibration. The two-step VCO calibration method according to the present invention can cover all the variation of process and temperature and gain the advantages of shorter calibration time, smaller gain of VCO, pretty smaller size of passive loop filter and less operating power consumption.

Abstract: In a PLL circuit, an oscillation frequency is quickly and accurately locked to a target frequency. There is provided a PLL circuit, including a VCO that controls the frequency of an output signal according to a voltage of an input signal, a loop divider that divides the frequency of a signal, which is acquired by causing a mixer to mix a local signal generated by a local oscillator and the output signal with each other, by N, and a reference frequency divider that divides the frequency of a reference signal, which is output by a reference signal oscillator, by R.