Abstract: A fully connected ring oscillator circuit includes a plurality of first ring oscillator loops, a plurality of second ring oscillator loops, a plurality of ring oscillators and a plurality of coupled ring oscillators. Each first ring oscillator loop extends along a first axis. Each second ring oscillator loop extends along a second axis that is transverse to the first axis and intersects each of the first ring oscillator loops. Each ring oscillator includes one of the first ring oscillator loops connected to one of the second ring oscillator loops. Each coupled ring oscillator includes two of the ring oscillators that are connected to each other through a programmable weighted coupling block.

Abstract: In a first and second embodiment, an apparatus and system comprising a set of voltage controlled oscillators (VCOs); wherein each VCO of the set of VCOs has an LC tank; wherein each VCO of the set of VCOs is connected via a transmission line. In a third embodiment, a method comprising connecting each VCO in a set of VCOs by connecting each respective LC tank of each VCO of the set of VCOs with a transmission line.

Abstract: A set and reset pulse generator circuit receives an input signal to generate a set signal and a reset signal pair. The set and reset pulse generator circuit includes a set circuit and a reset circuit. A cross-coupling circuit connects a voltage signal of the reset circuit to an output circuit of the set circuit, and another cross-coupling circuit connects a voltage signal of the set circuit to an output circuit of the reset circuit. The output circuit of the set circuit generates the set signal from the input signal, the voltage signal of the reset circuit, and the voltage signal of the set circuit. The output circuit of the reset circuit generates the reset signal from an inverted input signal, the voltage signal of the reset circuit, and the voltage signal of the set circuit.

Abstract: An apparatus is provided to improve lock time of a phase locked loop, wherein the apparatus comprises: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multiphase frequency monitor coupled to the ring oscillator to monitor frequency at an output of at least two delay stages of the ring oscillator.

Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.

Abstract: A LoRa receiver for processing digital chirp spread-spectrum modulated signals with an advanced module for the determination of the timing error and/or of the frequency error arranged to estimate a position of a frequency discontinuity in each symbol, extract one or more frequency-continuous fragments out of each symbol, dechirp the coherent fragments, determine a timing error, and/or a frequency error, and/or a modulation value, and/or a SNR.

Abstract: According to the embodiment discloses a method providing direct RF sampling of the received signal in a full duplex system. A sampler in the full-duplex system comprises a buffer to clip an amplitude information from each of a coupled transmitter (Tx) signal and a voltage at an antenna port of the sampler for obtaining a buffered transmitter signal and a buffered voltage at the antenna port. Phase detector in the sampler is configured to perform sampling of time delay between the buffered transmitter signal and the voltage at the antenna port and generate an output. The sampler further comprises current integrator configured to pass the output of the phase detector for generating a sampled output, wherein the sampled output generates an output received signal.

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

Abstract: A lock detection circuit is configured to include an integrating circuit that integrates a phase difference between a frequency-divided signal of a VCO and a reference signal during a constant period within a transient response period for an output signal from the VCO, and integrates a phase difference between the frequency-divided signal and the reference signal during a constant period within a convergence period for the output signal from the VCO; and a degree-of-convergence calculating circuit that calculates a degree at which the output signal from the VCO has converged, from a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the transient response period and a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the convergence period.

Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscillation signal. A frequency accuracy of the first oscillator is higher than a frequency accuracy of the second oscillator. Further, an oscillator phase noise of the second oscillator is lower than an oscillator phase noise of the first oscillator. The apparatus further includes a processing circuit configured to generate a third reference oscillation signal based on the first reference oscillation signal and the second reference oscillation signal. Additionally, the apparatus includes a phase-locked loop configured to generate the oscillation signal based on the third reference oscillation signal. A frequency of the oscillation signal is a multiple of a frequency of the third reference oscillation signal.

Abstract: Methods and systems for predicting deterioration of a patient's condition within a future time interval based on a time series of values for monitored physiological variables measured from a patient, and in some instances, providing advanced notice to clinicians or caregivers when deterioration is forecasted or modifying treatment for the patient are provided. In particular, deterioration of a patient's condition is based on a Hopf bifurcation model and is predicted using a ratio of deviations for monitored physiological variables. A ratio of deviations relates the standard deviation and root mean square of successive differences for a set of physiological values measured over time. The RoD for one or more variables, such as heart rate, respiratory rate, and blood pressure, may be used to predict the likelihood of the patient's condition deteriorating into an unstable state as what occurs in a Hopf bifurcation.

Abstract: A voltage controlled oscillator (VCO) is described. The VCO includes a plurality of nodes coupled with a plurality of transistors, and a first inductor-capacitor (LC) tank coupled with a second LC tank. The first LC tank and the second LC tank include a shared inductor structure coupled to the plurality of nodes. The first LC tank and the second LC tank each include a capacitor. The capacitors are each coupled on a first side to a node of the plurality of nodes and on a second side to a respective capacitor in the other LC tank. The first LC tank and the second LC tank are configured to resonate at a fundamental frequency for differential-mode signals, and the first LC tank and the second LC tank are configured to resonate at twice the fundamental frequency for common-mode signals.

Abstract: Systems and methods for providing a non-rewritable code comparator using a memristor and a serial resistor are disclosed. An example apparatus comprises: a plurality of first terminals; a plurality of second terminals; and a plurality of two-terminal device pairs formed between the plurality of first terminals and the plurality of second terminals. Each two-terminal device pair in the plurality of two-terminal device pairs include at least one memristor and at least one resistor; each two-terminal device pair is configured to be switched to a subsequent state once and only once. In some implementations, a two-terminal device pair is configured to remain in the subsequent state regardless of whether an input signal to the apparatus matches a reference signal to the apparatus.

Abstract: A monitor circuit is configured to receive sensor data samples at a first bit rate. The monitor circuit includes a sensor data processing circuit that is coupled to a sensor node and is configured to generate a sensor data characteristic signal for each sensor data sample. The sensor data characteristic signal for a particular sensor data sample indicates a value of a monitored parameter of the particular sensor data sample. The monitor circuit also includes a fault trigger circuit configured to determine, based on the sensor data characteristic signal, whether the sensor data samples satisfy a fault trigger. The monitor circuit further includes a summarization circuit configured to generate a sensor data summary signal based on the sensor data characteristic signal. The sensor data summary signal is provided to a summary output node at a second bit rate that is less than the first bit rate.

Abstract: Provided is an oscillator including: a first resonator; a second resonator; a first oscillation circuit generating a first oscillation signal by oscillating the first resonator; a second oscillation circuit generating a second oscillation signal that has frequency-temperature characteristics different from frequency-temperature characteristics of the first oscillation signal by oscillating the second resonator; a clock signal generation circuit generating a clock signal with a frequency that is temperature compensated by temperature compensation data; a storage unit storing information on a learned model that is machine-learned to output data corresponding to the temperature compensation data with respect to input data; and a processing circuit obtaining the temperature compensation data by performing processing based on the information on the learned model with respect to the input data based on the first oscillation signal and the second oscillation signal.

Abstract: An oscillator circuit includes a first oscillator, a second oscillator, and a calibration circuit to calibrate the first and second oscillators. The first oscillator is supplied with a first supply voltage, and the second oscillator is supplied with a second supply voltage. The calibration includes setting a frequency control of the second oscillator at a target frequency. Then, a voltage control of the second supply voltage is adjusted incrementally until a first control value is identified at which a second oscillator output frequency matches the target frequency. Then, a voltage control of the first supply voltage is set to the first control value. Then, the voltage control for the first supply voltage is adjusted incrementally until a second control value is identified at which a first oscillator output frequency is as close to the second oscillator output frequency as is achievable, but does not exceed it.

Abstract: A performance calculation method suitable for a chip is provided. The chip includes oscillator circuit systems configured to generate oscillation signals and to sense operation states of the chip to adjust periods of the oscillation signals. The method includes following operations: when the chip is in a first operation state, constructing a first function according to the periods of the oscillation signals and a first performance value of the chip; when the chip is in a second operation state, constructing a second function according to the periods of the oscillation signals and a second performance value of the chip; adjusting coefficients of the first or second function according to trajectories of graphs of the first and second functions, so that the graphs of the first and second functions intersect at a coordinate point; constructing a performance function of the chip according to the first and second functions.

Abstract: Methods and systems for generating oscillatory timbres for musical synthesis through synchronous ring modulation are described. An example method performing hard synchronization comprising using first and second oscillators, the first oscillator being a fundamental oscillator which provides a fundamental frequency, the second oscillator being a modulation oscillator operable at a frequencies higher than the first oscillator; and in response to the fundamental oscillator completing its cycle, synchronizing the modulation oscillator to the original point of its waveform. Ring modulation may be performed on the synchronized output by multiplying it by a waveform of the fundamental oscillator, such that the ring modulation is synchronized to produce a variety of oscillatory timbres. The method can create a variety of unique sounds having musically pleasing characteristics. A real-time audio signal can be used instead of the first oscillator to produce dynamically varying timbres.

Abstract: An example of a device for generating a broadband frequency signal comprises a first controlled oscillator, a second controlled oscillator, a phase-locked loop for feeding back an output signal of a controlled oscillator to the corresponding controlled oscillator, and a mixer. The mixer is configured to generate the broadband frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator. The device may, for example, be realized by means of a single phase-locked loop. A further example relates to a device for generating a frequency signal with a controlled oscillator and a phase-locked loop with a further controlled oscillator and a mixer in the feedback path of the phase-locked loop. Examples further relate to a high-frequency device for emitting a high-frequency signal and a method for generating a broadband frequency signal.

Abstract: A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillators, a second phase acquisition circuit coupled to the input for the reference clock source and to the second crystal oscillator, a first DPLL coupled to the first phase acquisition circuit, a crystal oscillator variation estimator coupled to the first DPLL, a second DPLL coupled to the second phase acquisition circuit and including a phase-frequency detector having a input coupled to the second phase acquisition circuit, a loop filter, a frequency subtractor having an input coupled to the loop filter and an input coupled to the crystal oscillator variation estimator, and a DCO coupled to the frequency subtractor and driving an input of the phase-frequency detector.

Abstract: An apparatus is provided which comprises: a first ring oscillator comprising at least one aging tolerant circuitry; a second ring oscillator comprising a non-aging tolerant circuitry; a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator; a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator; and logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices.

Abstract: A signal identification system includes an analog adaptive channelizer having a plurality of channels. Each channel has a channel size defined by a bandwidth and a gain. The system further includes an electronic signal identification (ID) controller in signal communication with the analog adaptive channelizer. The ID controller is configured to determine a dynamic range event that modifies an energy level of an affected channel among the plurality of channels, and output a feedback signal including channel parameters based on the dynamic range event. The analog adaptive channelizer actively adjusts at least one of the bandwidth and the gain of the affected channel based on the feedback to change the channel size of the affected channel.

Abstract: A method of quickly locking a locked loop includes generating an intermediate reference signal having an intermediate reference frequency between a desired output frequency and a reference frequency of a reference signal, and setting an output frequency of a controllable oscillator to the desired output frequency using a first locked loop having a first loop divider value. The first loop divider value is set such that the intermediate reference frequency multiplied by the first loop divider value is equal to the desired output frequency. The controllable oscillator is then coupled to a second locked loop when the first locked loop locks, with the second locked loop is being activated. The first locked loop is then deactivated.

Abstract: Exemplary embodiments of the present disclosure relate to a clock distribution network for a scan design, which may include, for example, a clock signal network(s), and a plurality of partitioned clock signal networks coupled to the clock signal network(s) through a controlling logic(s); where the controlling logic(s) may be configured to stagger a clock signal from the clock signal network(s), and where each of the partitioned clock signal networks may be connected to a group of flip-flops. A first partitioned clock signal network of the partitioned clock signal networks may be connected to a first group of flip-flops and a second partitioned clock signal network of the partitioned clock signal networks may be connected to a second group of flip-flops, and where the first group of flip-flops may be different than the second group of flip-flops. The controlling logic(s) may include a shift register(s).

Abstract: A method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate a loop filter output signal. The feedback clock signal is based on the loop filter output signal. The method includes transitioning a frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency responsive to detection of a catastrophic cycle slip event in the absence of an out-of-frequency event.

Abstract: A method is provided for managing a number of active wireless data streams in a device. An operating band of the device is detected, wherein the device is capable of simultaneously supporting Wi-Fi and Bluetooth communications by time sharing the operating band between the Wi-Fi and Bluetooth communications. A request is detected for simultaneously operating in at least two of a Wi-Fi communication mode, a Bluetooth source communication mode, or a Bluetooth sink communication mode. In response to detecting the request, only two of the Wi-Fi communication mode, the Bluetooth source communication mode, or the Bluetooth sink communication mode are selected.

Abstract: A differential phase and amplitude detector circuit is presented. Two source follower circuits respectively based on NMOS and PMOS transistors are used to charge and discharge a sampling capacitor asymmetrically to provide a measurement of phase and/or amplitude difference between two signals of a substantially same frequency. The measurement can be made in one cycle, with the charging of the sampling capacitor performed during a first half cycle where a voltage difference between the two signals is positive, and the discharging during a second half cycle where a voltage difference between the two signals is negative. Biasing of the two source follower circuits enable an excess current flow between the two transistors of the two source follower circuits beyond a biasing current of the transistors to charge the sampling capacitor during the first half cycle, and disable the excess current flow between the two transistors during the second half cycle.

Abstract: A system, method and circuits are described that pertain to locked loop circuits, distributed duty cycle correction loop circuitry. In some embodiments, the system and circuit may involve or be configured for coupling with lock loop circuitry such as phase locked loop (PLL) circuitry and/or a delay locked loop (DLL) circuitry. For example, one illustrative implementation may include or involve a phase locked loop (PLL) with distributed duty cycle correction loop/circuitry.

Abstract: An exemplary embodiment of the present disclosure provides a reference clock signal generation method for a memory storage device. The method includes: receiving a first type signal from a host system; generating a first control parameter according to a frequency of the first type signal; receiving a second type signal from the host system after the first type signal is received; generating a second control parameter according to a frequency of the second type signal; and generating a reference clock signal meeting a first condition according to the second control parameter. Therefore, an efficiency of generating the reference clock signal can be improved.

Abstract: A clock generator includes a hermetically sealed cavity and clock generation circuitry. A dipolar molecule that exhibits a quantum rotational state transition at a fixed frequency is disposed in the cavity. The clock generation circuitry is configured to generate an output clock signal based on the fixed frequency of the dipolar molecule. The clock generation circuitry includes a detector circuit, a multiplier, and reference oscillator control circuitry. The detector circuit is coupled to the cavity, and is configured to generate a detection signal representative of an amplitude of a signal at an output of the cavity. The multiplier is coupled to the detector circuit, and is configured to multiply the detection signal with a mixing signal to produce a derivative of the detection signal. The reference oscillator control circuitry is configured to set a frequency of a reference oscillator based on the derivative of the detection signal.

Abstract: A signal generating circuit includes a control voltage setting unit (CVSU) configured to set a control voltage for a chirp signal using voltage-frequency characteristics indicating characteristics of an output frequency versus voltage; a VCO configured to alter the frequency of its output signal by the control voltage; a quadrature demodulator configured to perform quadrature demodulation of the output signal of the VCO to generate an inphase signal and a quadrature signal orthogonal to each other; and a frequency detector configured to detect the frequency of the output signal of the VCO on the basis of the inphase signal and quadrature signal. The CVSU corrects the control voltage by using the voltage-frequency characteristics derived from relationships between the control voltage and the frequency of the output signal of the VCO. The VCO generates the chirp signal based on the control voltage corrected by the CVSU.

Abstract: Systems and methods for controlling phase or delay in multi-channel radio frequency applications. The system includes a local oscillator, a frequency generator, a clock buffer, a plurality of mixers and a plurality of filters. The frequency generator generates an intermediate frequency output signal which can be received by the clock buffer. The clock buffer creates multiple phase-adjusted reference frequency signals that are each different in phase. A local oscillator generates a plurality of local oscillator signals having the same frequency and phase. A plurality of mixers produce a plurality of RF signals based at least in part on the plurality of local oscillator signals and the plurality of phase-shifted reference frequency signals.

Abstract: A function generator provides a first signal unit for the delivery of a first signal at a first output. The function generator provides a second signal unit for the delivery of a second signal at a second output. The function generator provides a calibration unit for the generation of a test signal, wherein the test signal can be supplied to the first signal unit and/or to the second signal unit. A comparison unit is connected downstream of the first signal unit and/or the second signal unit. The comparison unit compares the test signal delivered at the first output and/or at the second output with a calibration signal, wherein the output signal of the comparison unit can be supplied to the calibration unit.

Abstract: A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.

Abstract: A data output device includes: a first serializer suitable for receiving first parallel data having a first size from a first data line, and selectively outputting first and second serial data each having a second size corresponding to ½ of the first size; a second serializer suitable for receiving second parallel data having the first size from a second data line, and selectively outputting third and fourth serial data each having the second size; and a latch circuit suitable for latching the output of the first serializer and the output of the second serializer, and outputting serial output data having the first size.

Abstract: A technique for cancelling or reducing crosstalk signals between controlled oscillators in an integrated circuit is provided. The technique involves an arrangement adapted to reduce a crosstalk signal generated by a first controlled oscillator to a second oscillator both comprised in the integrated circuit, wherein both controlled oscillators are configured to output a respective clock signal. The arrangement comprises a detector adapted to detect the crosstalk signal generated by the first controlled oscillator to the second controlled oscillator, a crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal, and a cancellation signal injector adapted to introduce the cancellation signal into the second controlled oscillator.

Abstract: A computing device includes an oscillator network and a controller. The oscillator network includes a plurality of oscillators coupled to each other. The controller is configured to control the oscillator network. Each of the oscillators has a nonlinear energy shift. The controller performs a plurality of sampling operations. Each sampling operation includes a first operation of outputting a signal causing the oscillators to stop oscillating, a second operation of outputting a signal causing the oscillators to oscillate based on a parameter relating to a first probability distribution, and a third operation of outputting a signal to measure, for the oscillators, a phase of an electromagnetic wave generated by an oscillation.

Abstract: A system includes: a unit configured to communicate a modulated signal via a signal interface; and at least one additional unit configured to receive the modulated signal from the unit. The at least one additional unit includes circuitry configured to remove jitter from a recovered clock signal to generate a jitter reduced clock signal that tracks long-term drift in the modulated signal, wherein the at least one additional unit is configured to generate the recovered clock signal from the modulated signal.

Abstract: An interface circuit for a sensor including: a first injection-locked oscillator having: a first input coupled to a sensor, a free-running oscillation frequency of the first injection-locked oscillator being controlled by a signal from the sensor; and a second input coupled to receive a synchronization signal at a reference frequency, the first injection-locked oscillator being adapted to generate an output signal at said reference frequency, the output signal being phase shifted with respect to the synchronization signal as a function of the signal from the sensor.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: A clock generating circuit is operated in a phase-locking mode to generate an output clock signal having a first frequency that is phased-locked with respect to a variable-frequency input clock signal. After a frequency transition in the input clock signal, phase-locking is disabled within the clock generating circuit to transition the output clock signal from the first frequency to a second frequency that lacks phase-alignment with the input clock signal, then a frequency-lock range of the clock generating circuit is adjusted to transition the output clock signal from the second frequency to a third frequency that also lacks phase alignment with the input clock signal. After adjusting the frequency-lock range of the clock generating circuit, phase-locking is re-enabled therein to transition the output clock signal from the third frequency to a fourth frequency that is phase-aligned with the variable-frequency input clock signal.

Abstract: Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.

Abstract: Method and apparatus for generating a jitter reduced clock signal from signal transmitted over a communication medium includes receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream. A recovered clock signal is generated from the modulated signal and tracks the long-term drift in the modulated signal. A jitter reduced clock signal is generated by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal.

Abstract: A method to perform convolutions between arbitrary vectors includes estimating a first degree of match for a difference between a first vector having a plurality of first elements and a second vector having a plurality of second elements using a first cluster of coupled oscillators, estimating a second degree of match for the first vector using a second cluster of coupled oscillators, estimating a third degree of match for the second vector using a third cluster of coupled oscillators, deriving a first squared L2 norm from the first degree of match, deriving a second squared L2 norm from the second degree of match, deriving a third squared L2 norm from the third degree of match, adding the second squared L2 norm and the third squared L2 norm, and subtracting the first squared L2 norm to form a sum, and dividing the sum by two.

Abstract: In a clock generating circuit having a plurality of injection-locking oscillators, a first one of the injection-locking oscillators is enabled to output a free-running reference clock signal and a control value is generated based at least in part on a frequency relationship between the free-running reference clock signal and an input timing signal. In accordance with the control value, a selected one of the injection-locking oscillators is enabled to generate an output clock signal that is frequency-locked with respect to the input timing signal.

Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Abstract: A circuit includes a coupling structure and a first inductive device. The coupling structure includes two or more conductive loops and a set of conductive paths electrically connecting the two or more conductive loops. The first inductive device is magnetically coupled with a first conductive loop of the two or more conductive loops.

Abstract: An electronic circuit includes a first oscillator, a second oscillator and ancillary circuitry. The first oscillator is configured to generate a first clock signal and has a first wake-up delay. The second oscillator is configured to generate a second clock signal and has a second wake-up delay that is shorter than the first wake-up delay. The ancillary circuitry is configured to provide the second clock signal as an output clock signal during wake-up of the first oscillator, and, following the first wake-up delay, to provide the first clock signal as the output clock signal.

Abstract: A communication system for an organization having multiple sites uses a dual-mode device capable of both cell phone communication and telephone communication on a local area network (LAN). IP LANS are established at organization sites such that a temporary IP address is assigned to a dual-mode device that logs onto an organization LAN, and the IP address is associated at a PSTN-connected server on the LAN with the cell phone number of the communication device. The IP server notifies a PSTN-connected routing server when a device logs on to a LAN, and also provides a destination number for the IP server. Cell calls directed to the device are then redirected to the IP server and directed to the device connected to the LAN.