Abstract: An electronic device has two oscillators, for example a first highly accurate crystal oscillator and a second less accurate low power oscillator. In a normal mode of operation, time is counted based on an output from the crystal oscillator, but in a low power mode of operation, time is counted based on an output from the less accurate oscillator. During the low power mode of operation, a calibration process is performed repeatedly. During a first calibration time period the second oscillator is calibrated against the first oscillator to obtain a first calibration result, and a recalibration is performed during a second calibration time period to obtain a second calibration result. A correction factor is determined from the first and second calibration results, and the correction factor is applied when subsequently counting time based on the output from the second oscillator.

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract: The invention discloses a dual frequency multiplexer by which a first and second coaxial harmonic oscillator type band pass filters are disposed in a box. The box includes a base body, a cover plate and a cover body. The two coaxial harmonic oscillator type hand pass filters are located on the base body and spaced each other by a metal plate; the multiplexer port, first and second ports are positioned on lateral side of the base body. The blocking capacitors are contained in the coaxial chamber of the two coaxial harmonic oscillator type band pass filters. The cover plate is secured on the base body; the first and second direct current circuits are placed on the cover plate; the low pass filters of the first and second direct current circuits are fixed on an edge of a top surface of the coaxial chamber by means of a support member; the cover body and the base body are fastened with each other. The blocking capacitors each are of distributed parameter capacitor.

Abstract: In described embodiments, a wide toning-range (WTR) inductive-capacitive (LC) phase locked loop (PLL) provides for a large range of differing oscillation frequencies with a set of individual LC voltage controlled oscillator (VCO) paths. The output of each individual wide range LCVCO path is provided to a multiplexor (MUX), whose output is selected based on a control signal from, for example, a device controller. Each of the set of individual wide range LCVCO paths includes a switch that couples the LCVCO to a loop filter of a voltage tuning module, wherein each switch also receives the control signal to disable or enable the LCVCO path when providing the output signal from the MUX. Each switch is configured so as to minimize leakage current drawn by the LCVCO when disabled, and to reduce or eliminate effects of input capacitance of each dormant LCVCO to the loop dynamics of the PLL.

Abstract: A semiconductor integrated circuit includes: digitally controlled oscillators; a phase-data output unit; an integration processing unit; a filter unit; a multiplier (a first multiplier) that outputs, as an oscillator tuning word, a value obtained by multiplying an output signal subjected to time division from the filter unit with a predetermined coefficient; and an output selector (a tuning-word separating unit) that allocates the oscillator tuning word to the digitally controlled oscillators in synchronization with a reference frequency.

Abstract: An analog-to-digital converter (ADC) suitable for measuring on-die DC or low frequency analog voltages may include a ring oscillator having a group of circuit cells successively and circularly coupled. Under certain circumstances, the ring oscillator may produce an output frequency that corresponds substantially linear to the input voltage. Other embodiments may be disclosed or claimed.

Abstract: A circuit includes an oscillator circuit including a first oscillator and a second oscillator. The first and the second oscillators are configured to generate signal having a same frequency and different phases. A transmission line is coupled between the first and the second oscillators.

Abstract: A quadrature oscillator includes a first oscillator having a first second-order harmonic node, a second oscillator having a second second-order harmonic node, and at least one capacitor coupling the first second-order harmonic node and the second second-order harmonic node. The first oscillator is configured to supply an in-phase signal and the second oscillator is configured to supply a quadrature signal.

Abstract: A radio circuit may be driven by a high frequency oscillator such as a crystal oscillator that may have sleep and wake time intervals. The sleep time interval length may be adjusted. A low frequency oscillator or low power oscillator (LPO) that may experience frequency drift may regulate the sleep and/or wake time intervals. The frequency drift may be detected based on two or more LPO calibrations and/or one or more clock adjustments. The LPO frequency drift may be detected based on an LPO frequency sampled after a first LPO calibration and a corresponding LPO clock adjustment, a second LPO frequency sampled after a second LPO calibration and a time interval between the two frequency samples. The LPO may be calibrated based on the HFCXO output. Sleep time intervals may be adjusted by adding and/or subtracting a time interval to an expected time to wake the radio circuit.

Abstract: In one embodiment, a circuit comprises a first inductor-capacitor based voltage-controlled oscillator (LCVCO) generating a first periodic signal with a first frequency and a first phase and a second LCVCO generating a second periodic signal with a second frequency and a second phase, and the second phase is offset relative to the first phase by a 90 degrees offset.

Abstract: A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.

Abstract: Provided is an oscillation device capable of obtaining a stable oscillation frequency by compensating for a change in oscillation frequency caused with an elapse of operating time of a quartz-crystal oscillator. A difference value ?F between a frequency difference between first and second quartz-crystal oscillators after a predetermined period of time has elapsed from a reference time and a frequency difference between the first and second quartz-crystal oscillators at the reference time is determined.

Abstract: A wideband oscillation circuit outputting oscillation signals (divided signals) of continuous frequencies is disclosed and the wideband oscillation circuit includes an oscillator that outputs an oscillation signal, a filter that filters the oscillation signal output from the oscillator and outputs an injection locked signal, and an injection locked frequency divider that performs a free-run operation and outputs a divided signal of the oscillation signal while its oscillating operation is regulated by the injection locked signal, the division ratio of which varies in accordance with a control signal, wherein the filter generates the injection locked signal by controlling the passing characteristic that caused the oscillation signal to pass with respect to time in accordance with a filter control signal locked with the divided signal.

Abstract: A single side band (SSB) mixer includes an in-phase SSB mixer unit and a quadrature-phase SSB mixer unit. The in-phase SSB mixer unit generates an in-phase output current, and includes a first transformer load in which a portion of a quadrature-phase output current flows. The quadrature-phase SSB mixer unit generates the quadrature-phase output current, and includes a second transformer load in which a portion of the in-phase output current flows. The SSB mixer may be used in a wide frequency band without degrading frequency selectivity.

Abstract: A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Abstract: To perform, in an oscillation device compensating an output frequency based on a detection result of ambient temperature, temperature compensation of the output frequency with high accuracy. First and second quartz-crystal oscillators are structured by using a common quartz-crystal piece, and when oscillation outputs of first and second oscillation circuits respectively connected to these quartz-crystal oscillators are set to f1, f2, and oscillation frequencies of the first and the second oscillation circuits at a reference temperature are set to f1r, f2r, respectively, a frequency difference being a difference between a value corresponding to a difference between f1 and f1r and a value corresponding to a difference between f2 and f2r is treated as a temperature at that time. Further, based on the frequency difference, a frequency compensation value is determined through polynomial approximation.

Abstract: A clock and data recovery circuit is disclosed and comprises a gated voltage-controlled oscillator (GVCO), a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop (DDFF). The GVCO receives a data signal and a reference voltage to generate first and second clock signals. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the first and second clock signals at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The DDFF receives the output signals from the matching circuit and the multiplexer, and outputs a recovered data signal.

Abstract: A frequency source and a method of frequency generation employ a memristive negative differential resistance (M-NDR) voltage controlled oscillator (VCO). The frequency source includes a first M-NDR VCO of a plurality of memristive VCOs to provide a first signal having a first signal frequency. The frequency source further includes a second M-NDR VCO of the plurality to provide a second signal having a second signal frequency. The first and second M-NDR VCOs are interconnected with the plurality of memristive VCOs. The first and second M-NDR VCOs have independent programmable states and are connected to a common output of the frequency source. The method includes providing an M-NDR VCOs, where each M-NDR VCO includes an M-NDR device connected in parallel with a capacitance, and applying a bias voltage to activate a selected M-NDR VCO of the plurality to produce a frequency output.

Abstract: An object is to provide a method for preventing the occurrence of variations in time resolution by providing a calibration process to a TDC at the time of start up and further preventing the increase in circuit scale by reducing the redundancy of delay elements. A calibration of a multiphase oscillator TDC and a vernier TDC is carried out at the time of power-on. In the calibration, a timing input to be input to the vernier TDC is selected from output signals of DCCO based on a reference clock. Also, data is defined as an output signal which is adjacent to the output signal of DCCO mentioned above and proceeds in phase, and the delay therebetween is derived. By repeating it to all of the output signals, the one cycle of the output signal of DCCO is derived.

Abstract: The present invention provides an array of tunable, injection-locking oscillators which are scalable to higher frequencies and measure the entire relevant frequency space simultaneously. The scalable, highly-parallelized, adaptive receiver architecture uses arrays of tunable, injection-locking nonlinear oscillator rings for broad spectrum RF analysis. Three separate and different microelectronic circuit configurations, each having a different type of readout, are described. The embodiments are designed to be incorporated as a subsystem in any type of powered system in which a fast image of the broader spectrum is valuable, when no information about the location of signals in the frequency space is predictable or forthcoming.

Abstract: A frequency source and a method of frequency generation employ a memristive negative differential resistance (M-NDR) voltage controlled oscillator (VCO). The frequency source includes a first M-NDR VCO of a plurality of memristive VCOs to provide a first signal having a first signal frequency. The frequency source further includes a second M-NDR VCO of the plurality to provide a second signal having a second signal frequency. The first and second M-NDR VCOs are interconnected with the plurality of memristive VCOs. The first and second M-NDR VCOs have independent programmable states and are connected to a common output of the frequency source. The method includes providing an M-NDR VCOs, where each M-NDR VCO includes an M-NDR device connected in parallel with a capacitance, and applying a bias voltage to activate a selected M-NDR VCO of the plurality to produce a frequency output.

Abstract: Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.

Abstract: A system includes at least a first array connected to a second array. The first array includes an odd number, greater than one, of unidirectionally-coupled non-linear first array elements. The second array includes an odd number, greater than one, of unidirectionally-coupled non-linear second array elements. The second array elements are unidirectionally-coupled in a direction opposite the coupling direction of the second array elements. The first array is configured to receive an input signal and down-convert the input signal. The second array is configured to receive the down-converted input signal, further down-convert the down-converted input signal, and output a down-converted output signal. The down-converted output signal is down-converted to a multiple of the frequency of the input signal proportional to the number of arrays of the system. The system may operate at frequencies greater than 1 GHz and may be contained in a microchip or on a printed circuit board.

Abstract: A device can be coupled to an electrical load for supplying electrical power to the electrical load. The device contains an oscillator unit and an auxiliary oscillator unit. The oscillator unit is configured to generate an output signal of the device which can be supplied to the electrical load and which has a first frequency. The auxiliary oscillator unit is electrically coupled to the oscillator unit. The auxiliary oscillator unit is configured to excite the oscillator unit to oscillate at a second frequency greater than the first frequency. The auxiliary oscillator unit contains a timing element which is configured and arranged to terminate the excitation of the oscillator unit after the expiration of a pre-specified period of time after the start of the oscillator unit and the auxiliary oscillator unit.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements.

Abstract: In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency.

Abstract: High-speed serial data signal transmitter and/or receiver circuitry is able to dynamically switch between handling data at two (or more) different data rates. Such a switch can be made very rapidly and with no requirement for reprogramming or reconfiguring the circuitry. Circuitry for glitchlessly switching between clock signals having different frequencies is also provided and may be used in the above-mentioned transmitter and/or receiver circuitry.

Abstract: Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

Abstract: The device resonant comprises a plurality of synchronized oscillators. Each oscillator comprises a resonator which comprises detection means providing detection signals representative of oscillation of the resonator to a feedback loop connected to an excitation input of the resonator. The detection signals control the conductivity of the feedback loop of the oscillator. The excitation inputs of all the resonators are connected to a common point which constitutes the output of the resonant device. A capacitive load is connected between said common point and a reference voltage.

Abstract: A frequency synthesizer includes: a first oscillator (1) controlled by a first control device, the first oscillator having a high quality factor that is greater than 300 and produces a first clock signal (2) RF having a fixed frequency, the first control device (30) controlling the frequency of the first controlled oscillator (1) on the basis of a first reference frequency; a second oscillator (3) controlled by a second control device and producing a second clock signal (4); the second control device (31) controlling the frequency of the second controlled oscillator (3) on the basis of a second reference frequency; and an integer frequency divider (5) dividing the frequency of the second clock signal (4) by a variable integer factor N1 and producing a third clock signal (6), the frequency of which is continuously variable by modifying the factor N1 and the control of the second oscillator.

Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

Abstract: A first and a second resonator are fabricated monolithically adjacent to one another. The first resonator is the reference resonator. The resonant frequency of the second resonator is offset by a difference frequency Fo from the first resonator. Each resonator is included within an oscillator. A mixer receives the output of both oscillators. A low pass filter receives the mixer output and generates a clock signal whose frequency is equal to the difference frequency Fo.

Abstract: In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency.

Abstract: A circuit comprising a DC current source and at least two spin torque oscillators, the at least two spin torque oscillators being electrically coupled to each other and to the DC current source. A circuit comprising phase shifting means is connected in such a way as to cause a phase shift between current and voltage through the spin torque oscillators. An advantage is that the controlled phase shift significantly increases the tolerance for deviating anisotropy fields, which makes manufacturing of spin torque oscillator devices much more feasible in practice.

Abstract: A device that includes: (i) an evaluated circuit; (ii) a leakage current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a leakage current of the evaluated circuit; (iii) a switching current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a switching induced current of the evaluated circuit; (iv) a power reduction module that is configured to: (a) compare between an oscillation frequency of the leakage current dependent oscillator and an oscillation frequency of the switching current dependent oscillator, to provide a current comparison result; (b) select a power reduction technique out of a dynamic voltage and frequency scaling technique and a power gating technique in view of the current comparison result; and (c) apply the selected power reduction technique.

Abstract: A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal.

Abstract: A semiconductor integrated circuit includes: digitally controlled oscillators; a phase-data output unit; an integration processing unit; a filter unit; a multiplier (a first multiplier) that outputs, as an oscillator tuning word, a value obtained by multiplying an output signal subjected to time division from the filter unit with a predetermined coefficient; and an output selector (a tuning-word separating unit) that allocates the oscillator tuning word to the digitally controlled oscillators in synchronization with a reference frequency.

Abstract: A communications device (100) includes a frequency divider circuit (106) having a plurality of frequency division ratios. The device also includes at least one phase-lock loop (PLL) circuit (101, 102, 103, 104, 110, 112) coupled to at least a signal input of the frequency divider circuit. The PLL circuit includes a local oscillator (LO) circuit (104) including a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges. The device further includes at least one control input (105) coupled to at least the frequency divider circuit and the PLL circuit for specifying one of the plurality of VCOs and one of the plurality of frequency division ratios of the frequency divider circuit.

Abstract: An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency.

Abstract: Phase locked loop based frequency tuning of an adjustable filter is disclosed. A resonant circuit includes the adjustable filter, and an oscillator signal provides an input to the resonant circuit.

Abstract: An apparatus and a method for compensating for a mismatch in temperature coefficients of two oscillator frequencies to match a desired frequency ratio between the two oscillator frequencies over a temperature range. In one embodiment of a temperature sensor, first and second oscillators of different temperature characteristics are coupled to a differential frequency discriminator (DFD) circuit. The DFD circuit compensates for the different characteristics in order to match a frequency difference between the first and second frequencies over a temperature range.

Abstract: System for filtering an input frequency to produce an output frequency having low phase noise. A first PLL includes, in the feedback path, a frequency translation circuit which translates a frequency from a VCO in the first PLL by an offset frequency provided by the second PLL to provide either a sum or difference frequency. The first PLL locks its VCO to a crystal oscillator input frequency translated by the offset frequency due to the frequency translation circuit. A second PLL compares the input frequency to be filtered to the output of the first PLL VCO. The second PLL causes the first PLL VCO to lock to the input frequency by varying the offset frequency it provides to the frequency translation circuit. The bandwidth of the second PLL is significantly smaller than the bandwidth of the first PLL. The filtered output frequency is available from the first PLL VCO.

Abstract: A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.

Abstract: A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Abstract: The invention relates to a method for carrying out a frequency change whilst retaining the phase relationship between several devices, in particular, network analyzers. Each device has at least one signal generator for stimulating an object for measurement and at least one local oscillator, connected to at least one mixer, for receiving a measuring signal obtained from the object for measurement by the superposition principle. On changing frequency, in a first step, only the frequency of the local oscillators of all devices is changed and the frequency of the signal generators of all devices remains unchanged. In a second step, only the frequency of at least one signal generator is changed and the frequency of the local oscillators of all devices remains unchanged.

Abstract: A multi-phase oscillator includes a plurality of ring oscillators (21) each having a plurality of output ports and each formed by connecting an odd number of inverters (20) in a ring, and a plurality of resistance elements (30) coupling the output ports between the plurality of ring oscillators (21) so that all of the plurality of ring oscillators (21) operate at an identical frequency while keeping a desired phase relationship. The number of the ring oscillators (21) is not limited to an odd number but may be an even number. The multi-phase oscillator changes the state of a succeeding node of a phase coupling to accord with the state of a preceding node of the phase coupling by using the resistance elements (30) as phase coupling devices. If resistors are used as the resistance elements (30), the phase output accuracy greatly improves and high frequency oscillation is possible.

Abstract: A device for inducing a user's motion in a rhythm responsive to a motion rhythm after the user's motion rhythm changes suddenly. The walking assist device generates a first oscillator which attains mutual entrainment with a user's hip joint angular velocity to reflect a natural angular velocity. On the other hand, a new natural angular velocity is set based on the phase difference between the hip joint angular velocity and the first oscillator. A second oscillator which oscillates in rhythm reflecting the natural angular velocity is generated. An inducing oscillator is generated based on the second oscillator, and a torque responsive to the inducing oscillator acts on the user's body. If the magnitude of a periodic variation in the hip joint angular velocity exceeds a threshold value, a second oscillator which oscillates in rhythm reflecting the angular velocity of the first oscillator instead of the natural angular velocity is generated.

Abstract: In a voltage-controlled oscillator capable of broadening a variable frequency range while suppressing increase of conversion gain, a converter (12) converts an input voltage to a first physical quantity, a variable converter (13) supplies a second physical quantity that accords with the status of each switch of a switch group (13a). another variable converter (14), when the input voltage is contained within a prescribed voltage range, supplies a third physical quantity that accords with the input voltage and the status of each switch of another switch group (14a), and a variable-frequency oscillator (15) supplies a signal of a frequency that accords with the first physical quantity, the second physical quantity, and the third physical quantity.