Abstract: A method is provided for generating local oscillator signals for a mixer. The method includes providing a reference frequency signal and generating a differential in-phase signal and a differential quadrature signal from the reference frequency signal. The method further includes re-clocking each of the differential in-phase and differential quadrature signals using the reference frequency signal. The re-clocked differential in-phase and differential quadrature signals are then provided as the local oscillator signals for the mixer.

Abstract: The present invention concerns a device having a first and a second differential oscillators (1, 2; 1?2?) coupled to and in quadrature-phase with each other, comprising first and second resonant electronic means (L1, C1, C2; L2, C3, C4) respectively, which are apt to provide, respectively on first two and second two terminals (NODE—1, NODE—2; NODE—3, NODE 4), first two and second two oscillating signals (VNODE—1, VNODE—2; VNODE—3, VNODE—4), said first two oscillating signals (VNODE—1, VNODE—2) being in phase opposition to each other and in quadrature-phase with said second two oscillating signals (VNODE—3, VNODE—4), the device being characterised in that it comprises first generator electronic means (M13-M24) apt to detect first instants of passage through a first reference value of each one of said first oscillating signals (VNODE—1, VNODE—2) and to generate first power supply pulses for said second resonant electronic means (L2, C3, C4) in second instants, and in that it comprises second generator electroni

Abstract: Disclosed is a semiconductor integrated circuit device that includes a ring oscillator circuit, performs a proper oscillation operation, and expands the range of oscillation frequency variation. The ring oscillator circuit includes, for instance, plural differential amplifier circuits. MOS transistors are respectively added to input nodes of a differential pair of the differential amplifier circuits. Further, gate control circuits are incorporated to control the gates of the MOS transistors, respectively. The gate control circuits cause the MOS transistors to function as an amplitude limiter circuit in mode 3, exercise control to turn off the amplitude limiter circuit in mode 2, and use the amplitude limiter circuit to start oscillation in mode 1.

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors.

Abstract: An electrical circuit includes a first path including even-number inverters connected in series from a first node serving as an input side to a second node serving as an output side, a second path including even-number inverters connected in series from the second node serving as an input side to the first node serving as an output side, a latch circuit providing a connection between the first node and the second node such that a logical value of the first node and a logical value of the second node are opposite to each other, and one or more control signal paths to supply one or more control signals to the latch circuit to provide and sever a connection between the latch circuit and a power supply.

Abstract: Provided are a differential voltage-controlled oscillator (VCO) and a quadrature VCO using center-tapped cross-coupling of a transformer. The differential VCO and the quadrature VCO can be driven by low power through a current reuse structure and have an excellent phase noise characteristic by center-tapped cross-coupling through a transformer. Further, variable capacitance units for frequency variation are divided into variable capacitance units for coarse tuning and variable capacitance units for fine tuning. Therefore, it is possible to obtain a wide tuning range while voltage oscillation gain is reduced. Further, the differential VCO and the quadrature VCO are configured in such a manner that the respective variable capacitance units operate linearly throughout the entire capacitance region due to control voltage distribution by resistors. Accordingly, it is possible to obtain a linear control voltage-oscillation frequency characteristic.

Abstract: The invention includes a harmonic suppression circuit, an injection-locked frequency divider circuit (ILFD) and associated methods. The harmonic suppression circuit comprises a source voltage, two suppression modules, two input terminals, two smoothed output terminals and a ground. The ILFD comprises a ground, an input transistor, an input terminal, two divider legs, two output terminals and a source voltage. The associated method to improve harmonic suppression comprises acts of synthesizing differential-phase signals and simultaneously suppressing second harmonics of in-phase signals. The method to extent an ILFD's locking range comprises acts of decreasing quality factor while keeping resonance frequency constant.

Abstract: The present invention relates to an oscillator circuit and a method of controlling the oscillation frequency of an in-phase signal and a quadrature signal. First oscillator means (2) with a first differential oscillator circuit and a first differential coupling circuit are provided for generating the quadrature signal. Furthermore, second oscillator means (4) with a second differential oscillator circuit and a second differential coupling circuit are provided for generating the in-phase signal. A frequency control means is provided for varying the oscillation frequency of the in-phase signal and the quadrature signal by controlling at least one of a common-mode current and a tail current of the first and second oscillator means. Thereby, a high-frequency IQ oscillator with high linearity is obtained.

Abstract: Improvements in and relating to electronic pulse generation or oscillation circuitry based on a signal path exhibiting endless electromagnetic continuity and affording signal phase inversion in setting pulse duration or half-cycles of oscillation within time of signal traverse of said signal path, and having active switching means associated with said signal path to set rise and fall times of each said pulse or said half-cycle of oscillation, including for frequency adjustment by selective inductance and power saving without stopping pulse generation or oscillation.

Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1?; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2?; a differential output terminal that outputs differential output signals Vout+ and Vout? generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

Abstract: A stabilized quadrature oscillator providing consistently high signal quality is disclosed. The stabilized quadrature oscillator includes an iterative quadrature oscillator and a quadrature signal stabilizer. The iterative quadrature oscillator generates an iterative cosine signal and an iterative sine signal using a stabilized cosine signal and a stabilized sine signal from the quadrature signal stabilizer. The quadrature signal stabilizer generates the stabilized cosine signal and the stabilized sine signal based on an energy measure of the iterative cosine signal and the iterative sine signal. Specifically, if the energy measure is less than a low threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a greater magnitude than the iterative sine signal and the iterative cosine signal, respectively.

Abstract: A dual-band wideband local oscillation signal generator includes an oscillation unit, a division unit, a poly phase filter (PPF), a switch unit, and a single side band (SSB) mixer. The oscillation unit is configured to generate a positive in-phase (IP) signal, a negative in-phase (IN) signal, a negative quadrature-phase (QN) signal, and a positive quadrature-phase (QP) signal. The division unit is configured to divide frequencies of the IP signal and the IN signal and generate an RF signal. The PPF is configured to receive the IP signal and the IN signals inputted to the division unit, and generate an LO IP signal, an LO IN signal, an LO QP signal, and an LO QN signal. The switch unit is configured to receive the generated LO signals and select a high band frequency signal or a low band frequency signal.

Abstract: A system includes at least a first array connected to a second array. The first array includes an odd number, greater than one, of unidirectionally-coupled non-linear first array elements. The second array includes an odd number, greater than one, of unidirectionally-coupled non-linear second array elements. The second array elements are unidirectionally-coupled in a direction opposite the coupling direction of the second array elements. The first array is configured to receive an input signal and down-convert the input signal. The second array is configured to receive the down-converted input signal, further down-convert the down-converted input signal, and output a down-converted output signal. The down-converted output signal is down-converted to a multiple of the frequency of the input signal proportional to the number of arrays of the system. The system may operate at frequencies greater than 1 GHz and may be contained in a microchip or on a printed circuit board.

Abstract: An oscillating circuit includes N nodes outputting oscillating signals, a main loop circuit including N inverting circuits, and a plurality of auxiliary loop circuits. Each inverting circuit in the auxiliary loop circuits is connected in parallel with even numbers of inverting circuits cascaded in the main loop circuit. The circuits for feeding back signals from outputs to inputs of the respective inverters of the main loop circuit have circuit configurations equivalent to each other. Each inverting circuit in the main loop circuit and the auxiliary loop circuits drives an output line such that a phase of an output signal is inverted with respect to a phase of an input signal and has driving power that becomes lower when the phases of the output signal and the input signal are inverted with respect to each other than when the output signal and the input signal are in phase with each other.

Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.

Abstract: Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.

Abstract: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor.

Abstract: Generation of Terahertz range (300 GHz to 3 THz) frequencies is increasingly important for communication, imaging and spectroscopic systems, including concealed object detection. Apparatus and methods describe generating multiple phase signals which are phase-locked at a fundamental frequency, which are then interleaved into an output which is a multiple of the fundamental frequency. By way of example phase generators comprise cross-coupling transistors (e.g., NMOS) and twist coupling transistors (NMOS) for generating a desired number of phase-locked output phases. A rectifying interleaver comprising a transconductance stage and Class B amplifiers provides superimposition of the phases into an output signal. The invention allows frequency output to exceed the maximum frequency of oscillation of a given device technology, such as CMOS in which a 324 GHz VCO in 90 nm digital CMOS with 4 GHz tuning was realized.

Abstract: To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born.

Abstract: A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.

Abstract: A multiphase oscillator with a control path for urging the rotational direction of the oscillator is disclosed. The multiphase oscillator has an electrically or magnetically or both continuous signal path over which a signal propagates subject to a phase reversal on each traversal of the signal path and active switching means that create and sustain the propagating signal. A control path has a control signal whose propagation activates each switching means in the order of the direction of propagation of the control signal on the control path so as to determine direction of the signal propagating on the signal path.

Abstract: An alternate clock apparatus and method configured to reduce noise in selected frequency bands in an electronic device such as a communication device is described. In one embodiment the alternate clock includes a ring oscillator to generate multiple time shifted signals which may then be combined to generate clock signals at alternate frequencies to a primary reference. A resynchronization circuit may be coupled to the ring oscillator to periodically resynchronize the ring oscillator to a reference signal to reduce alternate clock jitter.

Abstract: A circuit comprising a DC current source and at least two spin torque oscillators, the at least two spin torque oscillators being electrically coupled to each other and to the DC current source. A circuit comprising phase shifting means is connected in such a way as to cause a phase shift between current and voltage through the spin torque oscillators. An advantage is that the controlled phase shift significantly increases the tolerance for deviating anisotropy fields, which makes manufacturing of spin torque oscillator devices much more feasible in practice.

Abstract: There is provided a wide-band direct conversion transmitting apparatus including: a local oscillation unit generating first, second, and third oscillation signal pairs each including a pair of signals having a phase difference of 90°; an image rejection mixer unit mixing baseband transmission signals including an I signal and a Q signal having a phase difference of 90° with the first oscillation signal pair; a harmonic rejection mixer unit mixing each of the first, second, and third oscillation signal pairs with the baseband transmission signals; and an output signal selecting unit selecting output signals from the image rejection mixer unit or from the harmonic rejection mixer unit.

Abstract: A multi-phase ultra-wideband signal generator uses differential pulse oscillators. The multi-phase ultra-wideband signal generator using differential pulse oscillators includes N pulse oscillators for generating pulse signals based on a supply of power, and further comprises N inverting amplification units for outputting inverted amplified signals of output signals of the N pulse oscillators when a number of pulse oscillators is at least two, wherein, when the number of pulse oscillators is an even or odd number, the pulse oscillators are arrayed such that they have a connection form in which output terminals OUT(+) and OUT(?) of a relevant pulse oscillator are connected to output terminals OUT(+) and OUT(?) of a next pulse oscillator through a relevant inverting amplification unit, and the connection form is consecutively applied to the pulse oscillators.

Abstract: An element for interacting with electromagnetic radiation is disclosed, including a first self-resonant body, a second self-resonant body, and a directional device interposed between the first self-resonant body and the second self-resonant body. The directional device is adapted to inhibit propagation of electromagnetic radiation from the second self-resonant body to the first self-resonant body.

Abstract: Provided are a harmonic rejection mixer and a harmonic rejection mixing method. A plurality of oscillator signals having a ? duty cycle and uniform phase differences may be generated and a differential or quadrature mixer with harmonic rejection may be realized by using the oscillator signals.

Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).

Abstract: An automatic frequency calibration apparatus and a method thereof for a phase-locked loop based frequency synthesizer are disclosed. The apparatus includes a frequency-to-digital converter configured to convert a frequency of a VCO output signal to a first digital value, a target value setting section configured to provide a second digital value corresponding to a target frequency, and a finite state machine configured to calibrate the frequency of the VCO output signal by using the difference of the first digital value and the second digital value. Accordingly, the calibration speed and a frequency resolution of the automatic frequency calibration apparatus in a frequency synthesizer may be enhanced.

Abstract: System for filtering an input frequency to produce an output frequency having low phase noise. A first PLL includes, in the feedback path, a frequency translation circuit which translates a frequency from a VCO in the first PLL by an offset frequency provided by the second PLL to provide either a sum or difference frequency. The first PLL locks its VCO to a crystal oscillator input frequency translated by the offset frequency due to the frequency translation circuit. A second PLL compares the input frequency to be filtered to the output of the first PLL VCO. The second PLL causes the first PLL VCO to lock to the input frequency by varying the offset frequency it provides to the frequency translation circuit. The bandwidth of the second PLL is significantly smaller than the bandwidth of the first PLL. The filtered output frequency is available from the first PLL VCO.

Abstract: A frequency synthesizer includes a digitally-controlled oscillator and an oscillation frequency control unit. The digitally-controlled oscillator includes a loop-shaped transmission line path having an odd number of parallel portions in each of which two conductors are arranged in parallel to each other with a space therebetween, and an odd number of intersection portions in each of which two conductors intersect spatially, an active circuit coupled between the two conductors, and a first variable capacitance unit and a second variable capacitance unit. The oscillation frequency control unit includes a ?? modulation circuit for subjecting to ?? modulation a first control signal for switching a high capacitance state and a low capacitance state of a first variable capacitance element included in the first variable capacitance unit.

Abstract: An assistant measuring circuit for an oscillator is provided. The oscillator provides N oscillating signals with different phases. The assistant measuring circuit includes N buffers, N reflection-type modulators, and a controller. An ith buffer among the N buffers receives and further transmits an ith oscillating signal among the N oscillating signals. An ith modulator among the N modulators has an ith signal input end, an ith signal output end, and an ith signal control end. The ith oscillating signal is transmitted to the ith signal input end through the ith buffer. The signal output ends of the N modulators are all electrically connected to a measuring end. The controller is used for providing an ith control signal to the ith signal control end.

Abstract: A first comparator compares an output voltage Vout appearing at a capacitor with a maximum threshold voltage Vmax. A second comparator compares the output voltage Vout with a minimum threshold voltage Vmin. An edge detection circuit detects an edge of a synchronization signal SYNC having approximately ½ of frequency of the output voltage Vout and outputs an edge detection signal SE. A charge-discharge control unit refers to the first and the second comparison signal, and sets the charge-discharge circuit to a discharging state when the output voltage Vout becomes higher than the maximum threshold voltage Vmax and sets the charge-discharge circuit to a charging state when the output voltage Vout becomes lower than the minimum threshold voltage Vmin. When the edge signal SE becomes the predetermined level, the charge-discharge control unit switches the charging state and the discharging state of the charge-discharge circuit.

Abstract: A multi-phase oscillator includes a plurality of ring oscillators (21) each having a plurality of output ports and each formed by connecting an odd number of inverters (20) in a ring, and a plurality of resistance elements (30) coupling the output ports between the plurality of ring oscillators (21) so that all of the plurality of ring oscillators (21) operate at an identical frequency while keeping a desired phase relationship. The number of the ring oscillators (21) is not limited to an odd number but may be an even number. The multi-phase oscillator changes the state of a succeeding node of a phase coupling to accord with the state of a preceding node of the phase coupling by using the resistance elements (30) as phase coupling devices. If resistors are used as the resistance elements (30), the phase output accuracy greatly improves and high frequency oscillation is possible.

Abstract: A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal.

Abstract: A novel and useful apparatus for and method of local oscillator generation employing an exception handling mechanism that permits an oscillator having a limited modulation range to handle the large modulation ranges demanded by modern wideband wireless standards such as 3G WCDMA, etc. A controllable oscillator generates an RF signal having four quadrature phases in accordance with an input command signal. An exception handler compares the frequency command information against a threshold. If it exceeds the threshold a phase jump and a residue frequency command are generated. The residue frequency command is input to an oscillator which is operative to generate an RF signal having four quadrature phases. The phase jump is input to a quadrature switch which functions to select one of the four quadrature phase signals as the output RF signal which is then fed to a digital power amplifier.

Abstract: A multi-phase voltage-control oscillator including a first voltage-control oscillator circuit and a second voltage-control oscillator circuit is provided. The second voltage-control oscillator circuit and the first voltage-control oscillator circuit have a plurality of inductors, and the inductors in the second voltage-control oscillator circuit are respectively cross-coupled with the inductors in the first voltage-control oscillator circuit to generate a mutual inductance effect, so as to output a plurality of oscillating signals with different phases.

Abstract: A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector.

Abstract: A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase resolution.

Abstract: Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

Abstract: An electrical circuit includes a first path including even-number inverters connected in series from a first node serving as an input side to a second node serving as an output side, a second path including even-number inverters connected in series from the second node serving as an input side to the first node serving as an output side, a latch circuit providing a connection between the first node and the second node such that a logical value of the first node and a logical value of the second node are opposite to each other, and one or more control signal paths to supply one or more control signals to the latch circuit to provide and sever a connection between the latch circuit and a power supply.

Abstract: An oscillator includes a reference stage and multiple phase stages. The reference stage has a reference transistor having a gate coupled to a voltage reference and a drain coupled to a reference current source. Each phase stage includes a transistor, two current sources, a capacitor, switch, inverter, and latch. The transistor has a drain coupled to a first current source, a gate coupled to a node and a source coupled to the reference transistor's source. The capacitor and switch couple between the node and ground. The second current source couples to the node. The transistor's drain couples to the inverter's input. The inverter's output couples to the latch's set input. The latch's output couples to the switch. The inverter output also couples to the reset input of a subsequent phase stage's latch. The inverter output for a last stage couples to the reset input of a first stage latch.

Abstract: In an embodiment, a circuit is provided comprising a multi-phase oscillator configured to output a plurality of output signals having the same frequency and different phase offsets. A feedback value is generated based on at least two of said output signals. A reference value is generated based on a reference clock and a predetermined value. The reference value and the feedback value are combined.

Abstract: A tail-tank coupling technique combines two complementary differential LC-VCOs to form a quadrature LC-VCO. The technique reduces phase noise by providing additional energy storage for noise redistribution and by cancelling noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum 1+?, similar to a differential LC-VCO driven by an ideal noiseless current source. However, its figure-of-merit is higher, due to the absence of voltage head-room being consumed by a current source. The optimal ratio of tail-tank capacitor to main-tank capacitor for minimizing phase noise is approximately 0.5. The method can be extended to combine any even number of LC tanks resonating at fo and 2fo to form an integrated oscillator producing quadrature phase at frequency fosc and differential output at 2fosc.

Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

Abstract: Apparatus to generate signals with multiple phases are described. The apparatus includes a fixed multilayer stack providing a varying magnetic field and at least two sensors adjacent the fixed multilayer stack to sense the varying magnetic field and generate at least two output signals. The frequency of the output signals can be tuned by an input current.

Abstract: A wide tuning range and constant swing VCO is described that is based on a multipass Ring Oscillator enhanced with feed-backward connections. This VCO is designed to overcome tuning range limitations of prior-art “feed-forward” ring oscillators. The Feedback multipass Ring Oscillator of the invention provides decreasing frequency when tuned by increasing the feedback, thus covering a much wider tuning range irrespective of the speed limit of the technology while at the same time providing almost constant amplitude.

Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).

Abstract: A voltage controlled oscillator that is a differential ring oscillator type voltage controlled oscillator that, by connecting in cascade differential delay elements to which differential clock signals of a mutually reverse phase are input and controlling the current that flows to the differential delay elements by a bias voltage, controls a delay amount of this differential clock signal, having a phase detection portion that outputs a detection signal by comparing an output voltage of the differential output of any differential delay element and a reference voltage that is set to a voltage that detects an abnormal operation, and a cross-coupled circuit that is provided at each of the differential delay elements and, when the detection signal is input, amplifies the potential difference between the pair of differential output terminals.

Abstract: An open-loop switching amplifier achieves synchronous operation using a ring oscillator based upon a tapped delay line. A counter is clocked from the ring oscillator, periodically comparing incoming more significant data to the value of the counter to form a pulsewidth modulated output waveform. Modulating the effective width of the output waveform in incremental delay line taps is equivalent to incoming less significant data. This technique then effects time-period summation of coarse and fine resolution clocked data.