Abstract: The system and method generates two clock signals, one with a 2 ns delay with respect to the other, from a single PLL to enable a RGMII.

Abstract: An interleaved VCO is configured using a ring oscillator with voltage controlled feedforward inverting stages coupled around the inverting stages making up the basic ring oscillator to enable the frequency of the ring oscillator to be voltage controlled. The feedforward inverting stages comprise a complementary inverter stage and a voltage controlled transfer gate. Complementary control voltages are coupled to the gates of the complementary transfer gate FET devices. Likewise, the complementary control voltages are coupled to the corresponding body of the FET devices in the transfer gate and in the inverting stage. The complementary control voltages may also be connected to the body of the complementary FET devices in the inverting stages making up the basic ring oscillator. This allows the frequency range of the VCO to be extended without having to switch the feedforward paths into an out of the circuit.

Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: Provided is a quadrature voltage controlled oscillator capable of varying a phase difference between an in-phase output signal and a quadrature output signal. The quadrature voltage controlled oscillator comprises a first voltage controlled oscillator, a second voltage controlled oscillator, a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier. The first voltage controlled oscillator generates a first output and a second output. The second voltage controlled oscillator generates a third output and a fourth output. The first output is a positive in-phase signal, and the second output is a negative in-phase signal. The third output is a positive quadrature signal, and the fourth output is a negative quadrature signal. The first amplifier is controlled by a first current and drives the first output and the second output in response to the third output and the fourth output.

Abstract: An oscillator that provides a quadrature output and has a cross-coupled configuration is disclosed. The oscillator generates an output signal having a frequency. Two phase shift circuits, or stages, are activated by a control signal to provide phase shifts within the oscillator. Each phase shift circuit includes poles to provide the phase shift. A pole includes a varactor to tune, adjust or vary the phase shift accordingly.

Abstract: The invention provides an oscillator apparatus having a plurality of stages, with each stage of the plurality of stages having an output node, and with a plurality of input transistors within each stage. The various output nodes are coupled to the transistor inputs of the various stages, such that for the nth stage of the plurality of stages, the input to jth transistor, of the plurality of input transistors, is coupled to the (n?j)th output node, and wherein (n?j) is determined modulo N, where “N” is a total number of the plurality of stages and “j” is a transistor number of the plurality of input transistors within each stage. The various embodiments of the oscillator include oscillators with 6 or more stages and with 3 or more inputs per stage, plus any load input transistor, including 8 and 16 stage oscillators to produce a multiplicity of phases for any selected use.

Abstract: An apparatus and method for programmable lock detection and correction (PLDC) to a programmable accuracy in a digital delay-locked loop (DLL) based multiphase clock generator (MCG) is based on a DLL that utilizes a digital count to control the delay of a digitally controlled, multiple-tap delay line in its feedback path where stability of the digital count is used to qualify the determination of lock to a programmable accuracy and lock determination is based on combinatorial evaluation of the multiple phase outputs for the proper waveform relationships. The incidence of false lock corresponding to excessive delay through the delay line is addressed by a LOOPRESET signal that results in a reset of the digital count that controls the delay through the delay line. Additionally, programmability of the stability interval, the digital counter step size, and the accuracy of the lock provide control over lock acquisition time.

Abstract: Controllable oscillator circuit comprising a regenerative loop which incorporates a cascade circuit of first and second sections each having a controllable gain and a phase shift which is 90° at the oscillation frequency, the first and second sections comprising first and second transconductance amplifiers, respectively, outputs of which are coupled to third and fourth transconductance amplifiers, which are positively fed back from the output to the input, and via first and second capacitors to inputs of the second and first gain controlled amplifiers, said first and second capacitors being coupled in parallel to first and second load resistors, respectively, a tuning control current being supplied to control inputs of the first and second transconductance amplifiers, the output of at least one of the first and second transconductance amplifiers being coupled to an amplitude detection arrangement providing a gain control current for an automatic gain control to control inputs of the third and fourth transcond

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A frequency synthesizing circuit is provided. The frequency synthesizing circuit includes a frequency multiplying circuit and a phase-locked loop, wherein the frequency multiplying circuit can converts a reference signal having a low frequency into a high frequency signal for being a reference signal of the phase-locked loop, so that the loop bandwidth of the phase-locked loop can be increased to reduce jitter of the output signal. The present invention utilizes the delay-locked loop to generate multiphase output signals that equivalently divide a cycle of the reference signal for achieving a frequency multiplying through cooperating with a phase synthesizer. Through double frequency multiplying functions of the delay loop and the phase locked loop, a phase error accumulation caused by the single frequency multiplying of the conventional phase-locked loop with narrow loop bandwidth can be reduced.

Abstract: The asynchronous data burst transfer circuit includes a data burst transfer oscillation circuit which outputs n strobe signals of mutually different phases, plural parallel-serial conversion circuits which convert n-bit parallel signals into serial signals, and plural serial-parallel conversion circuits which convert serial signals into n-bit parallel signals. The parallel-serial conversion circuits convert every n-bit parallel signals of data read from a memory into serial signals based on the strobe signals, and transfer the serial signals. The serial-parallel conversion circuits convert the received serial signals into n-bit parallel signals based on the strobe signals, thereby obtaining the parallel signals as the original data.

Abstract: A zero or near zero IF frequency changer for use in a digital tuner comprises multipliers which receive the RF input signal from an input. The multipliers receive quadrature local oscillator signals from a first oscillator of an arrangement which comprises first and second phase-locked loops. The first phase-locked loop comprises a programmable divider, a comparator and a control loop so that the first oscillator is phase-locked to a second oscillator. A second phase-locked loop comprises the second oscillator and a synthesizer containing a reference oscillator to which the second oscillator is phase-locked. The output frequency of the second oscillator is in a frequency band which is outside the RF input frequency band of the frequency changer.

Abstract: A quadrature oscillator with phase error correction including a local oscillator that generates a single-ended clock signal, a single-ended to differential converter that converts the clock signal to a differential clock signal, a quadrature generator that converts the differential clock signal into I and Q carrier signals, a phase error detector that measures a phase error between the I and Q carrier signals, and a feedback amplifier that modifies the differential clock signal based on measured phase error. The feedback amplifier applies the measured phase error as a DC offset to an AC differential clock signal. A transconductor converts the differential clock voltage signal into two pairs of differential current clock signals, where the quadrature generator generates I and Q current signal outputs from the two pairs of differential current clock signals.

Abstract: A phase-locked loop includes a voltage-controlled oscillator (VCO) to generate a plurality of quadrature-phase signals at one-half an output frequency in response to bias signals. The VCO also includes a times-two multiplier biased by the bias signals to generate the output frequency from the quadrature-phase signals. The bias signals include a load-element bias signal to concurrently bias load elements of buffer stages of the VCO and substantially identical load elements of the multiplier. The bias signal also include a current-source bias signal to concurrently bias current sources of the buffer stages of the VCO and a substantially identical buffer stage of the multiplier. The VCO operating at one-half the output frequency together with the multiplier may consume less power than the VCO when operating at the output frequency.

Abstract: A divide by X.5 circuit can be implemented as a divided by 1.5 circuit. A phase-locked loop (PLL) has a quadrature voltage-controlled oscillator (VCO) that generates four phases offset at 0, 90, 180, and 270 degrees. Differential signals from the VCO are converted to single-ended VCO clocks that drive four divide-by-3 circuits, each clocked by one of the four phases of the VCO clocks. Resets to the divide-by-3 circuits are staggered to activate each divide-by-3 circuit synchronously with its phase clock. Outputs from the divide-by-3 circuits are applied to a frequency doubler that generates the final clock that is 1.5 times slower than the VCO clocks. The final clock has a near 50%-50% duty cycle.

Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: A system for generating in-phase and quadrature phase signals is provided. The system includes a first and a second differential output, such as from a sinusoidal oscillator. A first injection-locked frequency divider, such as one that uses an LC oscillator in conjunction with cross-coupled transistors, receives the first differential output and generates a in-phase or in-phase output. A second injection-locked frequency divider receives the second differential output and generates a quadrature phase output.

Abstract: A PLL circuit for comparing with a phase comparator 1a phase between an input signal and one of multiphase pulse signals CK0DIV to CKNDIV used as a channel clock generated by an output of a controlled oscillator 5, and controlling an oscillation of the controlled oscillator 5 according to a phase difference signal, comprises a frequency fixing circuit 9 for outputting an activating signal PCSTART for the control when the input signal is nearly equivalent to a frequency of the channel clock and has entered into a capture range of the phase comparator and a selection circuit 7 for selecting as the channel clock a multiphase pulse signal of a closest phase to a generating point of the input signal after generation of the activating signal, and the selection circuit 7 decides whether the input signal is advanced or delayed with respect to the channel clock after having selected a multiphase pulse signal as the channel clock and generates either an advance signal or delay signal according to the advance/delay of t

Abstract: A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

Abstract: Method and related apparatus for realizing frequency-multiplication by generating a high frequency signal according to a plurality of low frequency signals. The method includes: according to a plurality output signals generated by a phase-locked loop (PLL) or a delay-locked loop (DLL), generating a plurality of reference signals with a same frequency and different phases; when a number of the reference signals with signal level high is greater than a number of the reference signals with signal level low, making a signal level of the output signal remains a first level; otherwise, making the signal level of the output signal remains a second level substantially different from the first level. Thus the frequency of the output signals is a multiplication of the frequency of the input signals.

Abstract: Timing signal generation and distribution are combined in operation of a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means. Two-or more-phases of substantially square-wave bipolar signals arise directly in travelling wave transmission-line embodiments compatible with semiconductor fabrication including CMOS. Coordination by attainable frequency synchronism with phase coherence for several such oscillating signal paths has intra-IC inter-IC and printed circuit board impact.

Abstract: A quadiature oscillator includes a master tuned oscillator and two injection-locked slave tuned oscillators.

Abstract: A quadrature coupled controlled oscillator comprising a first and a second circuit module, each of the circuit modules (100 and 100′) comprising an astable multivibrator circuit (103). The first circuit module is coupled with the second circuit module and the second circuit module is cross coupled with the first circuit module. Each of the circuit modules (100 and 100′) comprises a first and a second Voltage Controlled Current Source (101) (VCCS). In each of the circuit modules, each VCCS is coupled to a phase shifter (102) for shifting the phase of a current (110) supplied by the VCCS to a resonator (104) included in that circuit module. A communication arrangement (300) for communicating via a bi-directional communication channel (304), comprises an oscillator (303) as described above for generating a periodic signal. A receiving module (301) generates an output signal from the periodic signal and a receiving signal received from the channel (304).

Abstract: A phase-locked loop system and method are provided. The system may include an error detector configured to receive a reference signal, and a voltage-controlled oscillator subsystem coupled to the error detector. The voltage-controlled oscillator subsystem is typically configured to produce a primary output signal that tends toward a predefined frequency relationship with the reference signal, and to produce a feedback signal that is routed in a feedback loop back to the error detector. The voltage-controlled oscillator subsystem typically includes a multiple output voltage-controlled oscillator having a plurality of VCO outputs. The voltage-controlled oscillator subsystem is typically configured to form the feedback signal from a plurality of the VCO outputs.

Abstract: A delay-locked loop includes a ring oscillator that generates a plurality of tap clock signals, with one tap clock signal being designated an oscillator clock signal. Each tap clock signal has a respective delay relative to the oscillator clock signal. The oscillator clock signal clocks a coarse delay counter to develop a coarse delay count that determines a coarse delay of a delayed clock signal. A fine delay of the delayed clock signal is determined by selecting one of the tap clock signals of the ring oscillator. The phase between an input clock signal and the delayed clock signal is determined and the coarse and fine delays adjusted in response to this phase to synchronize the delayed and input clock signals. The delay-locked loop may also monitor rising and falling edges of the input clock signal and develop corresponding rising-edge and falling-edge fine delays to synchronize rising and falling edges of the input clock signal.

Abstract: A cross-coupled differential MOS oscillator having reduced phase noise is applicable to a RF communication device such as a transmitter or receiver. The oscillator having low phase noise is formed of a frequency dependent amplifier to amplify a signal having a fundamental frequency; a frequency dependent feedback device that is connected between an output of the frequency dependent amplifier and an input of the frequency dependent amplifier to feed a portion of an amplified signal having the fundamental frequency to an input of the frequency dependent amplifier to stimulate oscillation; and a attenuating device in communication with the frequency dependent amplifier. The attenuating device reduces the gain of the frequency dependent amplifier for signals having frequencies much, much less than the fundamental frequency to decrease the phase noise.

Abstract: A quadrature ring oscillator for high clock-rate applications is disclosed. A quadrature LC ring oscillator may use two stages of LC oscillators and variable mixers to provide consistent oscillation even at high clock rates. One stage of the quadrature ring oscillator comprises a first resonating element having an input and an output, and a first variable summer having L and P inputs and an output, with its L input being connected to the output of the first resonating element. The output of the first variable summer is connected to the input of the first resonating element The first variable summer may generate its output at a first phase by combining the L and P inputs. A second stage of the LC ring oscillator comprises a second resonating element, which has an input and an output, with its output being connected to the P input of the first variable summer. An inverter is used to produce an inverted signal of the output of the first resonating element.

Abstract: A tapped phase shift ring oscillator may be used to provide multiple clock signals having variable phase delays. Phase delays may be selected to compensate for clock skews at different locations on high speed chips, or to provide clock signals having specific, desirable phase relationships, such as quadrature signals. The phase shift ring oscillator includes an odd number of amplifier stages. Each amplifier stage includes a phase shift network and an amplifier network. CMOS components used in the phase shift and amplifier networks provide voltage controlled variable phase shift and low gain, wide bandwidth, and low output impedance.

Abstract: A variable delay circuit of this invention includes delay paths, connection paths, and a NAND circuit 146 which takes output of the delay paths and performs logical NAND operation. The delay paths are connected in parallel to an input terminal. The connection path connects electrically an output of a delay element in the first delay path, and an input of a delay element in the second delay path. The connection path connects electrically an output of the delay element, and an input of the delay element. An additional element is positioned at an input of a predetermined delay element so that input loads of delay elements are equalized. From these configurations, there is provided the variable delay circuit which stabilizes a supply current, and generates an accurate delay in a small-sized circuit.

Abstract: The asynchronous data burst transfer circuit includes a data burst transfer oscillation circuit which outputs n strobe signals of mutually different phases, plural parallel-serial conversion circuits which convert n-bit parallel signals into serial signals, and plural serial-parallel conversion circuits which convert serial signals into n-bit parallel signals. The parallel-serial conversion circuits convert every n-bit parallel signals of data read from a memory into serial signals based on the strobe signals, and transfer the serial signals. The serial-parallel conversion circuits convert the received serial signals into n-bit parallel signals based on the strobe signals, thereby obtaining the parallel signals as the original data.

Abstract: A system and method are provided for controlling the phase of a voltage controlled oscillator output. The method comprises: accepting a plurality of VCO outputs coarsely differentiated by phase; selecting one of the VCO outputs; finely modifying the phase of the selected VCO output; and, supplying the phase modified VCO output. In one aspect, accepting VCO outputs coarsely differentiated by phase includes: accepting a first VCO output (I0); accepting a second VCO output (I1), differentiated approximately 90 degrees from the first VCO output; accepting a third VCO output (Q0), differentiated approximately 90 degrees from the second VCO output; and, accepting a fourth VCO output (Q1), differentiated approximately 90 degrees from the third VCO output. Finely modifying the phase of the selected VCO output includes modifying the selected VCO output in the range between +45 and −45 degrees. In one aspect, the output is modified in 16 discrete steps.

Abstract: A clock generation device includes a delay-locked loop and a plurality of programmable counters. The plurality of programmable counters are coupled to delay-locked loop. Each of the programmable counters has a separate output. The delay-locked loop is configured to generate a plurality of phase delay line outputs. A hard drive includes the delay-locked loop and the programmable counters, which generate multiple timing signals such as read, write, servo, and system timing signals. The method of generating timing signals includes delaying an input signal by a programmable delay and generating a plurality of timing pulses through the programmable counters.

Abstract: A ring oscillator integrated circuit is provided that is comprised of a plurality of parallely arranged ring oscillator sections, where a ring oscillator section can be any conventional ring oscillator circuit. That is, the inputs and the outputs of a plurality of conventional ring oscillators are connected together. Since each ring oscillator section output signal includes random noise, the parallel arrangement of ring oscillators, and the summing of several oscillator signals, causes at least some noise cancellation. As a result, a lower noise oscillator signal is supplied. A method of reducing random noise in a ring oscillator circuit is also provided.

Abstract: A phase-lock loop for preventing frequency drift and jitter problems is disclosed. A phase comparator compares an input signal and a feedback signal, and outputs a control voltage according to phase difference therebetween. A voltage-controlled oscillator outputs a plurality of multiple phase oscillating signals according to the control voltage. A phase swallower receives a plurality of multiple phase oscillating signals, and generates a phase swallow signal. The phase swallow signal is formed by adding or removing one phase in the oscillating signal per predetermined number of clocks. An output frequency divider divides the frequency of the phase swallow signal so as to generate a desired output signal.

Abstract: A multiphase voltage controlled oscillator (e.g., a quadrature VCO) 100, which includes multiple voltage controllable transconductance phase drivers 102, 104, 106 and 108. The output of each voltage controllable transconductance phase driver 102, 104, 106, 108 supplies one of 4 oscillator phases and receives 2 of the 4 phases as inputs. Each of the voltage controllable transconductance phase drivers 102, 104, 106 and 108 corresponds to a pair of controllable transconductance inverting amplifiers 132, 134, 136, 138. The controllable transconductance inverting amplifiers may be a simple inverter 150 that includes N-type FET (NFET) 152 and P-type FET (PFET) 154. Transconductance is controlled in the simple inverter by raising or lowering supply voltage (Vdd) levels. A more complex controllable transconductance inverting amplifier may be used, replacing PFET 154 with series connected PFETs 164, 166. The gate of one PFET 166 is controlled by a bias control voltage VCON.

Abstract: A spurious-free fractional-N frequency synthesizer circuit is disclosed. The synthesizer circuit includes a multi-phase network circuit operative to provide output signals that are at least a 1/(2n+1)) fractional version of the input signal. The synthesizer circuit includes a phase lock loop (PLL) circuit, with the multi-phase network circuit being coupled to the negative feedback loop of the PLL. The multi-phase network circuit includes a smoothing circuit that removes any jitter present at the output of the PLL.

Abstract: A phase locked loop in an imaging system is used to generate signals on one of eight equal phase steps within a clock period. The phase locked loop outputs eight clock phases, or four clock phases and their complements, each running at the pixel rate, eliminating the need for higher speed circuitry. According to one embodiment, the phase locked loop employs an oscillator with three inverting stages and one non-inverting stage. The output of each stage is shifted in phase 45 degrees from the previous one, in terms of pixel clock rate. Differential stages are employed so that the delay of the inverting and non-inverting stage are the same. According to the present invention, the output of the last stage is swapped onto the input of the first stage, making it non-inverting without path delay, permitting oscillation with each stage's output remaining at 45 degrees of the previous stage's phase.

Abstract: An oscillator circuit for efficiently generating a triangular wave signal having multiple phases. The oscillator circuit includes capacitors, each having two terminals and having a voltage between the two terminals. The capacitors include a first capacitor. A plurality of charge/discharge switching circuits are connected to the first capacitor. Each of the charge/discharge switching circuits generates a switching signal for an associated one of the switches to control the charging and discharging of the associated capacitor. The switching signals of the charge/discharge switching circuits have different phases. Each of the charge/discharge switching circuits receives a first capacitor voltage between the terminals of the first capacitor and compares the first capacitor voltage with a first reference voltage and a second reference voltage to generate the switching signal that has a predetermined phase. A triangular wave signal is generated at one of the two terminals of each of the capacitors.

Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: An apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series, where the shift register stages shift a latched logic state in response to the oscillating signal. Further included in the apparatus is a duty cycle correcting circuit coupled to the output terminals of the shift register stages which generates each of the output signals that can be used to drive a charge pump based on the latched logic state of two of the shift register stages.

Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: Timing signal generation and distribution are combined in operation of a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means. Two-or more-phases of substantially square-wave bipolar signals arise directly in travelling wave transmission-line embodiments compatible with semiconductor fabrication including CMOS. Coordination by attainable frequency synchronism with phase coherence for several such oscillating signal paths has intra-IC inter-IC and printed circuit board impact.

Abstract: A multiphase voltage controlled oscillator (e.g., a quadrature VCO) 100, which includes multiple voltage controllable transconductance phase drivers 102, 104, 106 and 108. The output of each voltage controllable transconductance phase driver 102, 104, 106, 108 supplies one of 4 oscillator phases and receives 2 of the 4 phases as inputs. Each of the voltage controllable transconductance phase drivers 102, 104, 106 and 108 corresponds to a pair of controllable transconductance inverting amplifiers 132, 134, 136, 138. The controllable transconductance inverting amplifiers may be a simple inverter 150 that includes N-type FET (NFET) 152 and P-type FET (PFET) 154. Transconductance is controlled in the simple inverter by raising or lowering supply voltage (Vdd) levels. A more complex controllable transconductance inverting amplifier may be used, replacing PFET 154 with series connected PFETs 164, 166. The gate of one PFET 166 is controlled by a bias control voltage VCON.

Abstract: The present invention provides an improved method and apparatus for independently controlling phase and frequency using an oscillator having a plurality of stages in combination with a phase selector within a digitally controlled phase-locked loop, preferably, a read phase locked loop. The present invention provides a digitally controlled variable phase of the read timing loop in read channel integrated circuits associated with data storage devices. The phase selector has a digitally controlled fine interpolator with 12 states for further fine interpolation between at least two multiplexer phase outputs to provide a single phase output selected from a range comprising at least 2&pgr; in selectable variable phase increments of 2&pgr;/96 radian. The combined oscillator with the phase selector within a phase locked loop controls phase by exact fractional increments of equally space phases of the operating frequency within the phase locked loop, therein controlling phase at all operating frequencies.

Abstract: Electronic devices are typically coupled together to operate as systems that require the communication of data from one device to another. Many such devices include a ring oscillator, a circuit that generates one or more oscillating signals using a series of interconnected delay circuits. One problem with conventional ring oscillators concerns differences in the signal paths between the delay circuits. Accordingly, the present inventors devised several oscillators having unique layouts, which reduce differences in the signal paths between delay circuits. One exemplary oscillator includes a sequence of delay circuits having input-output connections between at least two pairs of non-adjacent delay circuits. Another exemplary oscillator provides two groups of delay circuits with a bus between the two groups, intercoupling the circuits. And, another exemplary oscillator arranges three or more delay circuits to form a closed loop.

Abstract: Apparatus for generating an oscillating signal in a desired phase relationship with an input signal, including a mixer arranged to receive a pair of reference signals oscillating at a common frequency and having a phase offset between them, and to mix the reference signals in variable proportions according to the value of input weighting signals to generate an output signal. A comparator is to compare the phase of the output signal with that of the input signal to determine whether the signals are in the desired phase relationship and, if not, to output one or more control signals indicative of the required adjustment in the phase of the output signal to achieve the desired phase relationship. An adjustable ring oscillator including a plurality of stages is connected in a ring and arranged to propagate oscillations around the ring.

Abstract: A phase-locked loop system and method are provided. The system may include an error detector configured to receive a reference signal, and a voltage-controlled oscillator subsystem coupled to the error detector. The voltage-controlled oscillator subsystem is typically configured to produce a primary output signal that tends toward a predefined frequency relationship with the reference signal, and to produce a feedback signal that is routed in a feedback loop back to the error detector. The voltage-controlled oscillator subsystem typically includes a multiple output voltage-controlled oscillator having a plurality of VCO outputs. The voltage-controlled oscillator subsystem is typically configured to form the feedback signal from a plurality of the VCO outputs.

Abstract: A quadrature oscillator for generating quadrature and differential double-frequency signals is disclosed. This oscillator is formed by PMOS and NMOS transistors, complementary devices, etc. The circuit is designed by using the differential circuit structures, two LC tanks and the technology of current reuse. As the current pass through most devices and selectively coupling the specific terminals, therefore, it has advantages of less area requirement in circuit design, low power dissipation and low phase noise of output.

Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

Abstract: An oscillator includes four identical cells each producing a phase shift of 90 degrees. The output signal from one cell is applied to the input of the next cell, and with the cells looping back to themselves. Each cell includes a current amplifier and a parallel inductance-capacitance resonant circuit configured such that the output current from one cell is a fraction of the capacitive current of the parallel resonant circuit. This causes the 90° phase shift between the input and output currents of each cell.