Abstract: A frequency synthesizer with multiple tuning loops, e.g., a fine tuning loop and a coarse tuning loop, is described. The fine tuning loop may operate over a limited tuning range and may have fine frequency resolution. The coarse tuning loop may operate over a wide tuning range and may have coarse frequency resolution. The fine tuning loop may receive a reference signal at a reference frequency and generate a fine tuning signal at a first frequency adjustable in fine steps. The coarse tuning loop may receive the reference signal, generate an output signal at an output frequency, and generate a coarse tuning signal at a second frequency based on the output signal and the fine tuning signal. The second frequency may be adjustable in coarse steps, e.g., in integer multiples of the reference frequency. The output frequency may be determined based on the first frequency and the second frequency.

Abstract: An oscillator architecture and a method for powering up/down the oscillator architecture are described. In one embodiment, an oscillator architecture includes a reference generator configured to generate reference signals and an in-phase/quadrature (IQ) oscillator configured to generate oscillation signals based on the reference signals. The reference generator includes a distributed start-up circuitry that includes multiple start-up circuits. The IQ oscillator includes at least one turbo comparator having a low power functional mode and a turbo functional mode. Other embodiments are also described.

Abstract: An oscillator architecture and a method for powering up/down the oscillator architecture are described. In one embodiment, an oscillator architecture includes a reference generator configured to generate reference signals and an in-phase/quadrature (IQ) oscillator configured to generate oscillation signals based on the reference signals. The reference generator includes a distributed start-up circuitry that includes multiple start-up circuits. The IQ oscillator includes at least one turbo comparator having a low power functional mode and a turbo functional mode. Other embodiments are also described.

Abstract: The invention discloses a dual frequency multiplexer by which a first and second coaxial harmonic oscillator type band pass filters are disposed in a box. The box includes a base body, a cover plate and a cover body. The two coaxial harmonic oscillator type hand pass filters are located on the base body and spaced each other by a metal plate; the multiplexer port, first and second ports are positioned on lateral side of the base body. The blocking capacitors are contained in the coaxial chamber of the two coaxial harmonic oscillator type band pass filters. The cover plate is secured on the base body; the first and second direct current circuits are placed on the cover plate; the low pass filters of the first and second direct current circuits are fixed on an edge of a top surface of the coaxial chamber by means of a support member; the cover body and the base body are fastened with each other. The blocking capacitors each are of distributed parameter capacitor.

Abstract: A radio circuit may be driven by a high frequency oscillator such as a crystal oscillator that may have sleep and wake time intervals. The sleep time interval length may be adjusted. A low frequency oscillator or low power oscillator (LPO) that may experience frequency drift may regulate the sleep and/or wake time intervals. The frequency drift may be detected based on two or more LPO calibrations and/or one or more clock adjustments. The LPO frequency drift may be detected based on an LPO frequency sampled after a first LPO calibration and a corresponding LPO clock adjustment, a second LPO frequency sampled after a second LPO calibration and a time interval between the two frequency samples. The LPO may be calibrated based on the HFCXO output. Sleep time intervals may be adjusted by adding and/or subtracting a time interval to an expected time to wake the radio circuit.

Abstract: A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator.

Abstract: An integrated circuit (IC) with a low temperature coefficient and an associated calibration method are provided to lower the effect of the environmental temperature on the IC and at the same time to maintain the small area and low power consumption of the IC. The IC includes a first circuit, a second circuit and a calibration control circuit. The first circuit has a low temperature coefficient and generates a first output. The second circuit has a high temperature coefficient and generates a second output. The calibration control circuit detects the first and second outputs, and compares the first and second outputs according to a predefined relationship therebetween so as to generate an adjusting signal. The adjusting signal is for adjusting the second circuit such that the second circuit can have the characteristic of the low temperature coefficient.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.

Abstract: Phase locked loop based frequency tuning of an adjustable filter is disclosed. A resonant circuit includes the adjustable filter, and an oscillator signal provides an input to the resonant circuit.

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: A multi-phase voltage-control oscillator including a first voltage-control oscillator circuit and a second voltage-control oscillator circuit is provided. The second voltage-control oscillator circuit and the first voltage-control oscillator circuit have a plurality of inductors, and the inductors in the second voltage-control oscillator circuit are respectively cross-coupled with the inductors in the first voltage-control oscillator circuit to generate a mutual inductance effect, so as to output a plurality of oscillating signals with different phases.

Abstract: A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.

Abstract: In a multi-radar system, configured comprising a plurality of radar units which generate and output signals the frequency of which increases and decreases periodically, each radar unit generates and outputs signals synchronized with a prescribed sync signal, such that the upper limit and lower limit of the periodically increasing and decreasing frequency is different for the signals of each radar unit, and moreover the timing of the upper limit and lower limit of the signals substantially coincide. By this means, the frequency intervals between signals can be reduced, and more channels can be set, without causing radio wave interference.

Abstract: An oscillator circuit has a crystal oscillator amplifier having only two clock input terminals, one being an input terminal and the other being an output terminal. The input terminal allows a user of the integrated circuit to choose between connecting a first clock signal generated from a crystal or a second clock signal generated by a non-crystal source to the input terminal. Control circuitry has a capacitor coupled in parallel with a transistor. Both are coupled in series with a resistive device at an output of the control circuitry to provide a control signal. Clock generation circuitry coupled to the crystal oscillator amplifier provides an oscillating output signal in response to an enable signal. In one form a comparator circuit provides the oscillating output signal. The control signal is used to ensure that inputs to the comparator circuit repeatedly cross each other over time.

Abstract: A local oscillator communicates a signal of relatively low frequency across an integrated circuit to the location of a mixer. Near the mixer, a frequency-multiplying SubHarmonically Injection-Locked Oscillator (SHILO) receives the signal and generates therefrom a higher frequency signal. If the SHILO outputs I and Q quadrature signals, then the I and Q signals drive the mixer. If the SHILO does not generate quadrature signals, then a quadrature generating circuit receives the SHILO output signal and generates therefrom I and Q signals that drive the mixer. In one advantageous aspect, the frequency of the signal communicated over distance from the local oscillator to the SHILO is lower than the frequency of the I and Q signals that drive the mixer locally. Reducing the frequency of the signal communicated over distance can reduce power consumption of the LO signal distribution system by more than fifty percent as compared to conventional systems.

Abstract: LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

Abstract: Methods and systems to provide digitally controlled crystal oscillators are disclosed. One example method includes determining a state of an oscillator system and selecting a first output of a digitally controlled crystal oscillator or a second output of a second oscillator based on the determination. In an example implementation, the second oscillator is a ring oscillator.

Abstract: A self-calibrating temperature compensated oscillator includes a monolithic structure having a first resonator, a second resonator, and a heating element to heat the first and second resonators. The temperature coefficient of the second resonator is substantially greater than the temperature coefficient of the first resonator. A first oscillator circuit operates with the first resonator and outputs a first oscillator output signal having a first oscillating frequency. A second oscillator circuit operates with the second resonator and outputs a second oscillator output signal having a second oscillating frequency. A temperature determining circuit determines the temperature of the first resonator using the second oscillating frequency. A temperature compensator provides a control signal to the first oscillator in response to the determined temperature to adjust the first oscillating frequency and maintain it at a desired operating frequency.

Abstract: A radio circuit may be driven by a high frequency oscillator such as a crystal oscillator that may have sleep and wake time intervals. The sleep time interval length may be adjusted. A low frequency oscillator or low power oscillator (LPO) that may experience frequency drift may regulate the sleep and/or wake time intervals. The frequency drift may be detected based on two or more LPO calibrations and/or one or more clock adjustments. The LPO frequency drift may be detected based on an LPO frequency sampled after a first LPO calibration and a corresponding LPO clock adjustment, a second LPO frequency sampled after a second LPO calibration and a time interval between the two frequency samples. The LPO may be calibrated based on the HFCXO output. Sleep time intervals may be adjusted by adding and/or subtracting a time interval to an expected time to wake the radio circuit.

Abstract: Timing calibrator is disclosed. A first oscillator includes an output. The first oscillator includes a mechanically resonant element. A second oscillator includes an output. The second oscillator includes a quartz resonator. A frequency relater has an output, a first input, and a second input. The frequency relater has the first input coupled to the first oscillator output and the second input coupled to the second oscillator output.

Abstract: Aspects of a method and system for frequency tuning based on characterization of an oscillator are provided. In this regard, a frequency of an oscillator in an integrated circuit may be controlled based on a first digital control word, a frequency of a tuned circuit may be controlled based on a second digital control word, and the second control word may be determined utilizing a mapping between the first control word and the second control word. The frequency of the oscillator and the tuned circuit may be controlled by adjusting a capacitance of the oscillator and tuned circuit, respectively. The mapping may be based on a relationship between the oscillator and the tuned circuit, such as logical and/or mathematical relationship between the capacitance of the oscillator and the capacitance of the tuned circuit and/or the relationship between the frequency of the oscillator and the frequency of the tuned circuit.

Abstract: An object of the invention is to provide a multiplying oscillator capable of generating a high frequency signal by small circuit scale and power consumption in an oscillator for generating a signal with a frequency of a microwave band or more, and a local oscillator using this multiplying oscillator. A multiplying oscillator of the invention obtains a frequency signal four times or more a fundamental wave by adding a frequency adjusting unit 40 having a function of suppressing second harmonic of the fundamental wave to a resonance unit 20 in a multiplying oscillator which constructs an oscillator for connecting two negative resistance units 10 to 11 to the resonance unit 20 and generating a signal A and a signal B of mutually opposite phases in the fundamental wave and synthesizes the signal A and the signal B in phase in a synthetic unit 30 and obtains an oscillation signal output.

Abstract: Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, on injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one.

Abstract: Embodiments of the invention may provide for an LC quadrature oscillator that includes two LC oscillators that are cross-coupled with each other to generate I/Q clock signals and a phase and amplitude mismatch compensator. The phase and amplitude mismatch detector may include an amplitude mismatch detector, a transconductor, and a capacitor for compensating for both phase and amplitude mismatches between I/Q clock signals generated in the LC quadrature oscillator.

Abstract: A real time clock assembly includes paired crystal oscillators that experience changes in frequency responsive to temperature. The differences in frequency changes between the paired crystal oscillators are utilized to determine a temperature utilized to compensate for those shifts in frequency. The predictability of frequency responsive to temperature variations by the paired crystal oscillators is utilized for the determination of temperature.

Abstract: Determination and processing for fractional-N programming values. The present invention is operable to receive a clock signal (CLK) and to transform that CLK into a new CLK, when necessary, for use by various circuitries within a system. The present invention is operable to generate two different CLKs for use by a radio frequency (RF) circuitry and a baseband processing circuitry in certain embodiments. The present invention employs a measurement circuitry and to characterize a first CLK and uses a fractional-N synthesizer to perform any necessary processing to generate the one or more CLKs to the other CLKs within the system. The first CLK may be received from an external source or it may be generated internally; in either case, the present invention is able to modify the CLK into another CLK for use by other circuitries within the system or for use by another external device.

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Abstract: A multi-phase voltage-control oscillator including a first voltage-control oscillator circuit and a second voltage-control oscillator circuit is provided. The first voltage-control oscillator circuit includes a first LC tank and a first inductor assembly unit. The second voltage-control oscillator circuit includes a second LC tank and a second inductor assembly unit. A mutual inductance effect is generated between the inductors of the first voltage-control oscillator and the inductors of the second voltage-control oscillator.

Abstract: A magnetron (2), a launcher (4) which extracts the output power of the magnetron (2), an impedance generator (5) having one terminal connected to the output terminal of the launcher (4), and a reference signal supplier (6) connected to the other terminal of the impedance generator (5) are included. The reference signal supplier (6) supplies, to the magnetron (2), a reference signal lower in electric power and stabler in frequency than the output from the magnetron (2). The oscillation frequency of the magnetron (2) is locked to the frequency of the reference signal by injection of the reference signal. The impedance generator (5) can reduce the change width of the oscillation frequency of the magnetron (2) by adjusting the load impedance of the magnetron (2). This implements a magnetron oscillator (1) which has high frequency stability and does not fluctuate the frequency even when the output power is changed.

Abstract: Noise generation is reduced further. Oscillation control circuit 11 generates a modulation signal modulating oscillation frequency of an oscillation signal generated by oscillation circuit 12 and outputs modulation signal to same. Preferably, the modulation signal fluctuates period of the oscillation signal sequentially. The oscillation circuit 12 is composed of a ring oscillator, for example, and the power supply voltage or power supply current of the ring oscillator is controlled to fluctuate sequentially by the modulation signal output from the oscillation circuit 11. Buffer 14 of charge pump circuit 13 generates signals /? and ? by the oscillation signal and drives capacitors C1 and C2 for supplying a higher voltage than the voltage of the power supply Vcc to gate of N-channel MOSFET Q1.

Abstract: A startup circuit 200 and method 700 is provided for quickly starting up a resonator based oscillator. Tunable oscillator 201 provides an impetus signal to oscillator 205 through capacitor 202. The impetus signal has a frequency that is an estimate of the resonant frequency of resonator 205. The circuit measures the frequency of oscillator 204 and the frequency of tunable oscillator 201. The circuit then adjusts the frequency of tunable oscillator 201 such that the frequency of the tunable oscillator is substantially equal to the resonant frequency of the resonator 205 and stores a data state necessary for the tunable oscillator 201 to generate a signal with this target frequency in the future. During an ensuing startup cycle the stored data state causes the impetus signal delivered by tunable oscillator 202 to be substantially equal to the target frequency of oscillator 204 which improves startup performance.

Abstract: Signals outputted from oscillators (1-1, 1-2, . . . 1-n) are in phase with signals as reflected by band elimination filters (3-1, 3-2, . . . 3-n) at elimination frequencies of the band elimination filters (3-1, 3-2, . . . 3-n), while they are in opposite phase with signals leaked from the corresponding band elimination filters (3-1, 3-2, . . . 3-n). In this way, a stable oscillation can be performed with the oscillation frequencies of the oscillators (1-1, 1-2, . . . 1-n) balanced as optimum frequencies between the natural frequencies of the oscillators (1-1, 1-2 , . . . 1-n) and the elimination frequencies of the band elimination filters (3-1, 3-2, . . . 3-n), while the oscillators (1-1, 1-2, . . . 1-n) can be synchronized with the elimination frequencies being used as reference frequencies.

Abstract: A first receiver frequency reference is passively coupled to a second receiver by tapping a signal directly from the resonant element, such as a crystal, of an oscillator in the first receiver to drive the input of the second receiver. The sinusoidal signal from the resonant element is relatively free of harmonics and minimizes interference that could be caused by harmonics of a square wave signal coupling or an amplified signal. The oscillator of each receiver can be selectively enabled or disabled to allow the receiver to either generate or receive the frequency reference. This technique of coupling can be used to couple a frequency reference signal between integrated circuit receivers.

Abstract: The clock signal output device has a crystal oscillator for generating a reference clock signal and generating and outputting an output clock signal having a prescribed frequency on the basis of the reference clock signal. The device also has an atomic oscillator for generating a clock signal having higher precision than a crystal oscillator, an intermittent time management unit for intermittently driving the atomic oscillator, and a correction unit for receiving correction data for correcting the offset amount of the output clock signal on the basis of a clock signal each time the atomic oscillator is driven, and correcting the output clock signal on the basis of the correction data.

Abstract: An apparatus for reading out a differential capacity with a first and second partial capacity includes a first oscillator having a first frequency-determining element connectable to the first partial capacity and a second oscillator having a second frequency-determining element connectable to the second partial capacity; a switching means to switch the first frequency-determining element into a first state or to switch it into a second state, and to switch the second frequency-determining element into a third state or to switch it into a fourth state; read apparatus having a first detection means connected to the first oscillator; and an evaluation means which carries out a quotient formation to obtain a value indicating a quotient of the first and the second partial capacity.

Abstract: Circuits and methods for compensating a variable oscillator for process and/or operational variations. The circuit generally comprises (a) a replica oscillator, (b) a counter configured to count pulses of the replica oscillator and to produce a count signal, and (c) a compensation circuit configured to provide an adjustment signal to the variable oscillator in accordance with the count signal. The method generally comprises the steps of (a) counting the number of pulses of a replica oscillator signal, and (b) providing an adjustment signal to the variable oscillator in accordance with the number of pulses counted. The present invention advantageously provides a largely digital method to compensate a variable oscillator for process, voltage, and temperature variations.

Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit forming part of the transmission PLL circuit is configured to be operable in a plurality of bands. A circuit for measuring the oscillating frequency of the oscillator circuit forming part of the transmission PLL circuit is also used for measuring the oscillating frequency of the oscillator circuit forming part of the reception PLL circuit or for measuring the oscillating frequency of the oscillator circuit for the intermediate frequency.

Abstract: A redundant-source clock generator has only two oscillators, rather than three oscillators. A secondary oscillator is phase-locked to a primary clock from a primary oscillator using a phase detector, charge pump, and filter that generate a control voltage to the secondary oscillator that determine the frequency of a secondary clock. The primary clock is compared to the secondary clock to detect primary clock failure. When clock failure is detected, a mux is switched to select a delayed secondary clock rather than a delayed primary clock to output as a system clock. Since the mux receives delayed clock signals, clock-failure detection has additional time to detect the clock failure before the clock failure is propagated through the mux. When the primary oscillator fails and the clock failure is detected, the phase detector stops comparing a feedback secondary clock to the primary clock and instead holds the control voltage steady.

Abstract: A weighing apparatus includes a SAW oscillator and a “push oscillator” to force the SAW oscillator into a desired mode of operation. A SAW temperature oscillator and a thermistor are also provided. The frequency of the “push oscillator” is made immune to temperature changes by generating it via a mixer mixing the SAW temperature oscillator with an adjustable fixed frequency oscillator. Long term stability of the SAW temperature oscillator is achieved by periodic calibration with the thermistor.

Abstract: A method and system for fast wakeup of a high-Q oscillator (300) that includes a resonating element (304), preferably a crystal resonator (304), and an amplifier (310). The method comprises connecting the resonating element (304) to a fast wakeup, low-Q oscillator (302), inputting a plurality of pulses generated by the low-Q oscillator (302) into the resonating element (304), and simultaneously disconnecting the resonating element (304) from the low-Q oscillator (302) while connecting the resonating element (304) to the amplifier (310), thereby obtaining substantially uniform steady state oscillations in the high-Q oscillator. The system (300) includes in addition to high-Q and low-Q oscillator elements a mechanism for counting the pulses (312) and for performing the simultaneous disconnection and connection mentioned above.

Abstract: A method of analysis of a time interval between two selected measurement edges of interest includes locking a plurality of at least three substantially interchangeable oscillators to a common reference frequency, the oscillators containing digital locked-loop (DLL) circuit architecture. The method includes operating one oscillator as a timebase oscillator, and operating the other oscillators as edge-resettable measurement oscillators. The method further includes coupling one oscillator with a switched and physically-immutable parametric variation, producing an offset in the frequency of the coupled oscillator relative to the frequency of the other oscillators.

Abstract: The invention relates to the field of electronics and more particularly to the tuning and injection locking of voltage controlled oscillators (VCOs). An improved injection locking circuit is provided which allows the VCO to injection lock with a smaller reference signal and therefore a smaller locking bandwidth (LBW). In order to allow the VCO to injection lock with a lower power reference signal, this invention includes a pre-tuning algorithm to place the VCO frequency such that the desired frequency is in the LBW. Tuning of the VCO is achieved using direct digital tuning that does not require an input reference. Injection locking is performed using a low frequency clock harmonic as the reference signal. More specifically, tuning is accomplished by sub-sampling and digitizing the output signal of the VCO, determining the center frequency, and adjusting the VCO control voltage.

Abstract: Briefly, devices and methods for tuning of quadrature oscillators which may be used, for example, in a Complementary Metal-Oxide Semiconductor (CMOS) process. Devices and methods in accordance with some exemplary embodiments of the invention may allow, for example, improved locking, tuning and performance of slave oscillators and a master oscillator within a quadrature oscillator utilizing injection-locking.

Abstract: Clock signals and digital data signals at a variable frequency are introduced to the input of a FIFO and are passed from the FIFO at a second (or intermediate) frequency controlled by a numerically controlled oscillator. To regulate the frequency of the signals from the numerically controlled oscillator, the phases of the clock signals at the variable frequency are compared in a phase detector with the phases of the signals from the numerically controlled oscillator to generate an error signal. The error signals and the signals at a fixed sampling frequency higher than the intermediate frequency regulate the frequency of the signals from the numerically controlled oscillator and thus the frequency of the digital data signals from the FIFO. The digital data signals from the FIFO are converted to a pair of signals at the second frequency.

Abstract: A mobile radio communications device has a first crystal oscillator for providing a first master clock frequency for the timebase of a first communications system, a second crystal oscillator for providing a second master clock frequency for the timebase of a second communications system, and a phase locked loop connected between the first and second crystal oscillators and arranged to lock the first and second crystal oscillators together so that the two timebases cannot drift.

Abstract: A quadrature oscillator includes a master tuned oscillator and two injection-locked slave tuned oscillators.

Abstract: A voltage-controlled oscillator includes a control terminal having a control voltage applied thereto, first and second output terminals, first and second ring oscillators, first and second output buffer circuits, and a latch circuit. The first and second ring oscillators include odd numbers of inverting amplifier circuits in series, a transfer gate circuit connected between the inverting amplifier circuits, and a resistor connected in parallel to the transfer gate circuit. The transfer gate circuit includes a transfer transistor connected between the inverting amplifier circuits, and has a transistor control terminal connected to the control terminal. The first and second output buffer circuits have inputs connected to the first and second ring oscillators, and outputs connected to the first and second output terminals. The latch circuit is connected to the first and second ring oscillators. The latch circuit controls the first and second ring oscillators to output complementary oscillation signals.

Abstract: In the field of direct mind-machine interactions, prior art devices and methods do not provide sufficiently fast and reliable results. Mental influence detectors (100, 140, 400, 430) and corresponding methods provide fast and reliable results useful for detecting an influence of mind and hidden or classically non-inferable information. An anomalous effect detector (100) includes a source (104) of non-deterministic random numbers (110), a converter (114) to convert a property of numbers, a processor to accept converter output (118) and to produce an output signal (124) representative of an influence of mind. The processor output signal (124) contains fewer numbers than the input (110).