Abstract: A circuit separately measures a selected one of the rising-edge and falling-edge signal propagation delays through one or more circuits of interest. A number of synchronous components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component clocks a subsequent synchronous component in the ring; the subsequent synchronous component responds by clocking a later component in the ring and by clearing a previous component to prepare it for a subsequent clock. The oscillator thus produces an oscillating test signal in which the period is proportional to the clock-to-out delays of synchronous components. This proportionality provides an effective means for measuring the clock-to-out delays of those components. Other embodiments include additional asynchronous test circuit paths for which the associated signal propagation delays are of interest.

Abstract: An oscillation circuit stops the oscillation of an external oscillator to reduce the current consumed when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. A PLL circuit 37 generates a second clock 45 from a first clock 23 output by an oscillation circuit 1. A PLL lock signal 47 is changed from a first level to a second level when the second clock 45 is generated. A selector 39 outputs the second clock 45 as an internal clock 13 when the PLL lock signal 47 is at the second level. The operation of an oscillator 9 is stopped when the PLL lock signal 47 is at the second level.

Abstract: An oscillating circuit includes a low power inverting amplifier (10) having an input (208) and an output (209) and having a relatively high resistance d.c. biasing path (2) associated therewith. A relatively low resistance path (3) can be switched so as to couple the amplifier input (208) and output (209) together during a bias settling phase of the circuit. A detector (50) detects the voltage at either the amplifier input (208) or the output (209) and switches the relatively low resistance path (3) so that it does not couple the input (208) and output (209) together when the detected voltage reaches a level just before a required operating voltage level.

Abstract: A precision oscillator circuit having a wide adjustable operating frequency range and an adjustable duty cycle. The precision oscillator use a window comparator circuit for monitoring a voltage of a capacitive element. The window comparator circuit has a first operating voltage edge and a second operating voltage edge wherein the first operating voltage edge latches an output signal of the window comparator circuit at one level when the voltage of the capacitive element is greater than the first operating voltage edge. The second operating voltage edge brings the output signal of the window comparator circuit back to an initial level when the voltage of the capacitive element is greater than the second operating voltage edge. A precision current reference source is coupled to the capacitive element and to the window comparator circuit. The precision current reference is used for generating currents which are insensitive to temperature, supply voltage, and process variations.

Abstract: To provide a PLL circuit with little jitter and a minimum frequency drawing time, a PLL circuit comprises: a phase comparator for generating an up-down signal, which is turned to logic HIGH when a reference clock signal is phase-advanced to an output clock signal and a phase lock signal, indicating synchronization of the output clock signal to the reference clock signal; a timing signal generator for generating a timing signal when the phase lock signal is generated for a certain period after said timing signal generator is initialized with a reset signal; an up-down counter for generating a count value which is incremented when the up-down signal is at logic HIGH and decremented when the up-down signal is at logic LOW according to each pulse of a count clock, memorizing the count value in a nonvolatile memory when controlled by the timing signal, and outputting the memorized count value when initialized by the reset signal; a D/A converter for outputting a control voltage in proportion to the count value; an

Abstract: A ring oscillator includes a set of metal-oxide-semiconductor (MOS) complementary, inverting stages, wherein each stage includes a pair of cross-coupled CMOS NAND or NOR gates. The first and last stages are also cross-coupled, such that positive and negative output signals of the last stage are connected respectively to negative and positive input signals of the first stage.

Abstract: A data decoding circuit of the present invention can regenerate a bit synchronization signal from a data received by using a code such as a split-phase code and Manchester code in which a binary value can be detected through a transition of voltage at a central area of a bit cell and transform the received data into a serial binary data. The data decoding circuit includes an edge detection section for detecting a transition point in the received data; a pulse generating section for generating a phase comparing timing signal having a pulse width of substantially 1/(4.times.fs) when fs is a data transfer frequency and a received data regenerating signal having a pulse width of substantially 1(2.times.

Abstract: A kinetically multicolored light source is described, comprising: a light source capable of producing a plurality of primary colors; oscillatory means for driving said light source; and means for moving said light source. The oscillatory driving means may drive the light source so that one or more of the primary colors is alternately turned on and off at a frequency above the critical fusion frequency of an observer, whereby each of the colors appears to emanate simultaneously and continuously thereby appearing to the observer as a single secondary color when the light source moves slowly with respect to the observer.The light source may move relative to the observer sufficiently rapidly that each of the oscillating primary colors if viewed alone would appear to the observer to emanate from bright segments of a curvilinear path with intervening dark segments.

Abstract: A dual-multivibrator circuit using a pair of mutually triggering multivibrator sections is connected to operate in a free-running mode when no external synchronization signal is applied to the circuit input, and in synchronism with a master pulse train of substantially the same pulse repetition rate when such a master pulse train is applied to the circuit input.

Abstract: A CMOS inverter capable of reducing a through current therein including an E-type PMOS transistor, an E-type NMOS transistor and a D-type NMOS transistor. In the E-type PMOS transistor, the gate and the drain are connected to input and output terminals. In the E-type NMOS transistor, the gate and the drain are connected to the input and the output terminals and the source to the ground. In the D-type NMOS transistor, the source is connected to the source of the E-type PMOS transistor, the gate to the ground, and the drain to a power source.

Abstract: An astable multivibrator comprising a capacitor connected between a first output signal and a third output signal, an amplification circuit connected between the first and third output signals, a delay for delaying a signal logic-converted from the first output signal and for outputting a second output signal, and a variable resistor connected between the first output signal and an output node of the delay. High frequency oscillation performance is enhanced and a larger voltage operating range is obtained by excluding the effect of feedback current.

Abstract: A voltage controlled ring oscillator having a reduced voltage controlled oscillator (VCO) gain by controlling only the fall time of the period of the VCO using integrated circuits and logic circuits. The VCO includes a mixer/inverter circuit, a logic circuit, a delay/inverter circuit, a first delay circuit, a second delay circuit, and a third delay circuit. The VCO gain is reduced by controlling only one pulse width of the logic level High and one pulse width of the logic level Low of the oscillating period. Furthermore, the VCO can be logically controlled by using a simple logic circuit as a component of the VCO.

Abstract: An oscillating circuit body 10 includes a first two-input NAND gate, a feedback resistor, a resonator and capacitors. One input terminal of the NAND gate functions as a control terminal to which is applied a first control signal to perform on-off control of oscillation operation of the circuit body. An output terminal of the circuit body is connected to an input terminal of a second two-input NAND gate via two inverters. The other input terminal of the second NAND gate is connected to a control terminal to which a second control signal is applied. The second NAND gate is used for masking the oscillatory output in response to the second control signal for a predetermined period, and the output from the second NAND gate is provided as a final clock output.

Abstract: A quadrature oscillator is provided constructed of NOR gates in the manner of a non-linear circuit which is inherently unstable and which cycles sequentially through four distinct states at a rate determined by the constitution of the NOR gates. The quadrature oscillator includes first and second stages that each include first and second NOR gates. The output of the first NOR gate of the first stage is connected as an input to the second NOR gate of each of the first and second stages. The output of the second NOR gate of the first stage is connected as an input to the first NOR gate of each of the first and second stages. The output of the first NOR gate of the second stage is connected as an input to the first NOR gate of the first stage and the second NOR gate of the second stage. The output of the second NOR gate of the second stage is connected as and input to the second NOR gate of the first stage and the first NOR gate of the second stage.

Abstract: A low power consumption oscillator circuit. The oscillator circuit comprises a capacitor coupled to a first resistor that is capable of delaying discharge of the capacitor. The oscillator circuit further comprises a first inverter coupled to the capacitor and having a first input. The first inverter is capable of applying charge to the capacitor when a first voltage potential on the first input is above a first threshold voltage of the first inverter. The first inverter is capable of removing charge from the capacitor when a second voltage potential on the first input is below a second threshold voltage of the first inverter. The oscillator circuit further comprises threshold detection circuitry having a second circuitry is coupled to the first input of the first inverter, and the second input is coupled to the capacitor.

Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.

Abstract: An oscillation circuit is disclosed, which comprises an input stage, intermediate stage and output stage circuits which are coupled to one another. The input stage circuit is composed of a hysteresis inverter having a first threshold value and a second threshold value that is set between the first threshold value and the potential of a first power supply. The intermediate stage circuit includes an inversion circuit and a delay circuit that is provided between the hysteresis inverter and the inversion circuit. The output stage circuit includes an output terminal connected to the hysteresis inverter, a capacitor provided between the output terminal and the first power supply and an inverter circuit connected to the inversion circuit. The inverter circuit controls the charging and discharging of the capacitor to generate an oscillation output signal at the output terminal.

Abstract: A ring oscillator for circulating pulse edges of two types therein includes an even number of inverting circuits connected in a ring. Each of the inverting circuits is operative to invert an input signal and output an inversion of the input signal. One of the inverting circuits is a first start inverting circuit which starts an operation of inverting an input signal in response to a first control signal applied from an external input. One of the inverting circuits except the first start inverting circuit and an inverting circuit immediately following the first start inverting circuit is a second start inverting circuit which starts an operation of inverting an input signal in response to a second control signal.

Abstract: High-frequency, low-power CMOS oscillators having electrically-tunable tank circuits are disclosed. Electrically-tunable inductors assure highly efficient oscillator operation and can be adjusted after manufacture to assure high yields of high-precision oscillator circuits.

Abstract: A CMOS coupled-tank oscillator for VLSI circuit applications is disclosed. The coupled-tank oscillator has two inverters coupled, input-to-output, by inductances that may be simply wires, and a capacitance acting in parallel with each inverter that may be, simply, the invert's gate capacitance. The invention permits 0.9-micron CMOS oscillators to produce high-frequency signals.

Abstract: This invention relates to oscillators employing a primary feedback network and a high pass filter feedback network. The feedback networks are connected between the input and output of a of a high signal gain amplifier system. The primary feedback network provides positive feedback to cause oscillation to occur and also determines the nominal frequency of oscillation. The high pass filter feedback network provides a negative feedback signal that controls the rise and fall time of the amplifier system's output signal. By varying the output signal's rise and fall time the frequency of oscillation is also changed. The high signal gain amplifier system operates with one or more amplifier stages in the non-linear region to produce a significantly distorted sine wave or pulse output signal.

Abstract: An oscillator circuit having an amplifier and feedback loop multiplies a generated signal by appropriate selection of capacitance ratios in the feedback loop. In order to isolate this multiplied, high voltage signal, a voltage divider is used to isolate the high voltage portion from the input and output (I/O) of an integrated circuit oscillator core. The multiplied voltage creates a high voltage signal suitable for stylus signal transmission. The divided, and relatively low, voltage is used in the feedback path to stabilize the oscillator core's operation.

Abstract: An oscillator containing a chain of delay components (10.1, . . . , 10.l) and emitting an output signal, the period T of which substantially corresponds to the total delay of the chain. The oscillator has a logic stage (11) to which are applied signals which can be tapped along the chain or generated by additional means. The logic stage affects the input signal of the first delay component (10.1) in the chain. The oscillator may be used as part of a phase detector.

Abstract: A voltage controlled oscillator (VCO) (23) includes a periodic signal generator (30) such as a comparator (42)followed by a latch (43), and a logic gate such as a NAND gate (31) connected to the output of the latch (43) to adjust for asymmetries in the output signals from the latch (43). In one embodiment, the NAND gate (31) includes two pullup transistors (80, 81) receiving first and second output signals from the latch and connected between a first power supply voltage terminal and an output node (86). Two switching branches (82, 83 and 84, 85) each including two transistors are connected between the output node (86) and a second power supply voltage terminal. The order of the input signals received by the two transistors is reversed between the two switching branches (82, 83 and 84, 85) to compensate for any duty cycle asymmetries. A frequency divider (32) divides the output of the NAND gate (31) to complete the duty cycle adjustment.

Abstract: A serial data clock receiver circuit (11) is provided that synchronizes a clock signal to data. The serial data clock receiver circuit (11) comprises a control circuit (21), a dual oscillator circuit (19), and a phase locked loop circuit (22). The control circuit (21) arms the dual oscillator circuit (19) for being enabled during an idle period. The phase locked loop circuit (22) provides a reference voltage for the dual oscillator circuit (19). The dual oscillator circuit (19) is responsive to both the data and control circuit (19) for providing a clock signal.

Abstract: A ring oscillator for circulating pulse edges of two types therein includes an even number of inverting circuits connected in a ring. Each of the inverting circuits is operative to invert an input signal and output an inversion of the input signal. One of the inverting circuits is a first start inverting circuit which starts an operation of inverting an input signal in response to a first control signal applied from an external input. One of the inverting circuits except the first start inverting circuit and an inverting circuit immediately following the first start inverting circuit is a second start inverting circuit which starts an operation of inverting an input signal in response to a second control signal.

Abstract: A programmable VCO circuit (300, 700) and method of use are provided whereby a current proportional to the strength of the NMOS process used to fabricate the circuit may be subtracted from the control current derived at the circuit's input, to compensate for process variations. Also, a programmable VCO circuit (300) and method of use are provided whereby a current developed from one-half the supply voltage for the VCO circuit may be subtracted from the control current derived at the circuit's input, in order to cause programmed gain changes to occur about the center of the control voltage range, and minimize output "jitter" when the VCO is used in a phase-locked loop. A gain compensation circuit (800) is also provided to linearize the gain of the programmable VCO circuit (300) for higher control voltage levels and thereby extend the VCO's effective operating range.

Abstract: A circuit and method for minimizing electromagnetic emissions which employ a cancellation signal to produce electromagnetic fields which are opposites of the fields produced by the digital circuit. The circuit and method of the present invention are particularly suited for use in digital systems which produce constant-frequency and constant-amplitude clock signals for driving a circuit load. The circuit includes a cancellation circuit for producing the cancellation signal, which may include the same oscillator used to produce the clock signal. An amplitude-adjust circuit adjusts the amplitude of the cancellation signal, and a phase-adjust circuit adjusts the phase of the cancellation signal.

Abstract: A high-voltage generating circuit suitable for a light receiving circuit includes a pulse oscillating circuit, a current drive circuit, a first capacitor, a second capacitor, a Cockcroft-Walton circuit, a low-pass filter. The pulse oscillating circuit produces a train of repetitive pulses. The current drive circuit produces a train of repetitive pulses which are in phase opposite to the train of repetitive pulses. The first capacitor couples the current drive circuit with the first input terminal of the Cockcroft-Walton circuit. The second capacitor couples the pulse oscillating circuit with the second input terminal of the Cockcroft-Walton circuit. The Cockcroft-Walton circuit boost the pulse voltage applied between the first and second inputs to produce a high direct current voltage. The low-pass filter removes the ripple components of the high direct current voltage. The Cockcroft-Walton circuit can be formed with a small number of circuit components.

Abstract: A gain stage for providing an automatic phase shift is provided. In particular, the gain stage detects whether an oscillation signal appears at its inputs. If an oscillation signal is not detected, then the gain stage inverts output signals occurring at outputs of a first amplifier before being respectively applied to inputs of a second amplifier. This has the overall effect of implementing a 180.degree. phase shift of a signal appearing at the outputs of the gain stage with respect to a signal appearing at the inputs of the gain stage.

Abstract: A circuit is provided for an oscillator circuit comprising a differential amplifier such as an ECL line receiver which directly, in one step outputs a symmetrical square wave signal. This is obtained by means of a symmetrical connection of the bias voltage to the input terminals of the ECL-line receiver through two substantially equally large resistors. A feedback loop comprises, as is conventional, a crystal and a trimming capacitor or a capacitor which may be controlled in some other way as well as a resistor. The capacitor will together with the resistor form a low-pass filter for the control of the oscillating condition of the circuit. Further, an overtone synthesizer is provided adapted to generate even multiples of the frequency of an input signal and it comprises a second ECL line receiver, the positive and negative output terminals of which are directly connected to each other.

Abstract: Low power oscillator circuits for providing clock signals. The circuits comprise crystal oscillators for providing an input wave form of a specified frequency to the clock circuit, square wave generators having at least two input terminals wherein one of the two input terminals is coupled to the oscillator, and a power output network coupled to the square wave generator for outputting a substantially square wave having substantially the same frequency as the input wave form, the power output network being biased at a high voltage level. Clock circuits described herein provide the advantage of low power oscillation with little power dissipation.

Abstract: A topology for a high speed voltage controlled oscillator (VCO) with quadrature outputs is produced utilizing four inverting differential circuits. The fully differential four stage ring oscillator has outputs from alternate delay circuits combined in balanced exclusive OR gate frequency doublers to provide both in-phase and quadrature output signals at twice the ring oscillator frequency. The period of the quadrature delay signals is four gate delays and is easily realized in the Ghz frequency ranges. The in-phase and quadrature output signals are again combined in a balanced exclusive OR gate frequency doubler to obtain a final output frequency quadruple the ring oscillator frequency.

Abstract: A voltage-controlled oscillator capable of very high ratios of modulation to oscillation frequency is disclosed embodying a resonant circuit with an inductance and two tuning diodes connected with opposite polarity in series across the inductance, a cross-coupled feedback amplifier circuit with two matched MMIC inverting amplifiers capacitively cross-coupled to the resonant circuit for driving the resonant circuit into oscillation at its resonant frequency to produce an output carrier wave, and a transmission line resonator connected to the resonant circuit between the tuning diodes to couple a wide band frequency modulating voltage thereto for modulating the output carrier wave.

Abstract: Disclosed is a power system for use with a computer, the power system having incorporated in its circuitry for automatically varying the supply voltage output to the computer system based upon the magnitude of the current being supplied to the computer by the power system. Also included in the computer system is a variable frequency clock circuit, the frequency of which changes based upon the supply voltage produced by the power system. This permits, during computer system operation where low voltage and low clock speeds will be sufficient to provide the performance needed, achievement of a power saving since both the voltage and frequency at which the system operates is reduced, thereby markedly reducing the power consumption.

Abstract: A voltage-boosted phase oscillator for driving a voltage multiplier comprises two intermeshed ring oscillators, each composed by an odd number of inverters connected in cascade through a closed loop and generating a normal phase and a voltage-boosted phase derived from the normal phase through a bootstrap circuit. The frequency of oscillation of both intermeshed ring oscillators is established by means of two similar RC networks common to both loops. The synchronization of the respective oscillations of the two rings is ensured by means of a plurality of SR flip-flops connected in cascade, formed by two NAND gates which, singularly, constitute as many inverters of the two rings. The oscillation and the arresting of the oscillation are controlled by means of a logic signal fed to a common input of a first pair of NAND gates which constitute respectively a first inverter of the relative ring oscillator and to a second input of which the phase produced by the relative ring oscillator is fed.

Abstract: A circuit for producing four indications on a bicolor light emitting diode (LED) includes a ring oscillator, with two inputs controlling inverters of opposite phase. By enabling or disabling these inverters, either, both, or neither dies of the LED are energized, causing it to emit light of either of its two primary colors, a secondary color formed by the combination of its two primaries, or no light, respectively. Nonlinear resistances are used to equalize the brightness of the two primaries and set the hue of the secondary.

Abstract: A first inverter logic element, a second inverter logic element, and a third inverter logic element constitute a loop circuit, and a first transistor, a second transistor, and a third transistor are connected between an output of the third inverter logic element and an input of the first inverter logic element. An output signal is taken out from an output of the second inverter logic element, and an oscillation frequency is regulated by the first transistor, the second transistor and the third transistor. Consequently, in a voltage controlled oscillator of the present invention, the number of loop circuits and transistors for regulating the oscillation frequency can be decreased, so that a simulation process can be simplified and required characteristics of the oscillation frequency can be easily obtained.

Abstract: An oscillator circuit is tuned to the frequency of reference pulses, for example, the spindle index pulses of a rotating magnetic storage system. A ring oscillator circuit includes a series transmission gate. The transmission gate is controlled by the output signal from a programmable delay line to interrupt operation of the ring oscillator and, in effect, provide fine tuning of the ring oscillator frequency in programmed steps. The output signal of the ring oscillator is divided down in a programmable divider, which provides a coarse frequency adjustment for an output pulse signal provided by the divider. Output signals from the divider are also provided as inputs to the programmable delay line. The frequency of the output pulse signal is compared to the frequency of the reference pulses to generate control signals for the programmable delay line. The control signals are generated by a microprocessor.

Abstract: A piezoelectric oscillator semiconductor circuit comprises a piezoelectric oscillator which is set to a designated oscillation frequency via electrical coupling to a separate semiconductor element comprising an oscillation circuit. The oscillation circuit in the semiconductor element has a gate lead and a drain lead connected to the piezoelectric oscillator to set the frequency of operation of the piezoelectric oscillator. Included in the semiconductor element are adjustment means comprising one or more frequency adjustment elements which may be selectively connected to one of the connection leads whereby the frequency of operation of the piezoelectric oscillator may be selectively changed without need for replacement or change of the semiconductor element. The frequency adjustment elements may be comprised of one or more fixed, separately formed capacitances provided as part of the semiconductor element but are electrically independent of the oscillation circuit, i.e.

Abstract: A voltage controlled crystal oscillator circuit, such as a Pierce oscillator circuit, includes an amplifier and is balanced by the addition of another varactor connected directly to the amplifier, whereby the frequency pull range is increased. Further, greater linearity can be achieved by adding another pair of varactors to the circuit.

Abstract: A stable sampling clock signal is supplied from a VCO circuit which is able to operate in a synchronous manner with an external sync signal that does not posses good phase stability while also providing an enlarged range of variable frequency output. The VCO circuit of this invention comprises an oscillation output circuit, such as NAND or NOR circuit, having one input connected to receive an external sync signal and having its output for providing the desired oscillation or sampling clock frequency. A control voltage circuit is connected to the other input of the oscillation output circuit and to the output of the oscillation output circuit.

Abstract: A stabilized gated oscillator that provides pulses at a predetermined repetition rate in phase coherence with a gating signal includes a ceramic resonator in a feedback resonant circuit between the output terminal and the input terminal of a linear amplifier. The resonant circuit, which establishes the repetition rate, is constructed to provide an oscillator frequency in a frequency range between two resonant frequencies of the ceramic resonator wherein the ceramic resonator acts as an inductance.

Abstract: Three series connected inverters (38, 40, 42) are attached to a tank circuit (18) which includes an inductance (12, 14) and a capacitance (16, 17). Negative (38) biases the inverters at the midpoint between the bistable low and high logic level states. Positive feedback from the second inverter (40) to the tank circuit induces oscillation in the tank circuit. The negative feedback is decoupled at the resonant frequency and the energy delivered to the tank circuit from the positive feedback maintains a low level oscillation in the tank circuit. Negative feedback around the three inverter digital circuit prevents lockup in the event of power loss or momentary short.

Abstract: An oscillator for generating a master clock frequency and also dividing that frequency by two. The oscillator uses one flip-flop of a dual D package as the generator for the master clock frequency and the other flip-flop in that package to divide that frequency by two.

Abstract: Each section (e.g., 102) of the ring oscillator consists of three two-input NOR gates; one in the feedforward path (108), one in the feedback path (112), and one in the crossover path (110). The center frequency of the oscillator is controlled by enabling and disabling the appropriate gates, such that a single closed loop path is formed. The gates in the feedforward and crossover paths are directly enabled or disabled (to disable, either input is held high) from a control circuit (FIG. 2). The gates in the feedback path, however, are indirectly enabled and disabled. To enable a particular feedback path gate (e.g., 118), either the corresponding crossover gate (116) is disabled, or the corresponding feedforward gate is disabled (114) and the crossover gate (122) in the following section is enabled. The later causes the feedback gate (124) in the following section to be disabled, thereby removing the remaining sections (106) of the oscillator from the closed loop path.

Abstract: A low phase jitter oscillator which is adjustable in frequency is disclosed. The oscillator comprises a logical OR gate having a feedback loop adjustable in length between the inverted output of the gate and the input of the gate. Using this configuration, the output changes state once every 1/2 T seconds wherein 1/2 T is equal to the propagation delay through the feedback loop and the OR gate. The frequency of the oscillator can be adjusted by adjusting the length of the feedback loop which correspondingly modifies the propagation delay through the feedback loop and thus the frequency of the oscillator output.

Abstract: A temperature-compensated oscillator circuit utilizes a quartz oscillator for producing an oscillating signal having a variable oscillator frequency which fluctuates in response to ambient temperature change. A variable semiconductor capacitor having a variable capacitance is connected to the quartz oscillator for regulating the oscillating frequency thereof according to the variable capacitance. The variable semiconductor capacitor comprises a semiconductor substrate, a floating electrode disposed on and electrically insulated from the semiconductor substrate, an injection electrode formed in the semiconductor substrate for injecting a given amount of electric charge into the floating electrode to set the value of the variable capacitance, and a capacitance electrode formed in the semiconductor substrate and receptive of a bias voltage effective to adjust the set value of the variable capacitance.

Abstract: A crystal oscillator comprising a crsytal and an inverter amplifier which utilizes a current mirror to provide a voltage output having a frequency double the frequency of the voltage waveform present in the inverter amplifier.

Abstract: A system is described which comprises many quartz resonators, all formed on the same quartz substrate. The method of fabrication ensures that all the resonators are mechanically and electrically isolated from each other. The oscillation frequencies of the resonators may be individually adjusted to different desired values during fabrication. Since the deviation from the optimum angle of cut is the same for all the resonators because they are all on the same substrate, all the resonators have the same temperature coefficient (change of frequency per degree change in temperature). Mounting the electronic circuitry on the quartz substrate simplifies the interconnections between the resonators and the circuitry, and reduces the size of the resulting device.