Abstract: A voltage controlled triggered oscillator includes a NAND gate and a set of series connected triggerable delay circuits, the output of the NAND gate being fed back to one of its inputs through the delay circuits. A trigger signal is applied to another input of the NAND gate and to triggering inputs of the delay circuits. When the trigger signal is asserted, each delay circuit produces an output signal of state which tracks the state of its input signal but with a predetermined delay so that the NAND gate output oscillates with a frequency determined by the delay times of the delay circuits and the propagation time of the NAND gate. When the trigger signal is deasserted the NAND gate output is terminated and each delay circuit drives its output signal high regardless of the state of its input signal so that the oscillator may be rapidly retriggered.

Abstract: A voltage controlled oscillator (VCO) is stabilized against variations in output frequency resulting from changes in temperature or the power supply voltage by trimming the voltage controlled oscillator from a second master VCO which is connected into a phase lock loop. Each of the two voltage controlled oscillators has an output frequency which is a function of two inputs. The signal input to one control input of each of the VCO's is the output of the low pass filter in the phase lock loop. The VCO's may both be implemented by cross-coupled NOR gates with grounded capacitor inputs.

Abstract: An oscillator produces an output signal which is frequency locked to a reference signal but phased locked to a triggering signal. The oscillator includes a NOR gate having its output fed back to one of its inputs through a programmable delay circuit while the triggering signal is applied to another of its inputs. When enabled by the triggering signal, the output signal of the NOR gate oscillates at a frequency inversely proportional to the delay time of the delay circuit. The delay time is controlled by a control circuit which counts NOR gate output signal cycles occurring during a predetermined number of reference signal cycles and increments the delay time when the count is higher than expected for an oscillator output signal of a desired frequency and decrements the delay time when the count is lower than expected.

Abstract: There are three oscillator circuits which oscillate at different frequencies, each oscillator circuit including a gate having an input and an output. The output of the first gate is connected to an inverter and the input of the second gate. The output of the inverter is connected to the input of the third gate. The output of the second and third gates is connected across a piezoelectric transducer to produce a warble sound.

Abstract: A micropower DC voltage indicator is provided that is a two terminal device with a very high input impedance. An oscillator circuit is provided by a series of inverters, such as metal-oxide semiconductors (MOS) with the power inputs connected in parallel. A suitable RC circuit connects the output of one MOS inverter to the input of another MOS inverter, otherwise the output of each MOS inverter connects directly to the input of the next MOS inverter. Across one of the MOS inverters is connected a liquid crystal display which indicates if a DC voltage within a specific range is applied to the two terminals of the DC voltage indicator. The two terminal inputs to the oscillator circuit have a very high impedance and operate over a fairly broad DC voltage range.

Abstract: Between insulative layers (31-37, 41-44), a multilayer substrate comprises at least one dielectric layer (26-29). It is possible to form capacitors (58), resistors (46), and wiring conductors (61, 62) in the substrate. The at least one dielectric layer should be of at least one dielectric composition which has a perovskite structure. Preferably, each insulative layer is of an insulating material which consists essentially of aluminum oxide and lead borosilicate glass. The substrate is convenient in manufacturing a crystal oscillator by mounting a crystal vibrator (71) and a transistor (72) on the principal surface(s). Examples of the dielectric composition are:Pb[(Fe.sub.2/3.W.sub.1/3).sub.0.33 (Fe.sub.1/2.Nb.sub.1/2).sub.0.67 ]O.sub.3,Pb[(Mn.sub.1/3.Nb.sub.2/3).sub.0.01 (Mg.sub.1/2.W.sub.1/2).sub.0.30 (Ni.sub.1/3.Nb.sub.2/3).sub.0.49 Ti.sub.0.20 ]O.sub.3,andPb[(Mg.sub.1/2.W.sub.1/2).sub.0.66 Ti.sub.0.34 ]O.sub.3.

Abstract: A low power oscillator circuit including a latch connected to two loops. Each loop includes dynamic inverters and static inverters connected in cascade. The loops are connected to the latch such that the output of the final stage is an input to the latch. An initialization circuit is included on one loop to initiate oscillation. Storage capacitors are included in the loops to provide an oscillator output voltage that is greater than the oscillator power supply voltage.

Abstract: A standard TTL inverter (1) drives a series circuit of an inductor (9) and a capacitor (11). This is fed back through a frequency-control crystal (15). A resistor (19) is also in the feedback circuit, and a resistor 7 bridges the low-current-accepting inverter (1). None of the circuit elements need be of high precision or otherwise expensive.

Abstract: An oscillation circuit having a reference voltage circuit for forming a reference voltage by dividing a power supply voltage. The reference voltage circuit supplies the reference voltage to one of the input terminals of the comparing circuit. A charge/discharge voltage is supplied from a junction between a transmission gate circuit and a CR circuit to the other input terminal of the comparing circuit. The comparing circuit compares the charge/discharge voltage with the reference voltage to produce pulse signals.

Abstract: A clock pulse regenerator uses a pair of oscillators each comprising a NOR gate and a transmission line feedback element. The oscillators are provided with complementary data pulses and provide an output signal only when the data signal is of a selected logic level. The output signals are combined to form a continuous regenerated clock signal. An FSK encoder using similar oscillators is also disclosed.

Abstract: This relates to a programmable ring oscillator which comprises a plurality of series coupled gates the output of the last of which is fed back to the input of the first. Bypass means are coupled across the outputs of selected gates so as to in effect increase or decrease the length of the string. In one embodiment, laser trimmable fuses are employed in the bypass networks. In a second embodiment, a data selector under external control is employed.

Abstract: A test circuit that is particularly suitable for inclusion on an LSI chip when testing a new technology or process. The circuit will enable accurate determination of the effects of loading on the turn-on and turn-off delays of one or more logic circuits on the chip. These determinations are based upon a comparison of the periods of different signals obtainable from the test circuit.

Abstract: An oscillator circuit for simultaneously outputting two frequency signals comprises a single resonator vibrating in two modes at different frequencies, an amplitude modulating circuit for modulating one of said two frequencies with a third frequency, a feedback circuit receiving the output of the amplitude modulating circuit, a detector demodulating the amplitude modulated signal, the demodulated signal being the third frequency used to modulate the output of the resonator. The two frequencies of the resonator are close together in value and the third frequency signal is the difference in frequency of the two resonator outputs. Circuit outputs are one resonator frequency and the difference frequency.

Abstract: An oscillator including an amplifier which is formed by CMOS inverters and has a positive feedback path from an output to an input of the amplifier. The positive feedback path includes a capacitor which is alternately charged and discharged by switched constant current devices controlled by the amplifier and connected to the amplifier input. The amplifier includes a second capacitor in a negative feedback path to limit voltage swings at the amplifier input. The constant charging and discharging currents can be produced by current mirrors which are controlled to control the oscillation frequency.

Abstract: A thermometer is disclosed which utilizes a thermistor as a temperature sensor, controlling the frequency of oscillation of an oscillator circuit. The output pulses from that circuit are frequency-divided during a fixed time interval by a variable frequency divider circuit, with the division ratio being successively varied during that interval in accordance with the cumulative number of pulses output from the variable frequency divider circuit, counted by a counter circuit, with the variations of the frequency division ratio being such as to accurately compensate for the non-linear temperature/resistance characteristic of the thermistor. The cumulative count of pulses output from the variable frequency divider circuit at the end of the fixed time interval is proportional to temperature, and is displayed as temperature by a digital display. The thermometer is suited to mass-production low-cost manufacture, yet can be miniaturized, lightweight and accurate.

Abstract: A phase-locked loop for use in the common T1 systems. The phase relationship of the clock pulse output of a voltage controlled oscillator is determined with respect to an incoming data pulse train. If the clock signal leads the data signal, an error signal of a first polarity is applied to an integrator whose output is provided to the VCO to reduce the frequency of the clock pulse. If the clock signal lags the data signal, an error signal of a second polarity is applied to the integrator whose output is provided to the VCO to increase the frequency of the clock pulse. The logic of the circuitry is such that the output of the integrator is always either increasing or decreasing, even if there is zero phase error between the clock pulse and data pulse (i.e. the loop has infinite gain for zero error). The integrator continues to integrate in a first direction until the frequency of the clock pulses is adjusted so far that the lead is changed to a lag or vice-versa, with respect to the next data pulse.

Abstract: A low frequency pulse generator apparatus utilizing an R-C timing network which includes a plurality of selectable capacitors to provide frequency pulse rates over a predetermined range. A counter which may be set to count a finite number of pulses, controls the generated pulse total.

Abstract: A CR oscillation circuit is provided which includes inverters which are connected in series and whose operating current paths between a power source terminal and a ground terminal are connected in series with a constant current source. In certain embodiments, a resistor is connected between the output terminal of one inverter and the input terminal of the first inverter, and a capacitor is connected between the output terminal of another inverter and the input terminal of the first inverter. The CR oscillation circuit further has a constant current source connected in series with the operating current path of said inverters between the power source terminal and the ground terminal. In other embodiments, the resistor and capacitor are connected in parallel and to the input of an inverter.

Abstract: A two-phase, period-proportional voltage-controlled oscillator circuit is provided for clocking an analog delay line which can be used, for example, in an electronic musical instrument. The voltage-controlled oscillator circuit provides two clock output signals of opposite phase and having a period directly proportional to the control voltage, i.e., the frequency of the two clock signals is inversely proportional to the control voltage. Since the delay provided by the analog delay line is directly proportional to the period of the clock signals, the delay is directly proportional to the control voltage thereby eliminating a source of distortion in a delay modulation system.

Abstract: A test circuit that is particularly suitable for inclusion on an LSI chip when testing a new technology. The circuit will enable accurate determination of the turn-on and turn-off delays of a logic circuit on the chip. Two related feedback loops are provided, one of the loops containing the circuit being tested. The differences in time duration between related portions of the two loops correspond to the turn-on and turn-off delays of the circuit being tested.

Abstract: In a microcomputer integrated circuit the option of selecting between an RC oscillator or a crystal oscillator for generating the clock for the microprocessor is made available. By making the selection during the manufacturing process, external pin outs and chip area are minimized.

Abstract: An oscillator circuit which demonstrates stable operation over a wide range of supply voltages and process variations. A latch circuit is controlled utilizing a timing capacitor. A constant current source is applied alternately to opposite sides of the timing capacitor through a series of switching gates which bootstrap the voltage across the timing capacitor, with the switching gates being controlled by the output of the latch circuit.

Abstract: In an oscillator circuit including a variable capacitor for inverting a pair of inverters oppositely to each other with a time period defined by a resistance value of a resistor and a capacitance of the variable capacitor, an additional capacitor is provided to be biased by an inverter function of an additional inverter in voltage polarity opposite to that of the variable capacitor.

Abstract: A digital position transducer apparatus utilizing a moveable slug-tuned inductor to measure the displacement or movement of a mechanical component. The value of the inductor controls an oscillator's output frequency which is converted to a digital word proportional to the displacement of a mechanical component.