Integrated Circuit Patents (Class 340/14.61)
  • Patent number: 8558669
    Abstract: A RFID reader includes a radio frequency (RF) multiplexer having a plurality of antenna ports for connecting with a plurality of antennas respectively, a reader module having a first internal port and second internal port and being configured for communicating with a tag proximate to the RFID reader through one of the first and the second internal ports, a network module for connecting the RFID reader to a network, and a micro-controller module being connected to the RF multiplexer, the reader module and the network module. The micro-controller module is configured for controlling the reader module to communicate with the tag through a selected antenna port of the RF multiplexer or an external antenna device and for controlling the network module to communicate with the network. The first internal port of the reader module is connected to the RF multiplexer for the reader module to utilize the antennas connected to the antenna ports of the RF multiplexer.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: October 15, 2013
    Assignee: Megabyte Ltd.
    Inventor: Chun Sing Matthew Man
  • Patent number: 8390453
    Abstract: An integrated circuit with a rectifier element. One embodiment provides a signal source, an electronic circuit and a rectifier element with a copper layer and a cuprous oxide layer adjacent to and in direct contact with the copper layer. The signal source is configured to drive a signal on a signal output terminal that is electrically coupled to the copper layer. The electronic circuit is electrically coupled to the cuprous oxide layer. The rectifier element may be formed between wiring layers of an integrated circuit.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: March 5, 2013
    Assignee: Qimonda AG
    Inventor: Ricardo Mikalo
  • Patent number: 8294556
    Abstract: Circuits and methods for transmission of digital data between two or more devices via powerline particularly suited for use in high attenuation, high noise commercial/industrial powerline environments, including transmission of pulses generated by a capacitor charged in the positive half cycle of the sine wave and discharged during the negative half-cycle, placing the pulse at one of two predetermined signal timing positions related to zero voltage crossing points or to previously transmitted pulses so that the pulses are substantially in the powerline temporal quiet zone near zero crossing and so that the powerline voltage at the time of the pulse is additive to the capacitor voltage.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: October 23, 2012
    Assignee: Powerline Control Systems, Inc.
    Inventors: Marshall Lester, Preston Lane, Ron Fienberg
  • Patent number: 8207823
    Abstract: An integrated circuit is provided. The integrated circuit includes an RFID tag configured to store various administrative information after testing at a wafer level in response to a radio frequency signal, and an interface unit configured to perform the function of an interface between the integrated circuit and the RFID tag for storing the information in the RFID tag. An antenna of the RFID tag is formed using a wire and a lead frame. A method for writing information of an integrated circuit is also provided. The method includes the steps of performing a wafer processing of an integrated circuit having a RFID tag; performing a wafer level test of the integrated circuit; transmitting and receiving a radio frequency signal to store various administrative information in the RFID tag; and storing a chip confirmation code in the RFID tag.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: June 26, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 7786847
    Abstract: An RFID device includes an analog block configured to receive a radio frequency signal so as to output an operation command signal, a digital block configured to output an address, a temperature address, an operation control signal, and a temperature sensor activation signal in response to the operation command signal received from the analog block and to provide a corresponding response signal into the analog block. The device further includes a memory block configured to receive the address, the temperature address, and the operation control signal so as to generate an internal control signal for controlling the internal operation, and to read/write data in a cell array including a non-volatile ferroelectric capacitor in response to the internal control signal, and a temperature sensor processing unit configured to detect a temperature change state of an RFID tag in response to the temperature sensor activation signal.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: August 31, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 7741971
    Abstract: The Invention, titled the “Split Chip” by the Inventor, contemplates an RFID enabled consumer oriented tracking system which protects consumer privacy by splitting a miniaturized silicon RFID transponder circuit into a retained piece and a detached piece. The two pieces are electrically connected by a fine piece of conductive material. Each piece is dependent upon the other in order to disgorge data. The electrical connection between the two pieces can be severed by the consumer by tearing the fine piece of conductive material at a designated spot on the substrate making the Split Chip moribund. Upon a return or refund of the consumer item the original data can be recovered through a laser guidance system which connects the retained piece and its alpha numeric identifier to a back end host computer administration network.
    Type: Grant
    Filed: April 22, 2007
    Date of Patent: June 22, 2010
    Inventor: James Neil Rodgers
  • Patent number: 7639118
    Abstract: A detector receiver circuit (2) for use as a wake-up detector for detecting an amplitude modulated carrier signal is described. The circuit (2) comprises: an antenna (4) for receiving the modulated carrier signal; a transistor (10), such as an FET, is connected to the antenna (4) and configured to operate as a detector of modulation of the carrier frequency. The circuit further comprises a resonator circuit (12-16) which is also connected to the transistor and configured such that the transistor (10) can simultaneously oscillate at substantially the modulation frequency; an oscillator quenching means (20) for periodically quenching oscillation of the transistor (10) and means (26, 28, 30) for sensing the characteristics of the build-up of oscillation to indicate the presence of a modulated carrier signal.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: December 29, 2009
    Inventor: Ian J Forster
  • Patent number: 7274283
    Abstract: Methods and apparatus that allow restricted access to internal registers of an integrated circuit (IC) device via an interface are provided. Unrestricted access to internal registers via the interface may be allowed during a manufacturing process to allow device testing. After such testing is complete, the device may be placed in a restricted access mode, for example, by blowing a master “lock” fuse, to prevent unrestricted access to one or more of the internal registers via the interface. However, full or partial access to the internal registers may still be provided via an access code or “combination lock” allowing the master fuse lock, in effect, to be bypassed.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: September 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: Paul Stewart Yosim, Irfan Rashid
  • Patent number: 6965299
    Abstract: In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: November 15, 2005
    Assignee: LSI Logic Corporation
    Inventors: William J. Dally, Daniel K. Hartman