Abstract: An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT?) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT? signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.

Abstract: An order preserving pattern matching apparatus according to the present invention includes a matching direction pattern conversion unit for setting an ID number for each order preserving type of a character string in a retrieval pattern for a plurality of matching directions including at least one diagonal direction, and generating a list of the ID numbers as a matching direction pattern, an encoding processing unit configured to generate an encoded two-dimensional pattern assigned with a corresponding ID number for a pattern being a part of a two-dimensional pattern to be searched that matches an order preserving pattern assigned with an ID number, and a matching unit configured to perform matching whether an arrangement matching the matching direction pattern assigned with an ID number exists or not within the encoded two-dimensional pattern.

Abstract: A rack-mountable computer system includes: a power supply unit comprising a power storage module and a power switch module; a controller configured to generate a signal indicating status information of the rack-mountable computer system; an indicator configured to indicate the status information of the rack-mountable computer system; and a signal latch module. The power supply unit switches a power supply of the indicator from the external power supply unit to the power supply unit in a power loss event when the rack-mountable computer system is detached from a rack or a system power of the rack is lost from an external power supply unit and supplies power to the indicator after the power loss event occurs. The signal latch module is configured to latch the signal that is generated by the controller and indicates the status information of the rack-mountable computer system in response to the power loss event.

Abstract: A computer-implemented method causing a linear on-screen keyboard that includes an array of input keys and a focus indicator to be displayed, wherein navigation of the focus indicator to an input key in the array enables a selection of a character corresponding to the input key; and upon determining that the focus indicator has navigated to a first input key in the array, causing one or more utility keys to be displayed proximate to the first input key.

Abstract: Various embodiments are described that relate to random noise addition to a communication. A first secure network can employ a first encryption scheme and a second secure network can employ a second encryption scheme. In order to communicate between the first secure network and the second secure network such that the schemes are not decipherable, random noise can be added to a communication designated to transfer from the first secure network to the second secure network.

Abstract: Provided are embodiments for determining solenoid plunger position by performing a method which includes generating, by a first signal circuit, a first signal based at least in part on a pull-in current value of a current applied to a solenoid coil of a solenoid. The method further includes generating, by a second signal circuit, a second signal by applying a time delay to the first signal. The method further includes comparing, by a comparator circuit, the first signal and the second signal to determine whether a plunger of the solenoid has moved within the solenoid from a first position to a second position. The method further includes, responsive to determining that the plunger of the solenoid has moved within the solenoid from the first position to the second position, reducing the current applied to the solenoid coil of the solenoid from the pull-in current value to a hold current value.

Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m?r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m?r?1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m?r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage memory allocation. An example apparatus includes a memory detector to scan a platform for available memory. The example apparatus also includes a memory size checker to retrieve a virtual memory layout associated with the available memory devices associated with the platform and to determine whether virtual address boundaries of respective ones of a available memory device generate a virtual address gap therebetween. The example apparatus also includes a address assigner to reassign virtual addresses of at least one of the respective ones of the available memory devices to remove the virtual address gap.

Abstract: A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

Abstract: Disclosed herein is a novel multi-way merge network, referred to herein as a Hybrid Comparison Look Ahead Merge (HCLAM), which incurs significantly less resource consumption as scaled to handle larger problems. In addition, a parallelization scheme is disclosed, referred to herein as Parallelization by Radix Pre-sorter (PRaP), which enables an increase in streaming throughput of the merge network. Furthermore, high performance reduction scheme is disclosed to achieve full throughput.

Abstract: According to one embodiment, a device includes first lines transmitting a first signals; second lines receiving the first signals; and a first circuit including a first selector coupled to the first lines, a second selector coupled to the second lines, third lines and a fourth lines between the first and second selectors. Each of the third lines stores the second signals, each of the fourth lines stores the third signals. The first circuit counts a first number of second signals equivalent to the corresponding first signal; counts a second number of third signals equivalent to corresponding first signal of the first signals; and couples either the third or the fourth lines to the first and second lines via the first and second selectors, based on a result of comparison between the first and the second numbers.

Abstract: An automated system is provided. Examples of automated systems include processors for calculation which implement a secure boot process based on the plurality of numbers; chip cards for authentication; telecommunication equipment; programmable logic controllers, control devices for railways, etc. The operation is controlled depending on whether a sequential test for randomness of a plurality of numbers from a physical random number generator is marked as failed. This has the advantage that an online-test for integrity of the plurality of numbers is possible at a high accuracy and low latency.

Abstract: Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.

Abstract: A graphics processing unit (GPU), configured to perform tile-based rendering using prefetched graphics data, includes a tiler configured to perform binning on a current frame and obtain a first binning bitstream of a first tile among a plurality of tiles of the current frame, a binning correlator configured to determine whether the first tile and a second tile of a previous frame are similar to each other by using the first binning bitstream and a second binning bitstream of the second tile, where the second tile has a same tile ID as the first tile, a prefetcher configured to prefetch second graphics data used to render the second tile by using the tile ID, when it is determined that the first tile and the second tile are similar to each other, and at least one processor configured to render the current frame using the prefetched second graphics data.

Abstract: A glitch measurement device is coupled to a circuit under-test and includes a counter circuitry and a detector circuitry. The counter circuitry is coupled to the circuit under-test, and is configured to perform a first counting operation according to an input signal transmitted to the circuit under-test to generate a first count signal, and to perform a second counting operation according to an output signal outputted from the circuit under-test to generate a second count signal. The detector circuitry is coupled to the circuit under-test and the counter circuitry, and is configured to receive the first count signal and the second count signal according to the input signal, and to generate a glitch indication signal according to the first count signal and the second count signal.

Abstract: A method, computer program product, and computer system for providing a comparison result vector of a predefined number of elements w resulting from comparison of multiple vectors of compressed data within a processor comprising registers of same size m is provided. Vector elements of the comparison result vector are stored in a register of the registers. Zero bits are padded between vector elements of each of the comparison result vectors. A compare bit result vector indicative of the vector elements is generated for accessing the results of the comparison in the comparison result vector.

Abstract: There is disclosed in one example a communication apparatus, including: an analog data source; a digital communication interface; and an analog-to-digital converter (ADC) circuit assembly, including: an analog sample input; an input clock to provide frequency fin; a time-interleaved front end to interleave n samples of the analog sample input; and an ADC array including n successive-approximation register (SAR) ADCs, the SAR ADCs including self-clocked comparators and configured to operate at a frequency no less than f in n .

Abstract: Techniques are described herein for executing queries with a recursive clause using a plurality of processes that execute database operations in parallel. Each process of the plurality of processes either generate or are assigned a segment that is part of a temporary table. For each iteration of the recursive query, work granules are divided up and assigned to each of the plurality of processes. As each respective process produces a portion of a result set for a given iteration, that process appends said portion of the result set to the respective segment that the respective process manages. Each slave process then publishes, to one or more sources, a reference to the newly generated results. During the next iteration, any slave process may access any of the data from the previous iteration.

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

Abstract: A method for generating and maintaining hierarchical tags with community-based ratings is provided. Tags for media streams are organized into a hierarchical format. Users may select tags from the hierarchical tag database that describes a particular multimedia content. If the user is unable to locate a desired tag, the user may submit a new tag. Upon submission of the new tag, a librarian approves the tag before storing and placing the tag in the hierarchical tag database. Users are also able to rate the quality of the association between the tag and the multimedia content. If a tag is rated low, the tag may be removed from the hierarchical tag database. If the tag is rated highly, display of the tag in a list of tags becomes more prominent.

Abstract: An integrated circuit includes a pipeline of compare logic stages. The pipeline, at successive pipeline stages, determines whether each of a set of input symbols meets a corresponding programmable criteria. The compare logic stages each compare the set of input symbols to a respective programmable value. The compare logic stages also each provide, to a respective successive compare logic stage, a corresponding plurality of indicators of whether respective ones of the set of input symbols met the corresponding programmable criteria for that compare logic stage. The corresponding programmable criteria are configurable to be based at least in part on the corresponding plurality of indicators from a respective previous compare logic stage.

Abstract: An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

Abstract: A processor includes a vector register including data fields to store values of vector elements of data, a decoder to decode a single instruction multiple data (SIMD) instruction specifying a source operand and a mask to identify a masked portion of the data fields. An execution unit is to read a plurality of values from unmasked data fields of the plurality of data fields of the vector register; compare, within the vector register, each of the plurality of values from the unmasked data fields for equality with all other values of the plurality of values; and responsive to a detection of an inequality of any two values of the plurality of values, set a mask field, corresponding to a detected unequal value, to a masked state with a flip of a bit value of the mask field, to signal the detection of the inequality.

Abstract: There are provided a logic unit circuit and a pixel driving circuit, which relate to a display technical field and are used to solve the problem that technical difficulties are increased due to mixed use of different types of transistors in the logic unit circuit. The logic unit circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor of a same type. The logic unit circuit is used to realize logic gate operation.

Abstract: An efficient hardware apparatus for calculating the maximum and/or minimum of two n-bit binary input values generates a number of separate select signals, each of which is then used to control the selection of a single bit from one of the two binary inputs. A select signal for an ith bit of the output depends upon bits [n?1, i] in each of the two binary inputs and based on the select signal the ith bit is selected from one of the two inputs.

Abstract: A processor unit can be used to rapidly search a string of characters. The processor unit can include vector registers each having M vector elements, each vector element having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each diagonal of the matrix of comparators, and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. Correction logic within the processor unit can suppress indications of a partial match or of a full match in the bit vector.

Abstract: Apparatus and methods for conversion from signed integer to a floating point representation are provided. Two's complementation and lead zero count operations are performed in parallel. Exponent generation and mantissa shifting are performed in parallel. Generation of the floating point exponent from the signed integer, including application of a scaling factor, is performed using a 3:2 compressor or carry-save adder and an adder. Two's complementation for generation of the mantissa in unsigned integer format is performed using an adder. Lead zero count for controlling mantissa shifting is performed by one's complementing the signed integer if negative, counting lead zeros in the one's complement output, and determining, using the one's complement output, whether the one's complement lead zero count differs from the two's complement lead zero count by one.

Abstract: Dynamic history multistream long range compression (DHC) techniques are described for efficiently compressing multiple, prioritized data streams received over a channel. A history buffer is associated with each received stream and a DHC compressor dynamically allocates fixed sized history sections to and from each history buffer. In implementations, the DHC compressor makes stream history size adjustments prior to compressing a block of data and sends information identifying the change in history size to a DHC decompressor. The DHC decompressor sends signaling information to the DHC compressor that is used to ensure that the DHC decompressor can operate with a fixed amount of total history memory.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Abstract: A method for performing an operation based on at least two operands is proposed, in which steps of the operation are performed in time-randomized fashion. In addition, an apparatus, a computer program product and a computer-readable storage medium are accordingly specified.

Abstract: The formulation of a merged sorted list from multiple input sorted lists in multiple phases using an array pair. Initially, the first array is populated with the input sorted lists. In the first phase, the first and second input sorted lists are merged into a first intermediary merged list within the second array. Each subsequent phase merges a prior intermediary merged list resulting from the prior phase and, a next input sorted list in the first array to generate a next intermediary merged list, or a merged sorted list if there or no further input in the first array. The intermediary merged lists alternate between the first array and the second array from one phase to the next phase.

Abstract: A scalable rank filter and method that performs rank filtering based on input data samples are disclosed. In one embodiment, the rank filter comprises a pipeline that receives input data samples and generates an output based on the input data samples as a result of completing execution of the pipeline. The rank filter includes output logic to determine the output prior completing execution of the pipeline and outputs an indication of a median.

Abstract: A method for pattern matching finds a target pattern from a stream of patterns, both of the stream of patterns and the target pattern being comprised of elements. The method includes acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Abstract: A vehicle includes a gateway controller configured to interface a diagnostic port to a vehicle communication network. In response to a perimeter alarm system being in an armed state, transfer of messages from the diagnostic port to the vehicle communication network is inhibited. A change session diagnostic request received from the diagnostic port is transferred to the vehicle communication network in response to vehicle speed being less than a threshold and an ignition switch begin in a run position. The transfer of the change session diagnostic request is otherwise inhibited unless intended for a module designated for reprogramming keys.

Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Abstract: According to an embodiment, a computing apparatus includes a memory, and a processor. The memory stores N first vectors in a d-dimensional binary vector space consisting of binary values. The processor acquires a second vector in the d-dimensional binary vector space. The processor extracts M first vectors having a distance from the second vector satisfying a first condition out of the N first vectors, and calculate a distribution of distances of the M first vectors from the second vector. The processor acquires a first kernel function per a first distance between the M first vectors and the second vector in a first range. The processor generates a second kernel function based on the distribution and the first kernel functions. The processor calculates an occurrence probability of the second vector in the N first vectors based on the second kernel function.

Abstract: Embodiments include methods, systems and computer program products for performing a tournament tree sort on a hardware accelerator. The method includes receiving a plurality of key values by the hardware accelerator, storing each the plurality of keys into a location on a memory of the hardware accelerator, and creating a pointer to each of the locations of the plurality of keys. The method also includes storing the pointer to each of the plurality of keys into a first array stored by the hardware accelerator, sorting the plurality of keys by ordering the pointers in the first array and by using a second array for storing the pointers, wherein the sorting identifies a winning key from the plurality of keys in the memory, and outputting the winning key.

Abstract: Embodiments include methods, systems and computer program products for performing a tournament tree sort on a hardware accelerator. The method includes receiving a plurality of key values by the hardware accelerator, storing each the plurality of keys into a location on a memory of the hardware accelerator, and creating a pointer to each of the locations of the plurality of keys. The method also includes storing the pointer to each of the plurality of keys into a first array stored by the hardware accelerator, sorting the plurality of keys by ordering the pointers in the first array and by using a second array for storing the pointers, wherein the sorting identifies a winning key from the plurality of keys in the memory, and outputting the winning key.

Abstract: Techniques are described herein for, among other things, selecting and/or modifying an ad based on an emotional state of a user. The user's emotional state is determined based on the user's online activity. Advertisement(s) are selected and/or modified for provision to the user based on the user's emotional state. An advertisement may be modified in any of a variety of ways. For example, a color that is included in an advertisement may be replaced with a different color. In another example, a color filter may be applied to the advertisement. In yet another example, visual attribute(s) of the advertisement may be modified. Examples of a visual attribute include, but are not limited to, hue, brightness, contrast, and saturation.

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract: This document discusses, among other things, systems and methods to receive an instruction to selectively update a value of one or more selected bits of a first register, to receive the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged, and to selectively update the value of the one or more selected bits of the first register using a first write port without receiving the value of the one or more selected bits of the first register. In an example, the value of the one or more selected bits of the first register can be updated without receiving the value of the first register, in certain applications, reducing the number of read ports required to update the value of the first register.

Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.

Abstract: The formulation of a merged sorted list from multiple input sorted lists in multiple phases using an array pair. Initially, the first array is contiguously populated with the input sorted lists. In the first phase, the first and second input sorted lists are merged into a first intermediary merged list within the second array. Each subsequent phase merges a prior intermediary merged list resulting from the prior phase and, a next input sorted list in the first array to generate a next intermediary merged list, or a merged sorted list if there or no further input in the first array. The intermediary merged lists alternate between the first array and the second array from one phase to the next phase.

Abstract: A semiconductor apparatus may include an operation signal input selection block configured to output one of either a first operation signal or a second operation signal, as a select signal, in response to an operation select signal. The semiconductor apparatus may include a target code selection block configured to output one of either a first target code or a second target code, as a select code, in response to the operation select signal. The semiconductor apparatus may include an enable signal generation block configured to generate an enable signal when a time corresponding to the select code passes, in response to the select signal. The semiconductor apparatus may include an operation signal output selection block configured to output the enable signal, as one of either a third operation signal or a fourth operation signal, in response to the operation select signal.

Abstract: An approach is provided that uses symbols to represent search criteria. In this approach, a symbol is received from a user in a search request. Search criteria that corresponds to the received symbol is retrieved from a computer accessible data store. Data stores are searched for the plurality of search criteria that correspond with the received symbol and search results are retrieved based on the searching performed. These retrieved search results are then provided to the user.

Abstract: A timing control circuit includes a single chip having a plurality of output ports; a chip selecting circuit having a plurality of control ports connected to the output ports and paths; a signal input circuit; a signal output circuit; and a switching circuit including a plurality of signal channels. The chip selecting circuit generates a selection signal according to a control signal and outputs the selected signal via one of the selected paths. One of the channels is selected when a selection signal is output via the selected channel. When one of the signal channels is selected and there are signals inputted by the signal input circuit via the signal channel, the signals from the signal input circuit are passed to the signal output circuit through the signal channel and the light emitting diode in the signal channel is turned on.