Abstract: Representative implementations of devices and techniques provide analog to digital conversion of multiple parallel analog inputs. An input interface is arranged to organize the parallel analog inputs and an analog-to-digital converter (ADC) is arranged to sequentially convert the multiple parallel analog inputs to digital results.

Abstract: A passive entry system is disclosed. The system comprises an unlocking module that performs a key operation in a keyless environment and a plurality of fobs configured to trigger the unlocking module to perform the key operation. each fob has a unique value associated thereto. The unlocking module determines a range of identification values, generates an authentication request packet based on the range, of identification values, and broadcasts the request packet. Each fob receives the request packet; and determines whether the unique identification value of the corresponding fob falls within the range of identification values. The fob also generates a response packet if the unique identification value falls within the range of identification values and transmits the response packet to the unlocking module. The unlocking module receives the response packets from the fobs, and performs the key operation based on one of the received response packets.

Abstract: An inputter can intuitively understand a numerical value input by himself/herself and the possibility of ignoring an erroneous input can be reduced. Only an Arabic numeral representing the input numerical value is displayed in a first display area. At least one of (i) a character string comprising an Arabic numeral and a character or a character string other than the Arabic numeral and (ii) only a character or a character string other than the Arabic numeral, which represents the input numerical value, is displayed in a second display area.

Abstract: Various embodiments of a device, system and methods that promote safety and security within an organization. Sensor data from one or more installation sensors is collected, analyzed and used to create a map and/or directions that, when received by a wireless mobile device, facilitate a person's possible egress around or from a detected event. The information provided to the person by the map and/or the directions may be individually crafted to be of maximum use to the specific recipient so the person can understand, plan and execute the most appropriate danger avoidance maneuvers in minimal time.

Abstract: An ice detection system comprising a first group of sensors and a second group of sensors. The first group of sensors is located in a first group of locations on an aircraft. The first group of sensors in the first group of locations is configured to detect a first type of icing condition for the aircraft. The second group of sensors is located in a second group of locations on the aircraft. The second group of sensors in the second group of locations is configured to detect a second type of icing condition for the aircraft.

Abstract: Embodiments of methods, apparatuses, devices and/or systems for manipulating character expressions to determine relationships among such character expressions.

Abstract: A vehicle control system for data exchange in a transport system, where a control unit is configured to transfer control commands to a vehicle configured to transfer status messages to the control unit, where a signal generator is connected to a first data line and a second data line and provides a changeover signal, a first switching means is arranged in the control unit and is configured to change positive half-waves of the changeover signal, and a second switching means is arranged in the vehicle and is configured to change negative half-waves of the changeover signal, in a circuit formed by the first and second data lines to transfer binary values back-and-forth between the control unit and the vehicle.

Abstract: The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2?b2+c2) with (x2+y2+z2); and (a3+b3?c3) with (x3+y3+z3); implementing an efficient method of computing (a4?b4?c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.

Abstract: A system and method for effectively communicating information using at least one mode of communication is described, in which information recipients proximate to a communications device within a pre-determined space and during a pre-determined time period are identified, from whom physiological state information is obtained that, when coupled with other characteristics information, is used to select from a plurality of information elements at least one information element to better target the information elements. The information element is then provided to the communications device so that it may be provided to the information recipients in the pre-determined space in a manner that is sensed by the information recipients.

Abstract: Methods of determining patch cord connectivity information include receiving, at each of a plurality of RFID readers, a signal from an RFID tag that is associated with a first patch cord and then, identifying the one of a plurality of connector ports that the first patch cord is connected to based at least in part on respective strengths of the signals received at each of the plurality of RFID readers. RFID triangulation systems and methods of calibrating such systems are also provided.

Abstract: A management system using Global Positioning System receivers for tracking remote units from a central office and quickly and conveniently determining if those remote units have varied from a set of predetermined parameters of operation. The system also includes provisions that allows information to be sent from the remote units to the central office and vice versa. The system also has safety features that promote the rapid dispatch of law enforcement personnel when requests for emergency assistance have been made from the remote units.

Abstract: A magnitude comparator for comparing magnitude of a first data and a second data is disclosed. The first data and the second data are both binary data. The magnitude comparator includes many non-least comparator cells and a P-channel transistor. Each of the non-least comparator cells includes a first transistor, a second transistor, a third transistor and a fourth transistor. The drain of the second transistor is electrically connected to the source of the first transistor, and the source of the second transistor is electrically connected to a ground terminal. The third transistor electrically connects the first transistor, and the fourth transistor electrically connects the first transistor and the third transistor. The source of the P-channel transistor electrically connects a supply terminal, the gate of the P-channel transistor electrically connects the ground terminal, and the drain of the P-channel transistor electrically connects the third transistor of the first comparator cell.

Abstract: Embodiments of methods, apparatuses, devices and/or systems for manipulating character expressions to determine relationships among such character expressions.

Abstract: A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be compared at a time. In addition, a null terminated string may be detected. The shorter strings may be handled differently than longer strings.

Abstract: A system which operates a digitally controlled model railroad transmitting a first command from a first client program to a resident external controlling interface through a first communications transport. A second command is transmitted from a second client program to the resident external controlling interface through a second communications transport. The first command and the second command are received by the resident external controlling interface which queues the first and second commands. The resident external controlling interface sends third and fourth commands representative of the first and second commands, respectively, to a digital command station for execution on the digitally controlled model railroad.

Abstract: A magnitude comparator for comparing magnitude of a first data and a second data is disclosed. The first data and the second data are both binary data. The magnitude comparator includes many non-least comparator cells and a P-channel transistor. Each of the non-least comparator cells includes a first transistor, a second transistor, a third transistor and a fourth transistor. The drain of the second transistor is electrically connected to the source of the first transistor, and the source of the second transistor is electrically connected to a ground terminal. The third transistor electrically connects the first transistor, and the fourth transistor electrically connects the first transistor and the third transistor. The source of the P-channel transistor electrically connects a supply terminal, the gate of the P-channel transistor electrically connects the ground terminal, and the drain of the P-channel transistor electrically connects the third transistor of the first comparator cell.

Abstract: An electric motor control device includes a power supply unit that supplies power to a three-phase electric motor; a three-phase current sensor that individually detects three respective phase currents of the three-phase electric motor; a summing unit that calculates a three-phase sum by adding the three phase currents detected by the three-phase current sensor; a detected current correction unit that calculates correction amounts for at least two of the three phase currents based on a phase and an amplitude of the three-phase sum and then corrects phase current detection values by the calculated correction amounts; and a motor control unit that controls a power supply by the power supply unit to the three-phase electric motor by feedback control based on the three phase currents after correction by the detected current correction unit and on target currents.

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken.

Abstract: An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n?1, . . . , 0]) and a second n-bit operand (e.g., B[n?1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal Co (or its complement), where: C o = ( … ? ( ( C i ? ( A 0 + B 0 _ ) + A 0 ? B 0 _ ) ? ( A 1 + B 1 _ ) + A 1 ? B 1 _ ) ? … ? ( A n - 2 + B n - 2 _ ) + A n - 2 ? B n - 2 _ ) ? ( A n - 1 + B n - 1 _ ) + A n - 1 ? B n - 1 _ , “n” is a positive integer greater than one and Ci is a control input signal that specifies an interpretation to be given to the control output signal Co.

Abstract: A CPU and an image memory are provided in a printing apparatus. An interface circuit device for inputting/outputting signals representing image data is interposed between the CPU and the image memory. The interface circuit device constitutes of a plurality of SSTL circuits. One of two adjoining pixels in image data is changed into a non-inverted pixel, and the other is changed into an inverted pixel. In the SSTL circuits, to which inputted is a signal representing the one pixel, an input signal is inputted so as not to invert an input signal. In the SSTL circuits, to which inputted is a signal representing the other pixel as an inverted element, an input signal is inputted to the inverted element so as to invert an input signal. This suppresses an increase in cost and an increase in the size of a device, while reducing the current in impedance matching.

Abstract: A method for controlling for improper installation of sensors of a vehicle is provided. The method comprises the steps of determining a first indication of direction based at least in part on a yaw value, determining a second indication of direction based at least in part on a steering angle value, and changing the second indication of direction, if the first indication of direction and the second indication of direction are inconsistent with one another.

Abstract: An electrical circuit for comparing contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.

Abstract: The present invention relates to an autopilot system for a rotary wing aircraft operating relative to at least two pilot axes, which system comprises, for each of the two axes, at least one servo-control relationship providing a respective initial control instruction, with the two relationships having a common target; the system includes combination means (36) for providing a series of control instructions by combining the two initial control instructions (UCV, UTV).

Abstract: A method for compensating a steering system exhibiting dead-zone characteristics estimates the dead-zone parameters of the steering system and establishes a dead-zone inverse function utilizing the estimated parameters. The dead-zone inverse is utilized to transform steering orders in the dead-zone. Parameters of the dead-zone inverse are continuously up-dated with the utilization of the transformed steering order, the existing dead-zone parameters, and the present heading.

Abstract: A data recovery system for a serial digital data link includes a data sampler, compare logic, a phase controller, and a phase shifter. The data sampler samples input data three times in a bit time which time is determined by clock pulses generated by the phase shifter, and recovers digital data according to a predetermined decision criterion. The compare logic compares the output of the data sampler according to a predetermined method. Phase controller uses the output of the compare logic and generates phase control signals. The phase shifter uses the phase control signals and makes three different phase clocks from input clock. The input clock can be an external clock, or can be recovered from the external clock or input data stream.

Abstract: There is described a method for monitoring the load condition of a variable speed engine. Said method shows a determination of an actual speed and an actual load moment during operation. A warning signal is emitted when the actual load moment remains outside a monitoring range, predetermined depending on the speed, for the duration of a predetermined delayed reaction time.

Abstract: An electrical circuit for comparing contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.

Abstract: Apparatus and method for performing a high-speed, low-power bit-wise comparison of two digital words. For each bit, a bit comparator is shown, employing a compare node and a discharge node. After both nodes are charged, the discharge node is discharged and the condition of the compare node signals the result of the comparison. For each bit, a bit comparator is provided including a single transistor switch across the compare node and the discharge node. An exclusive-OR circuit connected to receive the corresponding bits of the words drives and selectively actuates the switch when the values of the corresponding bits are mismatched. Words may be segmented such that comparisons may be done segment-wise and the detection of a mismatch in any segment obviates the discharging of the compare node in segments containing more significant bits, to save power.

Abstract: A system, method and computer program for electronic documentation of information, such as medical information, on problem-specific templates that can be validated, in real-time, for completeness. The invention allows the user to organize, display, validate, archive, and export documentation of medical information on such problem-specific templates. By use of a recording device such as a digital pen, the invention combines the speed, ease of use, and familiarity of pen on paper with the data capture, real-time documentation validation, and real-time best practice prompts of traditional EMR systems. Interactive chart validation can be performed at will, rather than the traditional method of medical quality assurance, which consisted of chart review after for the patient had been cared for and discharged.

Abstract: A system and method for comparing binary data words are provided, which method includes splitting a first and a second data word (A, B) to be compared to one another into at least two subwords, one having high-order bits (hA, hB) and the other having low-order bits (nA, nB), and separately comparing each pair of the corresponding two subwords (hA, hB; nA, nB) in a separate comparing device. The intermediate comparison results of the comparing devices are gated in a logic device, e.g., an AND gate, to yield an overall result as a function of a control signal which is applied to a correction device, which is connected between at least one of the comparing devices and the logic device.

Abstract: A comparator having a small number of logic circuits and an improved operating speed is provided, where the comparator includes m number of bit comparators, each connected between a first node and a second node, comparing each corresponding bit between the first data and the second data, and connecting or disconnecting the first node and the second node, a charge unit connected between the first node and a first voltage and charging the first node with the first voltage, and a power connection controller disconnecting the second node and a second voltage in a first mode in response to a predetermined control signal and connecting the second node and the second voltage in a second mode, wherein the first node is charged with the first voltage in the first mode and the voltage level of the first node is output as a comparison result in the second mode.

Abstract: A data packet is received which includes an indication comprising a process state indication and a transmission state indication, the indication is compared with an expected indication, and it is determined if the data packet is valid or not based on a result of the comparison.

Abstract: An electrical circuit and method to compare contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.

Abstract: An interface and a method for image data transmission that is used for data transmission through a plurality of data lines is described, the correctness of the transmitted data being checked by reference to control data. The checking capability is achieved in that at least one item of control data is transmitted through each data line.

Abstract: A method and a device for determining the condition of roadway surfaces includes transmitting electromagnetic radiation at at least two different frequencies in the GHz range, reflecting and/or scattering the electromagnetic radiation by the roadway surface and subsequently receiving the electromagnetic radiation at the at least two frequencies. The condition of the roadway surface is determined on the basis of a comparison of the radiation intensities received at the different frequencies.

Abstract: The disclosure relates to a device for comparing two words, N and P, of n bits each. The device includes at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0=i=n?1. Moreover, each basic comparator block comprises: a first sub-block which can be used to generate a first signal indicating whether or not bits Ni and Pi are equal, said signal being generated at the output of the sub-block forming a first output (OUT_XORi) of the basic comparator block; a second sub-block which can be used to generate a second signal indicating which enables the second signal to pass to a second output (SOUTi) of the basic comparator block if the first signal indicates that bits Ni and Pi are not equal and which, in the opposite case, enables the second signal to be blocked.

Abstract: A power supply controller is used in a device including at least one component and at least one control board for controlling an operation of each component, and includes: a power supply section; and a power supply board for independently supplying a power supply voltage output from the power supply section to each of the component and the control board. The power supply board includes an output control circuit for independently controlling to output or to stop outputting the power supply voltage supplied from the power supply board to each of the components based on a signal indicating one of a normal state and an abnormal state of the power supply voltage used in each control board, which is fed back to the power supply board from each control board when the power supply voltage is supplied from the power supply board to each control board.

Abstract: A method and apparatus are provided for detecting a device change in a wireless network environment. The method includes receiving change information of a change device transmitted through a first channel, which is different from a second channel used by a plurality of devices, which form a wireless network, to transmit or receive data; storing the received change information; and reconfiguring the wireless network using the stored change information.

Abstract: A projection apparatus includes a first wireless unit receiving signals from a first external wireless remote controller, a second external wireless unit receiving signals from a second wireless remote controller, a signal-processing unit respectively coupled with the first wireless unit and the second wireless unit to receive signals, a CPU coupled with the signal-processing unit to receive processed signals from the signal-processing unit, and a projecting unit coupled with the CPU to perform a projecting function in accordance with the signal transmitted from the CPU.

Abstract: An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.

Abstract: An electrical circuit and method to compare contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit. The first counter circuit is for receiving a first enable signal INC_A and generating a first output signal SIG_A. The second counter circuit is for receiving a second enable signal INC_B and generating a second output signal SIG_B. The first enable signal INC_A and the second enable signal INC_B are for comparing the first output signal SIG_A to the second output signal SIG_B. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal SIG_A and the second output signal SIG_B. The logic circuit is for generating a second status signal defining a second relationship between the first output signal SIG_A and the second output signal SIG_B.

Abstract: A 2-bit binary comparator, including: a comparison unit for receiving a first bit and a second bit to thereby compare the first bit with the second bit; and an enable unit for outputting a comparison result of the comparison unit as an output of the 2-bit binary comparator according to an enable signal.

Abstract: A method and system for compositing a plurality of three-dimensional Sub-Images by examining the Depth values of the Pixels corresponding to same spatial location in each Sub-Image and compositing the content of the Pixel having the greatest Depth value. The Depth values are divided into two or more binary Segments, where the bit length of the Segments is determined according to their level of significance. In a first step, the numerical values of the Segments having the same level of Significance are simultaneously compared, and accordingly a group designating the Depth values which the numerical value of their Most Significant Segment is the greatest is determined, and a Grade is evaluated for the Least Significant Segments indicating their numerical size in comparison with the numerical value of the other Segments of the same level of significance.

Abstract: There is provided a test apparatus including a PLL circuit for generating a strobe signal of which the timing is shifted according to a given delay control voltage, a variable delay circuit being provided divergently from a path connecting the PLL circuit and the timing comparator and delaying the strobe signal according to the predetermined phase difference of the strobe signal for the output signal, and a first phase comparing unit for comparing a phase of the strobe signal output from the variable delay circuit and a phase of the output signal output from the device under test and supplying the delay control voltage according to the phase difference to the PLL circuit.

Abstract: A word recognizer for providing a channel-to-channel compare for an input digital signal divides channels of the input digital signal into equal-width input signal channel paths. One input signal channel path serves as a reference value for comparison with the other input signal channel path to produce the channel-to-channel compare.

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data An?1An?2 . . . A1A0 and a second binary data Bn?1Bn?2 . . . B1B0, and compare the first binary data and the second binary data to determine which of the first binary data and the second binary data is larger according to the following equation: F(A?B)=A(n?1)?·B(n?1)+(A(n?1)?+B(n?1))·{A(n?2)?·B(n?2)+(A(n?2)?+B(n?2)) . . . {A1?·B1+(A1?+B1)·(A0?+B0)}} where subscripts denote a position of a bit of the N-bit binary data and a prime (?) indicates that a bit is inverted, and outputting a signal corresponding to the comparison result.

Abstract: A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.

Abstract: A comparator for comparing binary numbers with N bits, where N>1, in which a plurality (200) of bit-to-bit comparators supplies a plurality of equality-difference signals, arranged in order of decreasing significance of the bits compared, to a matrix of transistors, arranged in 4 columns (201, 202, 203, 204) of N rows of transistors arranged in order, so as to control the gates of the transistors; the matrix, which receives, at the sources of the transistors of two (203, 204) of the columns, the signals representative of the bits of one of the numbers compared and their negated signals, is interconnected in a manner such as to identify the most significant difference by a simultaneous logic process, and to decide, on the basis of the bit signals received, which of the binary numbers is greater than, or greater than or equal to the other, presenting the outcome of the decision at an output (U2) within a very short time and with the use of much fewer active components than are required by conventional combin

Abstract: A device for acquiring the maximum value (or the minimum value) of a multiplicity of measured values, having a multiplicity of measuring points for acquiring the measured values, an a data line for transmitting data values between the measuring points, at least one of the measuring points having a comparator for comparing a data value received on the data line with its own measured value, and being configured to transmit its own measured value on the data line only if said measured value is not smaller than the data value, wherein the data line is a serial line for transmitting the data value in the form of successive bits of decreasing significance, wherein the comparator is a serial comparator which compares the received bits of the data value with the identically significant bits of its own measured value, and wherein the measuring point is configured to transmit each bit of its own measured value which is detected as being larger than the corresponding received bit, until a comparison reveals that the bit