Abstract: This application provides a communication method and an optical module. The method includes: A first optical module determines a first delay. The first optical module sends the first delay to an interface chip. According to the communication method and the optical module that are provided in this application, a delay in the optical module can be reported to the interface chip, so as to improve precision of time synchronization between a master clock and a slave clock, thereby further improving clock precision of a network device.

Abstract: A defrosting system for defrosting an evaporator assembly is disclosed. The system includes the evaporator assembly, an electrically resistive coating having an electrically insulative matrix and a conductive doping agent disposed on at least one surface of the evaporator assembly, and a plurality of electrical terminals arranged and disposed to supply electricity to the electrically resistive coating. A method for defrosting an evaporator assembly and a coating for heating evaporator assemblies are also disclosed.

Abstract: A matrix computation unit includes a systolic array of cells arranged along a first and second dimension, in which the systolic array of cells includes a first multiple of cells, each cell of the first multiple of cells including: a weight register configured to store a weight input; multiple activation registers, each activation register of the multiple activation registers configured to store a corresponding activation input; multiplexer circuitry communicatively coupled to the multiple activation registers and configured to select, from the multiple activation registers, one of the activation inputs as a selected activation input; and multiplication circuitry communicatively coupled to the weight register and to the multiplexer, in which the multiplication circuitry is configured to output a product of the weight input and the selected activation input.

Abstract: A I/O transmitter circuitry for supporting multi-modes serialization comprising a serializer, wherein said serializer comprising a multiple FIFO buffers, a multiple flip-flops including a first latch, a second latch, a third flop and a fourth flop, to hold data ready and stage the data for subsequent muxing, a 0-degree shifted clock and a 90-degree shifted clock and a multiplexer, wherein a read pointer reads one bit of data from each of the FIFO buffers, wherein the data is sampled into the respective flip-flops according to frequency of the 0-degree shifted clock and 90-degree shifted clock, wherein the data is outputted by the 0-degree shifted clock and 90-degree shifted clock via the multiplexer.

Abstract: An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.

Abstract: A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

Abstract: According to one embodiment, an electronic circuit includes a first delay element, a second delay element, a first hold circuit and a quantization circuit. The first delay element obtains a first signal by delaying a first pulse signal. The second delay element obtains a second signal by delaying the first signal. The first hold circuit holds a first voltage of an input signal corresponding to the first signal. The second hold circuit holds a second voltage of the input signal corresponding to the second signal. The quantization circuit obtains a third signal and a fourth signal each with different rising times based on a second pulse signal, to quantize the first voltage based on the third signal, and to quantize the second voltage based on the fourth signal.

Abstract: A processing system may include a systolic array including a plurality of processing elements (PEs) arrayed in M rows and N columns, where M and N are natural numbers and M is not equal to N. The processing system may further include a row buffer configured to transmit row data to the systolic array in a row direction, and a column buffer configured to transmit column data to the systolic array in a column direction. When the processing system is in a first mode, the row data is input data and the columns data is weights. When the processing system is in a second mode the row data is the weights and the column data is the input data.

Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites, such as by filling via opening and/or using jumpers, may form a deserializer circuit with a first via configuration or a first-in first-out (FIFO) circuit with a second via configuration.

Abstract: A sensor device includes a sensor array and a flow cell in fluid communication with the sensor array. Bias circuitry apply bias arrangements to the sensor array to produce sensor data. Peripheral circuitry coupled to the bias circuitry produces streams of data from the sensor array, the peripheral circuitry having an active mode and an idle mode. Logic to switch the peripheral circuitry between the active mode and the idle mode to control power consumption is provided. A temperature sensor may be included, and the logic can operate with feedback to switch between the active mode and the idle mode to maintain the temperature within an operating range.

Abstract: The embodiments of the present disclosure provide a shift register unit, a gate driving circuit and a driving method thereof, and a display device. The shift register unit, comprises two transfer gate modules (211, 212), four AND gate modules (231, 232, 233, 234), and two capacitor modules (241, 242), as well as a pulse signal input terminal (IN), four pulse signal output terminals (L1, L2, L3, L4), and a plurality of clock signal input terminals (CLK1 to CLK8). The shift register unit provided in the present disclosure can make the layout area occupied by the corresponding gate driving circuit reduce greatly as compared with that occupied by the gate driving circuit in the prior art, which facilitates border narrowing of the corresponding display device.

Abstract: A serializer includes: a data trigger circuit suitable for latching a plurality of input data based on a plurality of clocks having a predetermined phase difference to output a plurality of aligned data and a plurality of complementary aligned data; a hybrid multiplexing circuit suitable for outputting a pull-down signal and a pull-up signal that are selectively controlled based on a pull-down control signal which is generated by removing an input loading of the aligned data and a pull-up control signal which is generated by removing an input loading of the complementary aligned data; and an output driver suitable for outputting serial data corresponding to the pull-up signal and the pull-down signal.

Abstract: A data transmission system is provided. The data transmission system includes a plurality of data transmitters that respectively constitute a plurality of transmission lanes. Each of the plurality of data transmitters includes a serializer and an output signal storage circuit. The serializer coverts parallel input data into serial output data and outputs the serial output data. The output signal storage circuit stores the serial output data output from the serializer.

Abstract: A system and method generates optimized code for a source model. The system may include a resource sharing optimizer that evaluates the source model and replaces multiple model elements of the source model that are functionally equivalent with a single shared model element. The model elements replaced with the single shared model element may have different fixed point data types. The resource sharing optimizer may convert some of the fixed point data types to a common fixed point data type.

Abstract: A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

Abstract: A radio frequency receiving circuit, including: a tail current source, configure to be multiplexed to input radio frequency signals and amplify the radio frequency signals for producing a radio frequency current; a clock signal input unit, in connection with the tail current source and configured to input clock signals; a sampling-and-holding unit, in connection with the clock signal input unit and configured to output an orthogonal signal having a frequency of one half of a clock frequency; and a load unit, in connection with the sampling-and-holding unit. The radio frequency current flowing through the load unit is converted into a voltage which is modulated by the orthogonal signal, and a medium frequency signal having a frequency equivalent to a difference between a radio frequency signal frequency and an orthogonal signal frequency is output, whereby achieving the frequency mixing.

Abstract: Modular serializer and deserializer circuits convert a data input in a variety of applications. The serializer includes an array of cells that receive a parallel data input and transfer the word, row by row, to an output buffer that generates a corresponding serial data output. The deserializer includes an input buffer that receives a serial data input and transfers partial words sequentially through an array of cells. When the word fully occupies the cells, the array transmits the word as a parallel data output. A modular clock operates to clock the modular serializer and deserializer.

Abstract: A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.

Abstract: Circuitry is configured to store data in response to a phase transition of an input clock. The circuitry uses a master-slave latch configuration. Each of the master and slave latches includes respective feedback circuits, input circuits, and selection circuits. The feedback circuits drive outputs of the respective latches to values that are responsive to data stored in the latches. The input circuits drive the output of the respective latches to values that are responsive to data on an input of the latches. The selection circuits select between the feedback and input circuits based upon the phase of a clock signal.

Abstract: A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the first data so as to output the first data in accordance with the first clock, a second flip flop to receive the second data so as to output the second data in accordance with the first clock, a selector to select one of the first data and the second data so as to output the selected data in accordance with the first clock, and an adjustment unit to compare the second data to be received by the second flip flop and the first data output from the first flip flop so as to adjust, based on a comparison result, a timing for the first flip flop to receive the first data.

Abstract: An electronic device includes multiple functional logic modules each having a corresponding settling time, a clock generator element, and multiple memory elements. The clock generator element generates multiple clock signals having clock periods of a common duration. Each clock signal has a first clock transition and a second clock transition during each clock period, and a latest second clock transition of the clock signals in a particular clock period precedes an earliest first clock transition in a subsequent clock period by the settling time. Each memory element is clocked by a respective one of the clock signals, and each memory element includes an input latch clocked on a first clock transition of the respective one of the clock signals, and an output latch clocked on a second clock transition of the respective one of the clock signals.

Abstract: A de-serialization circuit includes a clock generation circuit, a first and a second latch circuit. The clock generation circuit is configured to generate a set of phase clock signals based on a first clock signal and a control signal. Each phase clock signal of the set of phase clock signals being offset from adjacent phase clock signals of the set of phase clock signals by a phase value. The first latch circuit is configured to generate a first set of data signals based on the set of phase clock signals and an input data signal. The second latch circuit is configured to generate a second set of data signals based on a first phase clock signal of the set of phase clock signals and the first set of data signals. Each signal of the second set of data signals being aligned with each other, wherein the first clock signal is non-continuous.

Abstract: A transmission circuit includes: a shift register configured to shift, in synchronization with a first clock signal, input parallel data within a plurality of flip-flop circuits; a control circuit configured to output a second clock signal of a phase in accordance with a phase of the first clock signal; a selector configured to select any one of the input parallel data and pieces of output parallel data of the plurality of flip-flop circuits; and a conversion circuit configured to convert, in synchronization with the second clock signal, the parallel data selected by the selector into pieces of serial data, in which the control circuit outputs a selection signal to the selector, in accordance with a deviation amount of the detected phase of the first clock signal.

Abstract: In a solid-state image sensing apparatus of an addressing method, a clock-conversion part generates a high-speed clock signal having a frequency two times or more the frequency of a low-speed clock signal. A signal processing part receives 10-bit pixel data through a horizontal signal line, performs predetermined signal processing, and passes parallel-format data to a switching part. The switching part selects each one bit of the parallel-format 10-bit data in a predetermined sequence to output from an output terminal using the high-speed clock signal from the clock-conversion part as a switching command, thus converts the parallel-format data into serial-format data, and passes it to an output buffer. The output buffer externally outputs differential output of normal video data and inverted video data individually from output terminals. Accordingly, the problems in power consumption, noises, and unnecessary radiation are solved, and higher-speed output is achieved.

Abstract: In a semiconductor device, the reset command input process may be executed by a simple method and circuit in a short period of time when a reset command is inputted compared to conventional art. A control circuit for the semiconductor device is adapted to control a clock generator for generating a system clock having a changeable frequency, wherein, in a normal operating mode of the semiconductor device, the control circuit changes the frequency of the system clock generated by the clock generator from a first frequency to a second frequency that is higher than the first frequency according to a reset command, and performs an interrupt process on the semiconductor device, so as to enter a reset sequence mode from the normal operating mode.

Abstract: The present invention discloses a gate drive circuit and a shift register. The gate drive circuit comprises a plurality of shift register circuits which are cascade connected, and each of the shift register circuits comprises a clock control transmission circuit and a NOR gate latch circuit, wherein the clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a gate drive pulse of a former stage to the NOR gate latch circuit, and the NOR gate latch circuit performs latch, and the NOR gate latch circuit is further triggered by a second clock pulse following the first clock pulse to output the gate drive pulse. With the aforesaid arrangement, the gate drive circuit of the present invention is applicable to CMOS process, and the power consumption is low and the noise margin is wide.

Abstract: An output circuit includes: an output portion which includes a plurality of output blocks each of which converts 2-bits parallel data to 1-bit serial data and outputs the converted serial data; a control signal generation circuit; a first clock generation portion; and a plurality of second clock generation portions which individually generate second clocks, wherein each of the output blocks includes: a latency expansion circuit which sequentially latches the 2-bits parallel data according to the reference clock and an inverted reference clock, selects two from the latched data signals based on the latency adjustment signal; and two-clocks flip-flop circuit which latches one of two outputs from the latency expansion circuit in synchronization with the second clock corresponding to the output block and latches the other of the two outputs from the latency expansion circuit in synchronization with the inverted second clock.

Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

Abstract: Disclosed are an apparatus and method for interfacing between a central processing unit (CPU) and a main memory unit, whereby a shared cache memory unit and the main memory unit are connected to each other using one optical signal transmission line. The apparatus for interfacing between the CPU and the main memory unit includes: a master optical connection protocol engine, converting operation control signals received from a shared cache memory unit of the CPU into serial signals; a first electrical-to-optical (E/O) converter, converting the serial signals converted by the master optical connection protocol engine into optical signals; a second E/O converter, converting the optical signals converted by the first E/O converter into serial signals; a slave optical connection protocol engine, converting the serial signals converted by the second E/O converter into operation control signals; and a memory controller having access to the main memory unit.

Abstract: Systems, methods, articles of manufacture and apparatus are disclosed to align actions of audio source monitors. An example method disclosed herein includes invoking an audience monitor to transmit a radio frequency (RF) initialization packet to a base unit, receiving an indication that the base unit has received the RF initialization packet at a first time, and invoking the base unit to transmit an RF acknowledgement packet to the audience monitor. The example method also includes receiving an indication that the RF acknowledgement packet is received by the audience monitor and waiting for an end to a delay period having a first value, identifying whether the audience monitor has finished processing the RF acknowledgement packet when the delay period ends at a second time, and incrementing the delay period to a second value when the audience monitor is still processing the RF acknowledgement packet and the delay period has ended.

Abstract: A bus system that has at least two lines. A bus subscriber has at least one connection element that has at least two contacts that can each be connected to one of the lines. An address allocation device can be used to ascertain an address for the bus subscriber in the bus system on the basis of a respective connection state of the contacts with respect to the lines. Also, a method allocates addresses in the bus system.

Abstract: Methods and systems provide a memory cell and a memory cell system for data serialization. In an embodiment, a half-rate serialization procedure uses a half-rate differential clock to output full-rate serial data. In an embodiment, the memory cell system includes two memory cells each receiving a respective data stream. Each memory cell may be controlled by a respective clock, the clocks being substantially mutually exclusive such that the output of each memory cell becomes alternately tri-stated. Based on the principle of a transistor tri-state or hold mode, if clocks of two memory cells are substantially mutually exclusive, then a tri-stated node can be driven by either of the memory cells in a substantially mutually exclusive manner, effectively multiplexing input parallel data to output serial data. The memory cell system may include a combination of different types of memory cells.

Abstract: To provide a display device with high image quality and fewer terminals. The present invention is made with a focus on the positional relation between a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit. The structure conceived is such that a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit are provided close to each other so that an RC load between the serial-parallel conversion circuit and the external connection terminal is reduced.

Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.

Abstract: Serializers are provided. The serializer includes a first drive control signal generator and a second drive control signal generator. The first drive control signal generator amplifies a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal. The second drive control signal generator amplifies a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal.

Abstract: A data input/output (I/O) device includes a plurality of data units and an I/O assembly. The plurality of data units is coupled to a global I/O (GIO) line through corresponding local I/O (LIO) lines and configured to receive or transmit a plurality of data groups through the corresponding LIO lines. At least one of the plurality of data units have a different operation speed. The I/O assembly performs serial/parallel conversion operations on the plurality of data groups including a high-speed data group and outputs results of the serial/parallel conversion operations. The high-speed data group is output from the at least one of the plurality of data units having the different operation speed.

Abstract: It is provided to implement a different number of logical slaves in a field device for use in an AS interface network as a function of the assigned address, which slaves may be addressed using the assigned address in the standard or in the expanded addressing mode. Thus, in a field device, it is possible to provide slaves having different profiles, via which different data types may be exchanged. Furthermore, a method is provided, with which a field device having different slaves is able to be addressed in a simple manner while avoiding double addressing.

Abstract: In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

Abstract: Provided are a signal processing apparatus and a signal processing method. The signal processing method include receiving a serial signal including an information frame including channel information and data information of a corresponding channel, extracting a clock signal from the serial signal, generating a load signal when a clock count reaches a maximum clock count by calculating the clock signal; converting the serial signal to a parallel signal according to the load signal, and changing the maximum clock count by comparing parallel-converted parallel channel information with a load count indicating the number of local signals.

Abstract: The disclosed conversion device converts an analog input signal into a digital signal and outputs thereof, wherein the conversion device comprises a feedback signal generator for performing mismatch shaping on the digital signal that has been converted and output, and then performing digital-analog conversion to generate a feedback signal; a subtractor for subtracting the feedback signal from the analog input signal and outputting thereof; a serial-parallel converter for converting the signal output from the subtractor into a plurality of parallel signals and outputting thereof; a vector filter for performing signal processing on the plurality of parallel signals output by the serial-parallel converter and outputting a plurality of signals; a quantizer for quantizing the plurality of signals output by the vector filter and outputting digital signals; and a parallel-serial converter for converting the digital signals output by the quantizer into serial signals and outputting thereof.

Abstract: In certain embodiments of the invention, a serializer has a transfer stage that transfers N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain and a serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that buffers the data and can be used to toggle the serializer between an N?1 operating mode and an N+1 operating mode.

Abstract: A serial-to-parallel converter includes a first register bank having first and second register groups, the first register bank configured to receive a communication signal having at least one bit for each unit interval (UI) of a system clock signal, the first register bank having a number of registers corresponding to a number of parallel processing stages, a second register bank having a plurality of register groups, each register group configured to receive the output of at least one of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank, and a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to a number of registers in the second register bank.

Abstract: In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.

Abstract: A serial-parallel conversion circuit for converting a high-speed serial signal to a parallel signal is provided. Further, a display device with high image quality and fewer external connection terminals is provided. Furthermore, a method for driving a serial-parallel conversion circuit for converting a high-speed serial signal to a parallel signal is provided. A serial-parallel conversion circuit includes a plurality of units in each of which a sampling switch and an amplifier are connected to each other. In the serial-parallel conversion circuit, each sampling switch is configured to output part of a serial signal to its respective amplifier only through one transistor.

Abstract: A first circuit operates in synchronization with a first clock having a first frequency, and generates N parallel data sets for every cycle period of the first clock. An interface circuit time-division multiplexes the N data sets received from the first circuit. A second circuit processes the N data set thus time-division multiplexed, in synchronization with a second clock having a second frequency which is N times the first frequency. A judgment unit judges whether or not the N data sets are effective data which instructs a flip-flop group, configured as a state holding element included in the second circuit, to generate an effective state transition. In a cycle period in which the N data sets are ineffective, a data replacement unit replaces at least a part of the N data sets with current compensation data DCMP.

Abstract: In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

Abstract: A first multiplexer, at each given cycle, outputs a second input data signal, after outputting a first input data signal. A second multiplexer, at each given cycle, outputs a fourth input data signal, after outputting a third input data signal. The second multiplexer outputs the third input data signal at a timing that coincides with the timing at which the second input data signal is output from the first multiplexer. At each given cycle, a third multiplexer, after outputting the first input data signal and the second input data signal output from the first multiplexer, outputs the third input data signal and the fourth input data signal output from the second multiplexer.

Abstract: In one embodiment, an apparatus may include a de-serializer to convert serial data into two parallel data streams, and a control unit to provide a first update signal and a second update signal based on a bit count of the serial data. The apparatus may further include a target component having an input bus, the input bus including a first portion and a second portion. The apparatus may further include a first output unit to provide the first set of parallel data to the first portion of the input bus, and a second output unit to provide the second set of parallel data to the second portion of the input bus.

Abstract: A transmission circuit includes: a plurality of lane blocks arranged in parallel to each other configured to convert parallel data supplied from a corresponding lane into serial data and output the serial data; and a clock enabler block including at least one clock enabler for outputting a drive clock phase-locked with a reference clock to the plurality of lane blocks after a plurality of cycles of the drive clock in response to an enable signal. Each of the plurality of lane blocks has a divider for dividing the drive clock supplied from the clock enabler block to generate a divide clock and a load signal, and a parallel-to-serial converter for converting parallel data supplied from the corresponding lane into serial data in synchronization with the divide clock and the load signal generated by the divider and the drive clock generated by the clock enabler block.

Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.