Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.

Abstract: A shift register SR configured to successively take in and hold input serial data on the basis of a first clock signal, a pattern detection section configured to detect a predetermined pattern contained in the serial data taken in the shift resister and a second clock generation section configured to determine timing of output of the serial data held in the shift register on the basis of a result of this detection are provided to detect the desired pattern contained in the serial data in the course of transferring the serial data for conversion from the serial data to parallel data to the shift resister, and to determine timing of conversion to the parallel data on the basis of a result of this detection, thus reducing the latency and achieving an improvement in communication speed and a reduction in circuit area.

Abstract: A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and a channel of high-speed serial data signal interface (e.g., transceiver) circuitry. To facilitate enabling the integrated circuit to support any of many possible different high-speed serial communication protocols, the channel is hard-wired to include a parallel data bus of fixed width for exchanging parallel data with the programmable circuitry. Regardless of the protocol being implemented, the full width of this bus is always used. A portion of the programmable circuitry is programmed to convert data between the block width and a group width, which can be different from the block width and which is used for the data elsewhere in the integrated circuit.

Abstract: A serial signal receiving device, includes: a serial-parallel converter that converts a transmitted serial signal into a parallel signal, wherein the serialized signal is obtained by the plural signal; a storage unit that stores phase difference information indicating a phase difference among the plural signals; and a correcting unit that corrects a phase relation among the plural signals of the parallel signal output from the serial-parallel converter based on the phase difference information stored by the storage unit.

Abstract: A parallel data output device includes a first latch circuit that latches and outputs one of at least two data signals input in parallel in accordance with a first clock signal; a second latch circuit that latches and outputs another of the at least two data signals in accordance with a second clock signal; and a phase set circuit that shifts at least one of a phase of the first clock signal and a phase of the second clock signal based on the phase of the first clock signal and the phase of the second clock signal.

Abstract: A data transfer apparatus includes a clock generation unit to generate a clock signal, a control unit to output parallel data and a reset signal, and a plurality of transmission units. Each of the plurality of transmission units uses continuous rising edges of a bit clock to sample the reset signal multiple times so that a phase shift of the reset signal between the transmission units is reduced, and the phase of the frequency dividing clock is aligned in each transmission unit.

Abstract: Some embodiments include apparatus and methods having an output line, clock nodes to receive clock signals, the clock signals being out of phase with each other, and selector circuits to receive data in parallel. In at least one embodiment, the selector circuits are responsive to the clock signals to transfer the data serially to the output line. Such apparatus and methods can also include a control unit to influence a portion of a signal that represents at least a portion of the data at the output line. Additional apparatus and methods are described.

Abstract: In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.

Abstract: A parallel-to-serial converting circuit includes a first alignment unit configured to receive and serially align parallel data included in a first group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit also includes a second alignment unit configured to receive and serially align parallel data included in a second group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit further includes a third alignment unit configured to serially align and output the serially aligned parallel data that is output from the first alignment unit and the second alignment unit. The first alignment unit and the second alignment unit drive an output node in response to activated data of received parallel data.

Abstract: In one embodiment, a semiconductor integrated device includes a plurality of semiconductor chips each having a first internal circuit and a second internal circuit and being stacked while displaced from each other. The first internal circuit processes a data signal in accordance with a predetermined process. The second internal circuit receives a request signal from a transmission source and determines whether the request signal is a request to itself or not. When the request signal is the request to the second internal circuit itself, the second internal circuit receives a data signal from a transmission source and outputs the data signal to the first internal circuit. When the request signal is not the request to the second internal circuit itself, the second internal circuit transfers the request signal to a transfer destination, receives the data signal from the transmission source and transfers the data signal to the transfer destination.

Abstract: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage. A bias element may bias the output node to a second voltage. Each of the switches may be controlled by a respective one of the sample signals.

Abstract: A serializer includes a first stage configured to convert m-bit-wide parallel data into n-bit-wide parallel data, where n is 2x, m?2x+y, x is an integer of at least 1, and y is an integer of at least 1, where the first stage includes a memory unit configured to store the m-bit-wide parallel in response to a timing signal and a first multiplexer configured to output the n-bit-wide parallel data in response to a frequency-multiplied derivative of the timing signal, and a current mode logic (CML) multiplexer stage configured to convert the n-bit-wide parallel data into serial data on successive transitions of n phase-shifted versions of the frequency-multiplied derivative of the timing signal.

Abstract: A parallel-to-serial converting circuit includes a first alignment unit configured to receive and serially align parallel data included in a first group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit also includes a second alignment unit configured to receive and serially align parallel data included in a second group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit further includes a third alignment unit configured to serially align and output the serially aligned parallel data that is output from the first alignment unit and the second alignment unit. The first alignment unit and the second alignment unit drive an output node in response to activated data of received parallel data.

Abstract: A data transmitting circuit that converts parallel data into serial data to output the serial data, includes a first data input port that receives first parallel data at a first data rate based on a reference input clock; a second data input port that receives second parallel data at a second data rate lower than the reference input clock, a data expansion unit that generates expanded data by expanding a bit number of the second parallel data to a bit number of the first parallel data, a serial data generation unit that performs a process for generating first serial data by performing a serial conversion on the first parallel data based on the reference input clock and a process for generating second serial data by performing a serial conversion on the expanded data, and a data output port that outputs the first serial data or the second serial data.

Abstract: An adaptor for a memory card includes a printed circuit board (PCB) conversion board, a memory card connector, a serial interface connector, a signal convertor, and a parallel interface connector. When a motherboard is connected to the serial interface connector, serial signals output from the motherboard are transmitted to the signal convertor via the serial interface connector. The signal convertor converts the serial signals into parallel signals and transmits the parallel signals to the memory card. When the motherboard is connected to the parallel interface connector, parallel signals output from the motherboard are transmitted to the memory card via the PCB conversion board without any parallel-to-serial signal conversion.

Abstract: There is provided a parallel-serial converter including a selector to convert parallel data to serial data, a flip-flop to which the serial data are input so as to latch the serial data, a generator to generate replica data simulating the serial data, a detector to detect a first switching point of the replica data and a second switching point subsequent to the first switching point, and a controller to control relative timings of timing converted to the serial data in the selector and timing when the serial data is latched in the flip-flop, based on the first switching point and the second switching point.

Abstract: An apparatus for processing digital input signals transferred from a plurality of circuit breakers includes: a plurality of signal input terminals configured to receive a plurality of digital input signals, which are generated from the plurality of circuit breakers and indicate an ON/OFF state of the plurality of circuit breakers, in parallel; a digital input signal parallel-to-serial converting unit configured to convert the parallel digital input signals from the plurality of signal input terminals into serial digital input signals, and output the converted serial digital input signals according to a control signal; and a controller configured to receive and process the serial digital input signals transferred from the digital input signal parallel-to-serial converting unit, and transmit the control signal to the digital input signal parallel-to-serial converting unit.

Abstract: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.

Abstract: A parallel to serial conversion circuit makes output data normally swing even in a high-speed operation. The parallel to serial conversion circuit includes a main selection block configured to drive an output node sequentially in response to data on a first line and data on a second line, and a subsequent selection block configured to drive the output node sequentially in response to data on a subsequent first line and data on a subsequent second line, wherein the output node is driven by inverted data of the data on the subsequent first line and inverted data of the data on the subsequent second line.

Abstract: A unit timing signal synchronized with a high-order transmission frame is used for measuring a difference between the number of data pieces of a client signal mapped to the high-frequency frame and the number of data pieces of the output client signal by integrating the difference therebetween for each unit timing signal. Then stuffing and de-stuffing operations are performed so that a integration result is zero.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: A semiconductor device includes a plurality of synchronization blocks configured to sequentially synchronize a plurality of input signals swinging in a complementary metal oxide semiconductor (CMOS) region with multi-phase clock signals to output a plurality of output signals swinging in a current mode logic (CML) region, a plurality of first swing region converting blocks configured to convert the plurality of output signals to a plurality of converted output signals swinging in the CMOS region, a serialization block configured to serialize a plurality of converted output signals, thereby outputting a serialized signal swinging in the CML region, and a second swing region converting block configured to convert the serialized signal to a serialized output signal swinging in the CMOS region.

Abstract: A parallel to serial conversion circuit includes a plurality of switching units and a voltage output unit providing an operating voltage for the switching units. Each of the plurality of switching units is operable to receive a first clock signal and a second clock signal which have the same frequency, a phase shift exists between the first clock signal and the second clock signal for each of the switching units, and a phase difference exists between the first clock signals received by adjacent two switching units of the plurality of switching units. The plurality of switching units receive data bits of parallel data in sequence according to the phase difference, particularly, each of the plurality of switching units receives one data bit within a time window corresponding to the phase shift. In comparison with the prior art, the inventive solution implement the parallel to serial conversion using a single system clock frequency, so that the complexity and power consumption of the system is reduced.

Abstract: An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units.

Abstract: Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.

Abstract: Aspects of the disclosure provide a circuit using digital techniques to generate a differential signal with a low skew. The circuit can include a first switching element configured to receive at least a first logic value and a second logic value, and output a first signal of the differential signal, the second logic value being different from the first logic value. Further, the circuit can include a second switching element configured to receive at least the first logic value and the second logic value, and output a second signal of the differential signal.

Abstract: A system and method for data transmission between an intelligent electronic device (IED) and a device, such as a remote display or input/output (I/O) device, are provided. Each data line of the IED is input into a serializer and transmitted over a serial link to a deserializer and then provided to the inputs of remote device, such as a remote display or input/output (I/O) device. The serial link can be made of any media such as copper, fiber optics, etc. The serial link can be formed as one, two or more channels.

Abstract: A signal transmission system in which a serializer IC connected to first parallel signal wirings and a deserializer IC connected to second parallel signal wirings are connected by a transmission line. Among input terminals of the serializer IC, redundant input terminals which are not connected to the first parallel signal wirings are connected to one wiring obtained by branching off the first parallel signal wirings. When parallel signals are converted into a serial signal, their bit data is arranged into the serial signal which is temporally continuous. Thus, the number of transition times of the serial signal is reduced and radiation noises can be suppressed.

Abstract: A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

Abstract: A transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data in synchronization with the serial clock. The transmission clock generator receives the serial clock to generate a transmission clock that has a same delay as the N-bit serial data, and the data transmission circuit simultaneously transmits the N-bit serial data and the serial clock.

Abstract: A physical layer (PHY) device includes a first encoder that receives a first data stream at a first data rate, that encodes the first data stream using a first type of encoding, and that outputs first encoded data. A second encoder receives a second data stream at a second data rate different than the first data rate, encodes the second data stream using a second type of encoding different than the first type of encoding, and outputs second encoded data. An output selector outputs the first encoded data to a serializer of the PHY when the PHY transmits at the first data rate, and outputs the second encoded data to the serializer when the PHY transmits at the second data rate.

Abstract: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A method, system, and apparatus of a balanced rotator conversion of serialized data are disclosed. In one embodiment, a method to convert serialized data includes acquiring a rotator module output, and generating a balancing signal with a reference module, which operates with a reference frequency. The method further includes processing the rotator module output and the balancing signal in an interpolation module to generate a balanced rotator output. The method may include a rotator module output that is generated by an analog phase rotator when a control voltage is received by the analog phase rotator. The reference module may include an other analog phase rotator to generate a balancing signal. The interpolation module may interpolate the balancing signal and the rotator module output to modulate a phase of the balanced rotator output. The balanced rotator output may include an orthogonal output.

Abstract: There is provided a PLL circuit 15, a voltage follower 19, and an output terminal 23, and a control voltage V1 of a voltage controlled oscillator circuit in the PLL circuit 15 is outputted to the output terminal 23 via the voltage follower 19.

Abstract: A programmable logic device (PLD) data transfer cable includes a parallel interface, a programming interface, and a logic control circuit. The parallel interface is used for connecting to PLDs. The logic control circuit includes a first group of transmission channels, a second group of transmission channels, a first group of switches, and a second group of switches. The first and second group of switches control the working status of the first and second group of transmission channels respectively. The electrical connections between pins of the parallel interface and the programming interface when first group of transmission channels are activated are different with those when second group of transmission channels are activated.

Abstract: A Serializer/Deserializer apparatus comprises a serializer adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block adapted to start the serializer means, and a count block. The serializer comprises flip-flops and muxes, and is adapted to N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter. The transmitter enable block comprises an inverter and flip-flops, and is adapted to start the serializer. The transmitter enable block comprises an inverter, flip-flops, and a NOR gate, and is adapted to create a waveform which programs data loading in the serializer.

Abstract: An integrated circuit comprises a first microcontroller unit located on a first die. The first microcontroller unit includes a first processing core for providing a parallel stream of data. A second microcontroller unit is located on a second die and includes a second processing core for receiving the parallel stream of data. Voltage isolation circuitry transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream and provides galvanic isolation between the first microcontroller unit and the second microcontroller unit.

Abstract: A system and process for receiving a variable pulse width signal and measuring and serially sending the measurements to a receiver that deserializes and regenerates the variable pulse width signal. Data bits may be embedded with the variable pulse width clock measurements and serially sent out. The measurements are illustratively accomplished using a reference clock and a phase locked loop.

Abstract: Signal transition feature based coding for serial link is described herein. According to one embodiment, in response to a data stream transmitted onto a serial communication link, one or more bits of the data stream are encoded according to bit order determined based on a frequency of signal transitions of the data stream. As a result, a sequence of encoded data stream having a lower number of bit transitions with respect to the frequency of signal transitions of the data stream prior to the encoding is generated. Thereafter, the encoded data sequence is transmitted onto the serial communication link. Other methods and apparatuses are also described.

Abstract: A parallel to serial conversion circuit includes a plurality of switching units and a voltage output unit providing an operating voltage for the switching units. Each of the plurality of switching units is operable to receive a first clock signal and a second clock signal which have the same frequency, a phase shift exists between the first clock signal and the second clock signal for each of the switching units, and a phase difference exists between the first clock signals received by adjacent two switching units of the plurality of switching units. The plurality of switching units receive data bits of parallel data in sequence according to the phase difference, particularly, each of the plurality of switching units receives one data bit within a time window corresponding to the phase shift. In comparison with the prior art, the inventive solution implement the parallel to serial conversion using a single system clock frequency, so that the complexity and power consumption of the system is reduced.

Abstract: A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on

Abstract: A device for parallel-serial conversion of several evaluation parameters determined respectively by a detector from detected signal values. The device includes a primary buffer memory for the synchronized buffering of each determined evaluation parameter, a synchronization unit for the generation of a synchronization signal for the synchronized buffering and a unit for the serial readout of the evaluation parameters stored in a synchronized manner in the primary buffer memory. A synchronization signal generated by the synchronization unit is derived from a release signal which provides the highest data rate of all the release signals associated respectively with the determined evaluation parameters.

Abstract: A semiconductor device includes a plurality of synchronization blocks configured to sequentially synchronize a plurality of input signals swinging in a complementary metal oxide semiconductor (CMOS) region with multi-phase clock signals to output a plurality of output signals swinging in a current mode logic (CML) region, a plurality of first swing region converting blocks configured to convert the plurality of output signals to a plurality of converted output signals swinging in the CMOS region, a serialization block configured to serialize a plurality of converted output signals, thereby outputting a serialized signal swinging in the CML region, and a second swing region converting block configured to convert the serialized signal to a serialized output signal swinging in the CMOS region.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: A serial signal receiving device, includes: a serial-parallel converter that converts a transmitted serial signal into a parallel signal, wherein the serialized signal is obtained by the plural signal; a storage unit that stores phase difference information indicating a phase difference among the plural signals; and a correcting unit that corrects a phase relation among the plural signals of the parallel signal output from the serial-parallel converter based on the phase difference information stored by the storage unit.

Abstract: An electronic device is described. The electronic device includes a first integrated circuit (IC) and a second integrated circuit (IC). The electronic device also includes a multiplexer configured to multiplex a parallel data signal into a serial data signal, and a transmitter configured to transmit the serial data signal from the first IC to the second IC. The electronic device further includes a receiver configured to receive the serial data signal. The receiver includes a clamp circuit configured to clamp the voltage swing of an analog node within a determined range. The clamp also helps to extend the bandwidth of the receiver.

Abstract: A digital signal transmitting apparatus includes an encoder which converts parallel input signals of multiple channels into serial data in a manner synchronized with a first clock signal, and a decoder which converts the serial data into parallel output signals of the multiple channels in a manner synchronized with a second clock signal operating in a manner asynchronous with the first clock signal. The serial data has a different period and a different duty factor corresponding to each combination of the logical values of the parallel input signals of the multiple channels.

Abstract: This invention relates to a pattern recognition correlator implemented entirely in the electronic domain. The correlator has a serial to parallel conversion means to convert input serial binary data into at least one input parallel binary electrical signal and a comparator to compare the or each input parallel data signal with a reference parallel binary data signal. The serial to parallel conversion means may comprises a demultiplexer to effectively slow the data update rate and a series of latch circuits to provide the parallel data signal. The comparator may be arranged to perform bit addition and may be arranged such that a zero total sum is an indication of correlation. The bit addition may be performed b an array of logic gates.