Abstract: A general-purpose processor performs high-speed variable-length decoding. The general-purpose processor includes a video data register for exclusively storing the variable-length code that stores data having a length larger than the maximum length of the variable code to be decoded. The general-purpose processor also includes a data counter register for exclusively storing the length of the data in the video data register which has not been decoded, as well as a pointer register for exclusively storing the address of the variable-length code to be read out next from a bit stream stored in memory. The general-purpose processor also includes an ALU for performing general purpose operations, and decodes the variable-length code stored in the video data register by controlling the video data register, the data counter register, and the pointer register.

Abstract: A circuit for determining a discrete amplitude of a set of samples xks comprising two integrators that produce integrated signals uk and vk, a converter which supplies an input to the first integrator, timing elements which produce delayed signals uk−1 and vk−1, and a vector quantizer Q(xk, uk−1, vk−1) configured to provide a binary output as a function of samples xk and the integrated signals uk−1 and vk−1.

Abstract: A device for performing a search for the optimum code vector in a codebook having N code vectors indexed by i has a controller which considers each ith code vector, and a processor which determines in two clock cycles whether said ith code vector is the current optimal code vector.

Abstract: Disclosed is a method of digital data conversion. The method comprises the following steps of: binding input digital data into unit blocks constituted by a plurality of bytes; modulation-coding each byte of the input data blocks by using a code conversion table; and allocating a merging bit in block unit for the modulation-coded input data in block unit.

Abstract: A method of modulating and a method of demodulating for a run length limited (RLL) code having an improved direct current (DC) suppression capability. Received data is modulated using a DC suppression control code group which is separate from a data modulation conversion code group. The DC suppression control code group maximizes use of the characteristics of codewords in conversion code groups, such as, the sign of parameter CSV representing the DC value within a codeword and the characteristics of parameter INV predicting the DSV transition direction of the next codeword, while relaxing the redundant codeword generation condition or the condition of usable codewords compared with the data modulation conversion code group. Therefore, the number of codewords increases, so that the probability of DC suppression control further increases.

Abstract: A decoding apparatus using tables T1, T2, and T4 has a buffer memory (1), a code word separation circuit (2), a comparator (31), and an addition circuit (4). In the table T1, decoded data items corresponding to each code word are stored based on each code length as index. In the table T2, addresses in the table T1 corresponding to the minimum value in code words having each code length is stored based on the code length as index. In the table T4, the number of code words having each code length is stored based on the code length as index. The buffer memory (1) stores the real data part in a bit stream transferred from outside. The code word separation circuit (31) separates each bit data item from the buffer memory (1). The comparator (31) analyses the content of the data item transferred from the code word separation circuit (2). The addition circuit (4) adds the output from the comparator (31) to the output from the table T2.

Abstract: A method for designing a computer program for finding a low-complexity coder for constrained block codes for application to timing recovery or error control in data recording systems. The method includes (1) decomposing an input set of candidate codewords into simple subsets of codewords, (2) providing, for each simple subset of codewords, a respective subset of datawords, and (3) filling in certain coordinates in the datawords by values of certain coordinates in the codewords.

Abstract: A new LZW compressor implementation architecture utilizes a plurality of character tables corresponding to the respective characters of the alphabet. A string is stored by storing the code associated with the string in the character table corresponding to the extension character of the string at a character table location corresponding to the code of the string prefix. A search for the longest matching string is performed by determining if the character table location is empty corresponding to the code of the currently matched string in the character table associated with the currently fetched character. If the location is not empty, it is storing the code of the string comprising the currently matched string extended by the currently fetched character. This string code is used as the next match with which to continue the search with the next fetched character. When the location is empty, the longest match has been determined to be the currently matched string.

Abstract: A code converter of the present invention converts m data bits to n channel bits (m<n) and records the n channel bits in a recording medium. The code converter includes a basic table made up of a plurality of tables smaller in number than 2m defined on the basis of a bit pattern required of the codes. A converting circuit codes all data of the m data bits to the n channel bits by calculation using the basic table. The code converter is operable with a minimum number of tables and therefore with a minimum of circuit scale.

Abstract: A method and apparatus is provided for translating an L-bit put signal to a W-bit output signal such as a virtual network identification signal to an internal virtual network signal. The translation is performed using a multi-stage lookup. The input signal is portioned into a plurality of subsets of bits. A first index to a first stage is provided by combining a portion of bits and a first delta subset of bits. A second index to a second stage is provided by combining data stored at the first index in the first stage and the a second delta subset of bits. The corresponding output signal is stored at the last index in the last stage. The use of the multi-stage lookup instead of a single-stage lookup reduces the memory required to perform the translation.

Abstract: A method of adapting a connection structure forming part of a dictionary in a computer memory device is provided. The structure includes a plurality of interface connections and a plurality of non-interface connections, with each interface connection representing a symbol, and the presence or absence of a chain of non-interface connections in which the symbol is represented, and each non-interface connection representing a relationship between two symbols, two non-interface connections, a symbol and a non-interface connection, or a non-interface connection and a symbol. The method includes determining alternative relationships between pairs of symbols, non-interface connections, and symbols and non-interface connections within the structure, and removing existing non-interface connections from the structure and inserting new non-interface connections into the structure according to relative numbers of occurrences of the alternative relationships within the dictionary.

Abstract: In a data decompression system of the type having a self-compiling dictionary for building or replicating codes used for decoding incoming code values, there is provided a decoded string dictionary or memory for storing plural characters representing decoded strings. The decoded strings may be stored in a modified dictionary replacing string codes or stored in a separate variable length memory as blocks of characters having predetermined length and accessed using a finder memory. If the decoded string becomes too long to be stored in a fixed length memory, a conventional decoder dictionary may be used to reduce the size of the strings stored for direct access and read out to a recovered data stream.

Abstract: A method and apparatus is provided for translating an L-bit input signal to a W-bit output signal such as a virtual network identification signal to an internal virtual network signal. The translation is performed using a multi-stage lookup. The input signal is portioned into a plurality of subsets of bits. A first index to a first stage is provided by combining a portion of bits and a first delta subset of bits. A second index to a second stage is provided by combining data stored at the first index in the first stage and the a second delta subset of bits. The corresponding output signal is stored at the last index in the last stage. The use of the multi-stage lookup instead of a single-stage lookup reduces the memory required to perform the translation.

Abstract: A system for encoding data is provided. The system includes a number parser that breaks down a field that has many digits into a set of data strings that each has a fixed number of digits. A logarithmic converter is connected to the number parser, and converts each data string into a compressed string that has less than the fixed number of digits. A compiler connected to the number parser and the logarithmic converter receives the compressed strings from the logarithmic converter and forms a new field that has many digits.

Abstract: A new LZW compressor implementation architecture utilizes a plurality of limited length character tables corresponding to the respective characters of the alphabet. A string is stored by storing the code associated with the string in the character table corresponding to the extension character of the string at a character table location corresponding to the code of the string prefix. A character table is created when the character corresponding thereto is first encountered in the input. The input data character stream is searched by comparing the input stream to the stored strings to determine longest matches therewith. The codes associated with the longest matched strings are outputted so as to provide an output stream of compressed codes. The respective lengths of the character tables are limited in accordance with the frequency of occurrence of the characters of the alphabet.

Abstract: A data compression and decompression system based on the LZW data compression and decompression methodology that includes exclusion tables for storing strings that are infrequently encountered. If an extended string formed for updating the compressor and decompressor dictionaries is included in the exclusion tables, the extended string is not stored and the code counter for assigning codes to dictionary strings is not advanced. In this manner, dictionary codes are not usurped by infrequently encountered strings. The exclusion tables are dynamically modified in accordance with the input data by deleting strings from the exclusion tables that are frequently encountered therein and by adding infrequently encountered strings to the exclusion tables.

Abstract: A method and apparatus are provided for modulating code for use with written optical disks such as digital video disks (DVD). The invention falitates 8/16 modulation by eliminating duplicate code conversion and by reducing the number of times that conversion codes must be looked up from a conversion table. A conversion code corresponding to a received input code is specified from among a plurality of conversion codes. Duplication information corresponding to the input code is read from a pre-processing table and duplicate information indicated duplicate conversion codes in the plurality of conversion codes is stored. Conversion code corresponding to the input code is read from the conversion table and is selectively stored with duplicate conversion codes being omitted.

Abstract: A programmable video interface (20) eliminates the need for select-in-test parts during manufacture. The video interface (20) includes a scaling module (40) and a programming module (60). The scaling module (40) converts an analog input signal into a digital output signal based on a plurality of analog programming signals. The programming module (60) generates the plurality of analog programming signals, where the analog programming signals maintain operation of the scaling module at a predetermined transfer characteristic and an associated tolerance. The programming module generates the plurality of analog programming signals based on digital programming data. The use of D/A converters (62, 64) in the programming module (60) allows the elimination of resistor divider networks and associated tolerance problems.

Abstract: A method and apparatus is provided for translating an L-bit input signal to a W-bit output signal such as a virtual network identification signal to an internal virtual network signal. The translation is performed using a multi-stage lookup. The input signal is portioned into a plurality of subsets of bits. A first index to a first stage is provided by combining a portion of bits and a first delta subset of bits. A second index to a second stage is provided by combining data stored at the first index in the first stage and the a second delta subset of bits. The corresponding output signal is stored at the last index in the last stage. The use of the multi-stage lookup instead of a single-stage lookup reduces the memory required to perform the translation.

Abstract: A method and circuit for compression and decompression of data. For compression, successive units of input data are received in first register and second registers. The contents of the registers are used to address a lookup RAM, and the data stored in the lookup RAM is used to address a dictionary RAM. If output data from the dictionary RAM does not match output data from the first and second registers, a value from a dictionary counter is stored in the lookup RAM. If output data from the dictionary RAM matches output data from the first and second registers, data read from the lookup RAM is fed back for storage in the first register. The data from the first and second registers is provided as compressed output data. For decompression, the compressed data are used to populate another dictionary RAM, which is used to reconstruct the uncompressed data.

Abstract: Huffman encoding, particularly from a packed data format, is simplified by using two different table formats depending on code length. Huffman tables are also reduced in size thereby. Decoding is performed in reduced time by testing for the length of valid Huffman codes in a compressed data stream and using an offset corresponding to a test criterion yielding a particular test result to provide a direct index into Huffman table symbol values while greatly reducing the size of look-up tables used for such a purpose.

Abstract: A data compression and decompression system based on the LZW data compression and decompression methodology that includes exclusion tables storing strings that are infrequently encountered. If an extended string formed for updating the compressor and decompressor dictionaries is included in the exclusion tables, the extended string is not stored and the code counter for assigning codes to dictionary strings is not advanced. In this manner, dictionary codes are not usurped by infrequently encountered strings.

Abstract: A look-up table scheme for performing non-return-to-zero inverted (NRZI) encoding on input data bytes. Also disclosed is a look-up table scheme for performing zero-insertion in data streams that so require. An address is formed from an input data byte and is then used to look-up the corresponding encoded/translated byte.

Abstract: A retrievable memory is provided with a priority encoder. The priority encoder is constituted by encoder units. Each of the encoder units is constituted by an inverter, N-channel MOS transistors and an AND gate. Upon receipt of a signal of H level from a matching line, the encoder unit outputs a signal of H level to a word line, and also outputs a signal of L level to a matching line active signal line MLA1. Then, the encoder units respectively output signals of L level to the word lines. Consequently, even when a plurality of results of a retrieving process are obtained, it is possible to output single data.

Abstract: Logic circuitry performs a matching algorithm function. A memory produces a match signal that indicates which memory cells contain data that matches input address data to the memory. A first logic AND function performs a logic AND between a current value of the match signal currently produced by the memory for the input address data with a prior value of the match signal produced by an immediately prior input address data. A buffer holds index data. A second logic AND function compares output of the first logic AND function with the index data. Output of the second logic AND function is returned to the buffer as new index data. Index logic generates an offset based on the index data stored in the buffer. A send byte function asserts a send byte signal when the match signal is zero and when the output of the second logic AND function is zero. A length counter is incremented for every cycle in which the send byte signal is not asserted.

Abstract: A method for mapping 2N message N-tuples into 2N+1 codeword (N+1)-tuples is developed. The 2N+1 codeword (N+1)-tuples are categorized into M subsets of codeword (N+1)-tuples, wherein M is an integer larger than 1, each subset G has NG codeword (N+1)-tuples and the total number of codeword (N+1)-tuples in the M subsets is 2N. Each subset G has a predetermined number KG of lower bits and a predetermined number (N+1−KG) of higher bits, and the number of lower bits in every codeword (N+1)-tuple in any subset is not equivalent to that of lower bits in every codeword (N+1)-tuple in any other subset. The 2N message N-tuples are matched with the 2N codeword (N+1)-tuples in the M subsets, respectively, in one-to-one correspondence to generate a lookup table.

Abstract: The present invention provides a novel method and system for obtaining maximum system speed performance for compressing coded data characters in a serial data stream by replacing strings of data with code values stored in a dictionary when strings are first observed as unique strings in the data stream. A novel pointer address is generated to represent new strings to be searched in the dictionary. The novel pointer address comprises a string code portion representative of the last matched string found in the dictionary and appended thereto an extension character code portion representative of the next character taken from the input data stream. The dictionary is constructed large enough to provide a unique memory location for every possible pointer address. The unique pointer address, representative of a string of data in the input data stream, is employed as an address pointer to access the memory.

Abstract: In an inversely quantizing method of determining an inverse quantization value Y from an original quantization index value X, scale conversion is performed to a quantization index value X1 as at least a part of the original quantization index value X to produce first and second values which indicate the quantization index value X1. Then, first and second tables are referred to based on the first and second values, to determine third and fourth values corresponding to the first and second values, respectively. Then, an inverse quantization value Y is determined from the third and fourth values.

Abstract: A method and system for overriding error correction capabilities of digital optical media is provided. The overriding of the error correction codes (ECC) is accomplished by causing a non-correctable pattern of erroneous symbols to occur in the ECC codeword. Specific redundancy symbols are replaced with invalid symbols. The non-correctable error pattern is recognized by the ECC decoder as being non-correctable and the ECC decoder does not attempt to change the values of any symbols of an ECC codeword that is contaminated by the detectable non-correctable error pattern.

Abstract: A method for compressing text, comprising the steps of splitting a main character string into component strings, and counting the frequency of occurrence of each component string in the main character string and ordering the component strings in their frequency of occurrence. The method also comprises a step of allocating to each component string a token value representative of the component string and determined by the frequency of occurrence of the component string, storing the token value so allocated as a token table in which tokens are associated with component strings, and allocating to each component string in the main character string the token value for that component string from the token table to generate a sequence of token values representing the main character string in a compressed format.

Abstract: What is disclosed is a method that consists of constructing a bit-serial decoding table for a list of variable length codewords without the use of a binary decoding tree, and decoding using the decoding table, in a bit serial fashion, a bitstream encoded using those variable length codewords.

Abstract: The subtracter performs subtraction processing between a pointer outputted from the pointer register and code words candidate outputted from the code word count storing circuit, and in accordance with whether the result is negative or positive, determines the code words of input data words. Code word candidates stored in the code word count storing circuit are created according to a finite-state transition diagram stored in the state transition storing circuit. An encoder and a decoder are thus made compact and faster.

Abstract: Information systems which provide access over a variety of devices (e.g. telephones, automated banking machines, computers) typically require that passcodes be numeric to allow entry on all device types. Alphabetic characters are associated with the numeric digits on both telephones and automated banking machines, allowing users to use mnemonic words to remember their numeric passcodes. Computer terminals do not have this association, creating user difficulties. The invention translates text entry on a computer keyboard into the equivalent numeric digits according to an appropriate mapping.

Abstract: An allocating method of allocating a run length limited (RLL) code having enhanced direct current (DC) suppression capability, modulation and demodulation methods, and a demodulation apparatus are provided. In order to control DC suppression, a pair of code groups having suppression controlling capability are allocated, and a (1, 8, 8, 12) code having DC suppression capability, in which a code word of the pair of code groups has the sign of code word sum value (CSV) parameter, which represent DC value in a code word, and the characteristic of an INV parameter, which predicts the transition direction of digital sum value (DSV) of the succeeding code word, both opposite to those of the code word which belongs to the other code group and corresponds to the same source code, is used and is appropriate to high-density optical disc system.

Abstract: A plurality of serial data streams are transmitted on a corresponding plurality of lines at a common frequency in equal groups of symbols. A framing signal composed of groups of symbols corresponding in number to groups of data symbols is transmitted on an additional control line. Each group of symbols in the framing signal includes a majority of symbols capable of representing a first plurality of code words and a second plurality, substantially less than the first plurality, of valid code words, and a minority of symbols which constitute parity check symbols. Each of the valid code words consists of a first sub-group of similar symbols and a second plurality of similar symbols. For some of the valid code words the symbols in the first sub-group are similar to the symbols in the second sub-group. For other valid code words the symbols in the first sub-group are different from the symbols in the second sub-group.

Abstract: An encoder/decoder (ENDEC) avoids undesired sequences in encoded data blocks, such as quasi-catastrophic sequences, by essentially skipping over inputs that create the undesired sequences. Upon recognizing that a particular incoming data block has a value corresponding to an undesired sequence, the ENDEC does not use the problematic value for the incoming data block, but rather adds an offset to the value for the incoming data block, and uses the offset value for producing an encoded output sequence for the data block.

Abstract: A method of generating a run length limited (RLL) code having improved direct current (DC) suppression capability and modulation and demodulation methods of the generated RLL code. According to the method of generating the RLL codes, code words that satisfy a (d, k) run length constraint are generated.

Abstract: A system and method for compressing state transition data on a computer system is disclosed. The method and system include separating the state transition data into a plurality of segments and separating each of the plurality of segments into a plurality of subsegments. The method and system further include providing a plurality of code words. Each of the plurality of code words corresponds to a unique subsegment of the plurality of unique subsegments. The method and system also include providing a representation of each segment. The representation of each segment includes a portion of the plurality of code words. The portion of the plurality of code words replaces the plurality of subsegments in each of the plurality of segments. Thus, the present invention allows compressed state transition data to be used without full uncompression, allowing a system to be explicitly checked without substantial loss of information and without consuming memory.

Abstract: Data words are converted to codewords in accordance with a run-length limited (RLL) or maximum transition run (MTR) code in which the codewords are subject to one or more constraints on the number of consecutive like symbols. The data words and codewords are each partitioned into a number of disjoint subsets. Associated with each of the disjoint subsets of data words is a distinct mapping. A given data word is converted to a codeword by applying to the given data word the mapping associated with the subset containing that data word. The mappings are configured to utilize symmetry whenever possible. For example, if Y=&psgr;(X) represents the mapping of a given data word X onto a corresponding codeword Y. then it is preferred that X′ and Y′ representing the words X and Y in reversed order, satisfy the relation Y′=&psgr;(X′).

Abstract: A method for transforming a data octet (8B) including eight bits into a ten-bit code group (10B) including ten bits, the method including deriving an intermediate result from a table having fewer than 500 entries, and performing a logical operation on the intermediate result to generate the ten-bit code group. Related apparatus and methods are also described.

Abstract: A binary arithmetic coder and decoder provides improved coding accuracy due to improved probability estimation and adaptation. They also provide improved decoding speed through a “fast path” design wherein decoding of a most probable symbol requires few computational steps. Coded data represents data that is populated by more probable symbols (“MPS”) and less probable symbols (“LPS”). In an embodiment, a decoder receives a segment of the coded data as a binary fraction C. It defines a coding interval of possible values of C, the interval extending from a variable lower bound A to a constant upper bound 1. For each position in the decoded symbol string, the decoder computes a test value Z that subdivides the coding interval into sub-intervals according to the relative probabilities that an MPS or an LPS occurs in the position. A first sub-interval extends from the lower bound A to the test value Z; the second sub-interval extending from the test value Z to 1.

Abstract: A bitstream decoding apparatus for decoding a video signal compressed according to the Moving Picture Experts Group (MPEG) standard within a single clock cycle to convert the compressed video signal into the form of symbols such as video parameters and discrete cosine transform (DCT) coefficients. The bitstream decoding apparatus for performing the decoding operation within a single clock cycle includes a shifter, a variable length decoder, a fixed length decoder, a zero-run & AC decoder, a first multiplexer, a second multiplexer, and a first comparator. In the bitstream decoding apparatus, the compressed video data can be decoded within a single clock cycle to perform transmission of a high-resolution picture signal such as that used in a digital television in an efficient way.

Abstract: A method and system for handling literals in a Lempel-Ziv data compression system. The literals are arranged in a storage array in an MRU/LRU format in a defined sequential MRU/LRU order, with shorter MRU/LRU reference codes assigned to the MRU literals and longer MRU/LRU reference codes to the LRU literals. Upon receiving an input literal, a selector selects the literal and a reference encoder provides the assigned MRU/LRU reference code for the literal as the output. The literals are then rearranged. An incrementor responds to the literal selection, by incrementing downward one location in the sequential order, all the literals in the storage array from the top of the MRU order to the one of the literals in the order immediately preceding the selected literal, and the selector moves the selected literal to the top of the MRU order.

Abstract: Rather than comparing an old file with a new file to generate a set of patching instructions, and then compressing the patching instructions to generate a compact patch file for transmission to a user, a patch file is generated in a single operation. A compressor is pre-initialized in accordance with the old version of the file (e.g. in an LZ77 compressor, the history window is pre-loaded with the file). The pre-initialized compressor then compresses the old file, producing a patch file from which the new file can be generated. At the user's computer, a parallel process is performed, with the user's copy of the old file being used to pre-initialize a decompressor to which the patch file is then input. The output of the decompressor is the new file. The patch files generated and used in these processes are of significantly reduced size when compared to the prior art.

Abstract: A process for initializing a serial link between two integrated circuits comprises an initialized input-output port associated with each integrated circuit connected between a parallel bus and a serial link. Each port uses two clocks with different frequencies, a first higher-frequency clock for the serial link, called a transmitting clock, and a second lower-frequency clock for the signals arriving from the parallel bus, called a system clock. The process comprises the following steps: reinitializing the port with isolation of the receiving clock logic; reinitializing the transmitting clock logic; resetting the serial link between two ports; and initializing a two-way serial link by a looped process, either automatic or dependent on a microprocessor.

Abstract: A CODEC has a DSP which can consecutively execute a plurality of algorithms without restriction of a memory capacity. The DSP performs an encoding/decoding operation on a digital signal. A program memory stores a program divided into a plurality of block programs, the program being stored on an individual block program basis. A data memory stores a set of data used for executing each block program stored in the program memory, the set of data being divided into a plurality of data blocks and stored on an individual data block basis. A program executing unit executes each block program stored in the program memory by using a corresponding data block stored in the data memory. A program changing unit obtains a new block program from an external device each time execution of one of the block programs by the program executing unit is completed so as to store the obtained new block program in the program memory.

Abstract: An engineering unit converter system for converting an analog measurement into an engineering value. An analog measurement of a physical quantity is transformed into a digital value. The digital value is then split into a high order digit and a lower order digit. The high order digit is used as an address to a memory device for fetching a line segment coefficient and a line segment offset coefficient. The lower order digit is multiplied with the line segment coefficient in a multiplier resulting in a product. The product is added to the line segment coefficient offset resulting in a sum whose value is an engineering unit. One embodiment is directed to converting temperature measurements into engineering units via thermocouples. This embodiment includes: thermocouple devices, resistance thermal devices or positive temperature coefficient thermistors, adders, multipliers, and memory devices (readable and writable memory devices).

Abstract: Two different (d,k)-RLL codes can be used in systems such as erasable and writable dense optical disks. This is because it is typically possible to make readers capable of reading information written at a higher resolution (by a short wavelength authoring system) than the resolution that can be written by a consumer writer (using a laser of the same or longer wavelength as the reader). For one embodiment, two different decoders are used to decode the data. Alternately, we present an encoding scheme which operates with a single decoder. In one case, q1=q2 (and as a result p1<p2), so that the decoders D1 and D2 actually process blocks of the same length. The decoding of the sequences encoded by E1 is done using the decoder D2 plus an additional function &psgr; which maps the restored p2-blocks into p1-blocks in a to very simple manner. This way, we do not need a separate circuit for the (d1,k1)-RLL decoder, because D1 is obtained as a cascading of D2 and another very simple circuit &psgr;.

Abstract: A technique to demodulate digital data streamed from a recording medium by periodically hashing m-bits of data to create an index to a look up table and a code word identifier. The look up table includes the modulation pattern, which has a plurality of m-bit data entries, mapped into a plurality of n-bit data clusters, with each of the plurality of data clusters including a sub-portion of one of the plurality of m-bit data entries and a cluster identifier, with each of the plurality of data clusters differing from the remaining data clusters, with n being less than mn. The index and code word identifier is determined from a sub-portion of the m-bits of data, which are then both compared with a sub-group of the plurality of data clusters. Upon finding a match between one of the data clusters of the subgroup and both the index and the code word identifier, a signal is generated.

Abstract: A microprocessor 11 receives an ambiguous input from a key 2-9 and disambiguates the ambiguous input using a dictionary. The dictionary is stored in an efficient manner by being partitioned according to the first three letters of a word. A sequence of three letters in the dictionary is stored as eight bits of data, the first three letters of a word being stored using three pairs of bits, such that each pair of bits represents one of no more than four alternative letters.