Abstract: A method is provided to leverage blockchain based data tokenization to randomly tokenize encrypted and nonencrypted data elements within a data set represented in a 3-dimensional form, wherein the tokens are distributed and reordered into the correct position using a key pair match and Verifiable Self Sovereign Identification (VSSI). The key pair and VSSI credentials must be presented in order to distribute the tokenized data elements into the correct 3-dimensional position within the data set upon verification of the match of the key pair and the prescribed VSSI.

Abstract: The present disclosure relates to the technical field of displays, and provides a pixel compensation circuit, which includes a detection circuit, a first compensation circuit, and a second compensation circuit. The detection circuit is configured to detect a threshold voltage of a driving transistor; the first compensation circuit being configured to write a first reference voltage to a source electrode of the driving transistor; the second compensation circuit being configured to write a second compensation voltage to a control terminal of the driving transistor at the same time of writing the first reference voltage to the source electrode of the driving transistor. The second compensation voltage is equal to a difference between the threshold of the driving transistor and a first compensation voltage.

Abstract: The invention relates to a device (1) for encoding information between a plurality of normally closed switches (P1 . . . Pn) arranged on an operating lever (2) and a control device (9), said switches being connected in series between a voltage line (3) and a measuring line (5), each switch (Pi) being associated with a single resistor (Ri) connected between the terminal of the switch closest to a voltage source (Vcc) and the measuring line. The encoding device thus allows a hierarchy of the switches to be obtained.

Abstract: The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

Abstract: A digital-to-analog converter has both a plurality of DAC stages and a plurality of dummy stages. Each DAC stage causes a glitch or disturbance to a pair of reference voltages when the DAC stage changes its switching state. Each dummy stage also causes a similar glitch or disturbance to the pair of reference voltages when the dummy stage changes its switching state. The dummy stages are controlled to change their switching state responsive to how many DAC stages change their switching state such that a total glitch induced onto the reference voltages remains substantially constant across a succession of digital words converted by the digital-to-analog converter into an analog output signal.

Abstract: A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.

Abstract: An analog-to-digital conversion circuit and method are provided. At a sampling stage, the first capacitor array connects lower electrode plates of N capacitors to a first input voltage, connect lower electrode plates of the other capacitors to a common-mode voltage, and connect upper electrode plates of all the capacitors to the common-mode voltage to sample the first input voltage; in an ith conversion at a conversion stage, the logic circuit controls, the lower electrode plate of an ith capacitor to connect to a reference voltage or a ground voltage, a first comparison voltage output by the first capacitor array approximates a second comparison voltage; and the comparator stores a comparison result between the first and the second comparison voltage to an i+1th flag bit in the logic circuit, and analog-to-digital conversion is completed when i+1 is equal to the total number of capacitors in the first capacitor array.

Abstract: According to an embodiment, a digital-to-analog converter may be provided. The digital-to-analog converter may include a resistive ladder network including a plurality of paths corresponding to bit currents, respectively. The digital-to-analog converter may include a switching circuit configured to include a plurality of weighted elements respectively coupled to the paths. The digital-to-analog converter may include a reference voltage setting circuit coupled to the weighted elements and the paths, and configured to minimize a variation of threshold voltages of the weighted elements.

Abstract: A host integrated circuit is provided with an interrupt aggregator having a signal terminal for coupling to the signal end of an R-2R resistor ladder that has a plurality of rungs corresponding to a plurality of peripheral devices. The interrupt aggregator is configured to process a voltage signal received at the signal terminal to identify any of the peripheral device that intend to trigger an interrupt to a processor.

Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.

Abstract: A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.

Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.

Abstract: A precision bipolar digital-to-analog converter (DAC) that provides a bipolar current output having a substantially fixed zero center point is provided. The DAC includes digital-to-analog converter circuitry configured to provide, responsive to a reference signal indicative of the digital data, a first analog current signal having a first potential and a second analog current signal having a second potential, subtractor circuitry configured to provide a bipolar current signal by subtracting the second analog current signal from the first analog current signal, the bipolar current signal having a zero center point, and first control circuitry electrically coupled to the subtractor circuitry and to the digital-to-analog converter circuitry, and configured to modify the second potential so that the second potential equals the first potential.

Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.

Abstract: In some embodiments, a digital-to-analog converter (DAC) system includes an output segment, a main branch, first and second edge segments, and a sub-segment. The output segment includes secondary switches that selectively connect conductive paths to an output. The main branch includes unit resistance elements, each including a resistor and a switch. The first and second edge segments each include a respective group of secondary switches that selectively connect a respective conductive path to a unit resistance element. The sub-segment includes terminal resistors connected to at least one conductive path and includes main switches that selectively connect respective terminal resistors to the unit resistance element. The main switches and the unit resistance element switches use a single switch design. The DAC system may have an improved differential non-linearity (DNL), as compared to a DAC system that does not include the unit resistance element switches or the first and second edge segments.

Abstract: An integrated circuit temperature sensor includes a sensor to determine whether the integrated circuit is currently exposed to a relatively low or high temperature. A measured voltage across the base-emitter of a bipolar transistor is selected if the sensor indicates exposure to the relatively low temperature or, a measured delta voltage across the base-emitter of the bipolar transistor is selected if the sensor indicates exposure to the relatively high temperature. The voltage across the base-emitter is compared against a first reference for determining exposure to a too cold condition or the selected measured delta voltage across the base-emitter is compared against a second reference for determining exposure to a too hot condition. In a test mode, the measured delta voltage across the base-emitter and/or the measured voltage across the base-emitter are scaled.

Abstract: A fast, high resolution digital-to-analog converter (DAC) is described herein. The DAC comprises a pulse generator, decay circuit, controller, and sample circuit. The pulse generator serially outputs pulses representing digits of a digital word least significant digit first. Each pulse generates a response in the decay circuit that decays over time according to a known decay response. One exemplary decay circuit comprises an RC circuit having an exponential decay response. The controller controls the timing of the pulses output by the pulse generator such that the period of each pulse relates to a predetermined decay amount. The sample circuit samples an output of the decay circuit at a sample time after the decay circuit receives the pulse for the most significant digit. The sampled output represents the analog value corresponding to the input digital word. The digital word may have any length, radix, or format.

Abstract: A sensing circuit determines whether an integrated circuit is currently exposed to one of a relatively low or a relatively high temperature. A selection circuit selects a measured voltage across the base-emitter of a bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively low temperature or, alternatively, selects a measured delta voltage across the base-emitter of the bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively high temperature. A comparator compares the selected measured voltage against a first reference voltage indicative of a too cold temperature condition or compares the selected measured delta voltage against a second reference voltage indicative of a too hot temperature condition. As a result of the comparison, detection may be made as to whether the integrated circuit is currently exposed to a too cold or too hot temperature.

Abstract: An improved apparatus and method for interfacing a time variant waveform between two hardware environments. In one aspect, the invention comprises a circuit for accurately simulating the output of one or more types of sensing device (e.g., passive bridge pressure transducer) for use with a plurality of different monitoring and/or analysis devices, thereby obviating the need for specialized interface circuitry adapted to each different monitor/analyzer. In one exemplary embodiment, the sensing device comprises a non-invasive blood pressure monitor (NIBPM), which universally interfaces with prior art patient monitors via the interface circuit of the invention. In a second aspect of the invention, an improved NIBPM device incorporating the interface circuit is disclosed. An improved disconnect circuit adapted to sense the status of the electrical connection between the sensing device and monitor is also described.

Abstract: Methods and structures are provided to enhance the linearity of amplifiers such as those which include a complementary common-collector amplifier stage. The methods and structures configure this stage so that each transistor of the stage drives an output port through a linearizing resistance. The methods and structures then control a bias current through the stage to substantially be the thermal voltage VT divided by twice the linearizing resistance.

Abstract: A radio frequency digital-to-analog converter with a programmable current output. In exemplary aspects of the invention, improved apparatus and methods for providing (i) current mirror matching, (ii) enhanced current pulse rising edge performance, (ii) reduced base voltage swing, and (iv) compensated high voltage swing, are provided. The foregoing apparatus and methods can be applied to any RF signal application (wireless or otherwise), including for example wireless cellular handsets.

Abstract: The accuracy of output power in a digital-to-analog converter (DAC) is critical in certain applications. When bi-CMOS technology is used to implement a DAC, a number of factors affect the gain accuracy of the DAC. The present invention provides a circuit architecture to reduce the variation in these factors to ensure the accuracy of the output power of a DAC. The architecture comprises a bandgap portion, replica circuit and a DAC. The bandgap portion of the architecture provides a constant voltage, while the replica circuit provide a correct current to drive the DAC.

Abstract: A digital-analog converter for mobile radiotelephone base stations includes a D flip-flop and a modulator. The D flip-flop is clocked by a clock signal and a digital input signal is fed to an input of the D flip-flop to produce an output signal. The modulator multiplies the output signal produced from the D flip-flop with the clock signal and outputs an analog output signal indicative thereof.

Abstract: The system includes a unipolar A/D converter, which samples analog signal inputs thereto, the A/D converter being used in a protective relay for electric power systems. The unipolar A/D converter is responsive to input voltage values and current values from the power line to produce corresponding digital signals. The A/D converter has a ground pin voltage reference at least as negative as the most negative point of the input signal to be processed.

Abstract: Differential heating is avoided by a digital to analog converter for generating analog cyclical waveforms having a period. The cyclical waveforms are generated by conversion of a sequence of step wise linearly incrementing digital phase words presented during the period for conversion. The digital to analog converter has a clock for operating conversion timing within the digital to analog converter. The clock generates a clock pulse for conversion of each of the digital phase words by said digital to analog converter while generating the cyclical waveform. A lookup read only memory for converting each of the incrementing digital phase words within the period into a plurality of ON commands to be used by a plurality of current sources. The plurality of ON commands are timed to generate the cyclical waveforms and have nearly equal time duration approximating a 50 percent duty cycle. The cyclical waveform has one or more non-linear portions reflected in the content of the read only memory.

Abstract: The system includes a unipolar A/D converter, which samples analog signal inputs thereto, the A/D converter being used in a protective relay for electric power systems. The unipolar A/D converter is responsive to input voltage values and current values from the power line to produce corresponding digital signals. The A/D converter has a ground pin voltage reference at least as negative as the most negative point of the input signal to be processed.

Abstract: An analogue to digital converter generating at least two threshold levels and a comparator for comparing each of the levels with the input signal and generating a primary digital output signal to provide an indication that the input signal has crossed one of the threshold levels. The converter comprises a timer for determining the elapsed period of time between the input signal crossing a first level and the input signal crossing a second level and for generating a secondary output signal representing the elapsed time, whereby the secondary digital output signal and the corresponding primary output signal are used to provide a digital representation of the analogue input signal. The converter may also comprise a receiver of the primary digital output signal from the comparator and for providing an UP/DOWN digital output signal to indicate in which direction the input signal crossed the threshold level.

Abstract: An OTA circuit is disposed between a differential pair composed of NMOS transistors and an NMOS follower transistor that composes an output buffer circuit. The OTA circuit generates a compensation current that is equal to a current that flows in a capacitance formed between the gate and the drain of each of the differential pair transistors and that flows in the reverse direction thereof. The compensation current cancels the current that flows in the capacitance formed between the gate and the drain of each of the differential pair transistors. Thus, a differential amplifier that has a high accuracy and, high gain, and a wide frequency band and that operates at a low power voltage can be accomplished. Using a differential amplifier having a high gain and a wide frequency band, a comparator that operates at high speed and an A/D converter using such a comparator can be accomplished.

Abstract: An analog to digital converter has a differential input arrangement with a static reference ladder and comparators for comparing the differential input signal with respective reference voltages from the ladder. For sensing the positive and the negative values of the input signal the same taps of the reference ladder are used.

Abstract: Integrated-circuit structures and methods are provided for generating an error signal that represents temperature and process-induced signal changes in transistor parameters. In particular, a reference transistor and a sense transistor are biased to each generate a substantially temperature-insensitive minority-carrier current. The reference transistor is provided with a substantially constant voltage across its current terminals to convert its minority-carrier current into a substantially temperature-insensitive reference current IR. In contrast, the sense transistor is provided with a temperature-varying voltage across its current terminals to convert its minority-carrier current into a temperature-varying sense current IS. The reference current and the sense current are then differenced to realize an error signal IE that contains information that describes temperature and process-induced signal errors in integrated-circuit transistor stages.

Abstract: The invention relates to an A/D conversion device intended to supply at the output a digital signal Vout[0:7] resulting from the conversion of an analog input voltage Vin and receiving a control signal CRS used for defining the transfer characteristic of the device by way of comparison with the output signal Vout[0:7]. According to the invention, such a device comprises a reference module (AO, CMP2) which allows adjustment of the digital value of the output signal Vout[0:7] at a predetermined value when the analog input voltage Vin is zero, and means (Mx, Vact) for substituting for said voltage Vin a reference voltage Vref having a predetermined value when the device is in its control mode.

Abstract: A two's complement digital to analog converter (300) is for converting a two's complement binary value to an analog output current, and includes a control circuit (310) which generates controlled value bits, a digital to analog current converter (DACC) (320), and an augmenter (330). The DACC (320) generates a DACC analog current which is a portion of the analog output current and which has an absolute value which is related to the binary value of the controlled value bits. The augmenter (330), which is coupled to a most significant bit of the two's complement binary value, generates a portion of the analog output current by modifying the absolute value of the DACC analog current by a least significant bit current increment when the most significant bit indicates a negative value of the two's complement binary value.

Abstract: A symbol detector (110) includes an analog-to-digital converter (115) for converting signal voltages to digital values and peak and valley counters (310, 315) for tracking the digital values to determine peak and valley values associated with high and low voltages of the signal. The symbol detector (110) further includes calculation circuitry (356) for calculating upper, lower, and center thresholds based on the peak and valley values and a decoder (125) for generating data symbols in accordance with the upper, lower, and center thresholds.

Abstract: An integrated circuit is disclosed including an analog-to-digital (A/D) converter having an offset source for providing an offset signal; and a first reference array including a plurality of cells for generating a first output signal from an input signal and the offset signal, for generating a second output signal from the offset signal, and for generating an A/D output signal from the first and second output signals.

Abstract: A balanced delta-modulation analog-to-digital conversion circuit is disclosed. A first principal integrator produces a first output signal which rises when a first control signal is generated and falls when a second control signal is generated. A second principal integrator produces a second output signal which fails when the first control signal is generated and rises when the second control signal is generated. The first and second control signals are then generated based upon the differences between the first and second output signals.

Abstract: An apparatus is provided for generating a multiple-level amplitude modulated data signal. The circuit provides accurate data signal level control while minimizing transient errors. A controlling level, relative to an analog reference level is provided. Multiple bit reference levels are generated from the controlling level and analog reference level. A method is provided for selecting one of the reference levels.

Abstract: A D/A converter divides an input digital data into at least two overlapping digital ranges. The data in the two ranges are converted separately from digital to analog by a low-range and a high-range DAC. The resulting analog signals are then added with a weighting that maintains the proper loudness relationships in the final combined analog output. In a low range of amplitudes, only the low-range DAC performs D/A conversion. Above a predetermined amplitude threshold, some of the high significant bits to the low-range DAC are frozen, while a remaining low significant bits of the low-range DAC are permitted to vary with the input digital data. Above the predetermined amplitude threshold, a digital value is subtracted from the data fed to the high-range DAC. The subtracted value is equal to the frozen value in the low-range DAC. In some embodiments, one or more supplementary bits are developed to smooth the transition between ranges.

Abstract: A circuit and method for converting a digital number to an analog output signal, wherein the most significant bit or "sign" bit of the digital number is used for switching the accumulated currents of the other data bits to a chain of operational amplifiers employing feedback resistors for conversion into an output voltage of magnitude and sign corresponding to the input digital number. A decoding circuit and method enables the circuit to present an output voltage corresponding to the two's--complement of the input digital number.

Abstract: An integrated circuit incorporating an analog-to-digital (A/D) conversion subsystem having a current mode in which only negative analog currents are converted and a voltage mode in which only positive analog voltages are converted is adapted to produce bipolar digital current and voltage signals. An on-board microprocessor operates the A/D conversion subsystem to perform a conversion in the current mode. If the converted digital value is non-zero, this value is used as the negative digital value of analog input signal. If the result of the conversion in the current mode is zero, a second conversion is made in the voltage mode and used as digital value with a positive polarity. An input circuit having an output impedance substantially equal to the "full scale equivalent" input impedance of the IC defined as the full scale voltage of the IC divided by the full scale current, eliminates the need for special scale factors to correlate the positive and negative conversion values.

Abstract: In an analog-to-digital converter, one-bit A/D conversion stages are connected in series to receive an analog signal. Each conversion stage includes a sample-and-hold circuit for sampling an analog signal from a preceding stage, a comparator for comparing it with a specified voltage level to produce a logic signal at one of two discrete levels depending on whether the signal received from the preceding stage is higher or lower than the specified level. The signal received from the preceding stage is summed with a prescribed reference voltage of one of opposite polarities depending on the level of the logic signal to produce an analog output signal. The successive conversion stages are driven so that the analog signal from each stage is transferred to the next, and the logic signals generated by the individual conversion stages are delayed so that they appear simultaneously at digital output terminals.

Abstract: A high resolution analog to digital converter is provided which operates at a relatively high speed. The converter will operate in either a bipolar or unipolar mode and the bipolar mode includes a signal/sign transposer. A sample/holding circuit temporarily holds the analog input at its sample level. The device also includes analog to digital converter, a reference selector, a reference source, a digital/analog converter, a subtracter for conversion voltages, a plurality of latches, a buffer and timing/control circuitry.

Abstract: The converter input i is connected through a comparator to the polarity bit output as well as to the input of a full-wave precision rectifier in the first quantization stage, which like further stages comprises an operational amplifier, a comparator and an exclusive OR gate, the output of which is connected to the output for the first bit. To the inverting input of the amplifier with the gain equal to 2 through the potentiometer a voltage -U.sub.o /2 is fed, (-U.sub.o, +U.sub.o) being the interval of the input voltage. The input of the rectifier is connector to the input i and the input of the rectifier in further stages is connected to the output of the operational amplifier in the previous stage. The second input of the exclusive OR gate is connected to the bit output of the previous stage.

Abstract: An integrated A/D converter includes an integrator 8integrating reference signals in synchronism with an integration start signal, and counters for counting integrating clock pulses until the integrated value of the integrator reaches a value corresponding to an input signal, thereby to convert the input signal into a digital or analog signal based on the counts of the counters. An AND gate supplies the integrating clock pulses to the counters only during a predetermined period in synchronism with the integration start signal, so that the integrating clock pulses are supplied to the counters only during an integrating period for the reference signals.

Abstract: An automatic reference voltage controller of an integral A/D converter comprises a reference voltage switching circuit, an input voltage switching circuit, a Miller integrator, a comparing circuit, a logic circuit, and an automatic reference voltage control means for reducing the output error of the integral A/D converter. According to the present invention, the error of the digital output signal due to the limit error of the integral A/D converter can be reduce by automatic control of the reference voltage.

Abstract: A multiplying digital-to-analog converter for multiplying a bipolar input current by a digital word A having N bits a.sub.i including a current adder for adding a constant current to the bipolar input current to produce a unipolar current, a first current mirror responsive to the unipolar current for providing N binary weighted versions of the unipolar current, a second current mirror for providing binary weighted versions of the constant current, N current selection circuits respectively controlled the N bits a.sub.

Abstract: A termination circuit for an R-2R ladder network for producing weighted currents, the 2R terminating resistor of the ladder being connected to an excitation source voltage which is 2(kT/q)ln 2 closer to the supply voltage than the emitter of the current source in the last (i.e., least significant) leg of the ladder. The excitation source is fabricated with just one type of bipolar transistor and does not require anamplifier or frequency compensation capacitor(s). The excitation source is a simple circuit requiring only five transistors, at least one of which has an emitter area which is a multiple of the emitter areas of the current source transistors. The base-emitter voltages of the transistors in the excitation source are connected in a voltage loop that goes from a voltage V.sub.LSB at the emitter of the current source transistor connected to the least significant ladder network shunt resistor to a voltage, Vt, which would be equal to V.sub.

Abstract: A sliding scale averaging technique is employed for an analog-to-digital converter. An analog signal is summed with a varying number prior to conversion. This causes repeated input voltage signals of the same value to be converted in different bins of the ADC converter thereby minimizing errors due to unequal bin widths. The present invention includes a comparator technique for ensuring that the summed signal does not exceed the full dynamic range of the ADC.

Abstract: A digital-to-analog converter which includes a digital-to-analog conversion circuit of the current output type, a current-to-voltage conversion circuit receptive of an analog current produced form the digital-to-analog conversion circuit in correspondence to an input digital signal value, for converting the analog current to a voltage and producing it at the output thereof in an output stage of the converter, a first drive circuit for driving the digital-to-analog conversion circuit with constant current, and a second drive circuit which is controlled by the first drive circuit to drive the current-to-voltage conversion circuit with constant current, thereby it being made possible to arrange a plurality of digital-to-analog converters in a simple structure.

Abstract: An operational amplifier is provided and includes at least two input terminals of one polarity and another input terminal of the opposite polarity. The amplifier includes an amplifying portion which comprises a differential section for receiving input signals applied to the input terminals. The differential section includes at least two differential amplifiers which form difference signals from the input signals. A summing section receives the difference signals and forms a sum result therefrom. A multiplying section provides an amplification gain to the sum result to form an output signal of desired gain. The amplifier is also provided with a feedback for applying an input signal to one of the input terminals, the output signal. The amplifier can be configured to provide amplification gains of 2, 1/2, -1 and 1.

Abstract: A code converter includes an extraction device for extracting a reference level from a binary-coded input signal, which is offset at a predetermined voltage level and which varies arbitrarily with the same polarity as the voltage level. A twos-complement conversion device, connected to the extraction device, converts the reference level into a twos-complement value. A creation device, connected to the extraction device and the twos-complement conversion device adds an output signal of the twos-complement conversion device and the binary-coded input signal, thereby producing a bipolar binary-coded output signal to which a polarity bit is added.