Abstract: A voltage supply and a method for calibrating the voltage supply are provided. The voltage supply is for providing a reference voltage to supply a voltage to at least one electrode. The voltage supply comprises: an ultra-stable DC voltage source, an accurate DC voltage source, a tuning unit, a comparator, and a control unit. An ultra-stable voltage is applied to the tuning unit, which is provided based on a supplied voltage of the ultra-stable DC voltage source. The tuning unit provides an output voltage. A voltage based on the output voltage of the tuning unit is compared by the comparator with an accurate voltage. The accurate voltage is provided based on a supplied voltage of the accurate DC voltage source.

Abstract: Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

Abstract: A device for processing digital signals is provided. The device comprises a digital signal source and a converter circuit having a current supply. The digital signal source outputs a codeword. The converter circuit receives the codeword from the digital signal source, receives a current at the current supply, and generates an output signal based on the codeword. The current is generated in accordance with the codeword.

Abstract: Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the nth Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the nth Nyquist zone to the mth Nyquist zone of the spectrum, where n>m?1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

Abstract: Methods of performing mixed-signal/analog multiply-accumulate (MAC) operations used for matrix multiplication in fully connected artificial neural networks in integrated circuits (IC) are described in this disclosure having traits such as: (1) inherently fast and efficient for approximate computing due to current-mode signal processing where summation is performed by simply coupling wires, (2) free from noisy and power hungry clocks with asynchronous fully-connected operations, (3) saving on silicon area and power consumption for requiring neither any data-converters nor any memory for intermediate activation signals, (4) reduced dynamic power consumption due to Compute-In-Memory operations, (5) avoiding over-flow conditions along key signals paths and lowering power consumption by training MACs in neural networks in such a manner that the population and or combinations of multi-quadrant activation signals and multi-quadrant weight signals follow a programmable statistical distribution profile, (6) programmab

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block.

Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

Abstract: Technologies directed to a receiver circuit with selective time-interleaved analog-to-digital converters (ADCs) are described. The receiver circuit includes a first ADC, a second ADC, and a digital processing circuit coupled to the first ADC and second ADC that operates in a first mode or a second mode. In the first mode the first ADC receives a first signal and generates first samples at a first sampling frequency. The digital processing circuit processes the first samples. In the second mode, the first ADC and the second ADC both receive a second signal and collectively generate second samples at a second sampling frequency that is greater than the first sampling frequency. The digital processing circuit processes the second samples.

Abstract: Embodiments are directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements.

Abstract: Systems or methods for losslessly compressing data received from sensors, such as photon counters, are disclosed. An integer representation of a sensor reading is received from a sensor. The integer representation is combined with additional integer representations from each of a plurality of additional sensors into a single integer value. The single integer value is then stored as an element of an integer array that represents a predefined sample interval.

Abstract: A signal analyzer for analyzing a signal includes a frontend with at least two interleaved digitizers configured to digitize an input signal, thereby generating a digitized input signal. The signal analyzer also includes a first interleave alignment filter established by a hardware interleave alignment filter that is configured to hardware-compensate non-ideal effects of the frontend in the digitized input signal in real-time, thereby generating a hardware-compensated, digitized input signal. Further, the signal analyzer includes an acquisition memory configured to store the hardware-compensated, digitized input signal, thereby acquiring an acquired signal. Moreover, the signal analyzer includes a second interleave alignment filter configured to fine-compensate further non-ideal effects of the frontend in a post-processing of the acquired signal.

Abstract: A method of tuning a production module using a reference module with virtual gain correction is provided. The method includes selecting a counterpart reference module created for a select application. The production module is commutatively coupled to the selected counterpart reference module to generate a production module pair. A production module gain curve for the production module pair is measured for each frequency band to be used by the production module. The production module is tuned based at least in part on offset gain values at select number of frequency observation points for each frequency band associated with the counterpart reference module and gain values at the select number of frequency observation points of the measured production module gain curve for each frequency band.

Abstract: A method and apparatus for processing or generating a high-frequency signal using parallel and undersampled baseband signal processing in the frequency domain.

Abstract: A digital-to-analog converter comprises a plurality of first digital-to-analog converter cells configured to generate a first analog signal based on first digital data, wherein the first digital-to-analog converter cells of the plurality of first digital-to-analog converter cells are coupled to a first output node for coupling to a first load. Further, the digital-to-analog converter comprises a plurality of second digital-to-analog converter cells configured to generate one or more second analog signals based on second digital data, wherein the second digital-to-analog converter cells of the plurality of second digital-to-analog converter cells are coupled to one or more second output nodes, and wherein the plurality of first digital-to-analog converter cells and the plurality of second digital-to-analog converter cells are coupled to a power supply node for coupling to a mutual power supply.

Abstract: Multipliers, Multiply-Accumulate (MAC), and Square-Accumulate (SAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers, MACs, and SACs. Generally, digital multipliers, MACs, and SACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers, MACs, and SACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.

Abstract: Various embodiments provide a filter for propagation delay compensation and interpolation in encoder digital signal processing. The filter can include a first low pass filter configured to reduce noise of a digital input comprising a measured angular position; a first differentiator configured to receive a filtered digital input and to calculate a speed from a difference in time of the measured angular position and a previous angular position; a second low pass filter configured to reduce noise from the speed; a second differentiator configured to receive a filtered speed and to calculate acceleration using a difference in time of the filtered speed and a previous speed; a third low pass filter configured to reduce noise of the acceleration; and a delay compensator configured to receive the filtered digit input, the filtered speed, and a filtered acceleration, and to calculate a propagation delay compensated digital output.

Abstract: System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.

Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.

Abstract: A digital transducer provides a digital output indicative of dynamic characteristics of machines and processes. The transducer sensors may be single-axis or multiple-axis accelerometers and other measurement sensors. The transducer may be hands-free and wireless in machinery monitoring applications. An integral magnetic mount assists with hands-free data collection. Digital data accumulated in transducer memory may be selectively decimated before or after transfer from the transducer to a remote analyzer. Wireless communications are used to upload measurement setups to the transducer and download data from the transducer to a handheld analyzer or remote computer. Analysis and interpretation of dynamic digital data streams are performed after data is downloaded.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A method for operating a receiving device in a wireless communication system comprises determining inter-symbol interference between symbols in a received signal, determining a location of a receive detection window according to the inter-symbol interference, and demodulating the received signal based on the location of the receive detection window. A receiving device includes at least one transceiver, and at least one processor configured to determine inter-symbol interference between symbols in a received signal, determine a location of a receive detection window according to the inter-symbol interference, and demodulate the received signal based on the location of the receive detection window.

Abstract: A communication apparatus accepts remote control from an external apparatus via wireless communication, and includes a communication unit configured to communicate with the external apparatus, and a control unit configured to execute, in response to an operation request that the communication unit has received from the external apparatus, the request being performed through the remote control, a task corresponding to the operation. The control unit sets a time interval relating to a timing at which communication with the external apparatus is performed, and controls the communication unit to perform communication with the external apparatus in compliance with the set time interval.

Abstract: An analog-to-digital converter (“ADC”) includes an analog voltage sampler having an energy storage device, such as a capacitive element, configured to charge based on an analog input voltage. A timer determines an elapsed time for the energy storage device to discharge to a predetermined value. The ADC outputs a digital value representing the analog input voltage based on the determined elapsed time.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A data transfer method comprises encoding data and control signals in a sequence of symbols to be transmitted on a plurality of connectors, and transmitting the sequence of symbols on the plurality of connectors. Each symbol may be transmitted using a combination of a phase state of a first pair of connectors, a polarity of a second pair of connectors, and a selection of at least one undriven connector. Transmission of each symbol in the sequence of symbols may cause a change of state for at least one of the plurality of connectors.

Abstract: Systems and methods for processing a multitude of variable and varying signals in real time with low latency using fixed hardware with fixed processing resources, such as those within an application-specific integrated circuit (ASIC) or a field-programmable gated array (FPGA). The signal processing systems and methods allow the resource allocation to continuously adjust their processing as a result of changing signal conditions. In accordance with various embodiments, fixed processing resources in ASIC or FPGA form are dynamically allocated through an intelligent interleaving methodology that efficiently maps the signal processing of incoming signals while essentially preserving the same latency as if each signal channel were processed at the full sample rate. This is accomplished by multiplexing under the control of a resource sharing algorithm.

Abstract: A first electronic device is provided. The first electronic device includes a communication circuitry and at least one processor. The at least one processor is configured to control the communication circuitry to connect with a second electronic device, determine data to transmit to the second electronic device, control the communication circuitry to transmit the data to the second electronic device, and when a signal, indicating that an application is executed from the second electronic device, is received after the data is transmitted, stop transmission of the data.

Abstract: A universal input/output circuit for building automation is provided that may avoid issues related to capacitor soakage, thereby giving more accurate measurements of electric resistance. To mitigate capacitor soakage, the voltage between the input/output terminals is held constant. A programmable source drives a current through a resistor that connects to the input/output terminals. The circuit then measures a value of electrical resistance. The measurement yields a voltage signal which is transferred from the input of an analog-to-digital converter to the input of a digital-to-analog converter. A unity gain amplifier applies the output voltage of the digital-to-analog converter D/A to one of terminals. The circuit is configured such that the voltage signal at the output of the amplifier matches or substantially matches the voltage obtained from the resistance measurement.

Abstract: An electro-optical circuit, includes in part, a modulator, a signal splitter, N signal paths each having one or more signal processing components, N photo-diodes and a signal combiner. The modulator modulates an optical signal using an electrical input signal. The splitter splits the modulated optical signal into N optical signals each delivered to a different one of the N paths for processing by the associated signal processing component(s). Each photo-diode converts an optical signal it receives from its associated optical signal processing component(s) to a current signal. The signal combiner combines the N current signals it receives from the N photo-diodes to generate an output current signal. The signal processing component(s) may be a variable optical delay component, a variable optical gain/attenuation component, or both thus enabling the output current signal to represent a filtered version of the electrical input signal.

Abstract: Provided is an AD converter including a first AD converting unit in which pixel columns of a pixel array are divided into at least two groups, and that compares a first ramp signal and a first pixel signal output from a first group of the pixel columns and performs AD conversion on the first pixel signal; and a second AD converting unit that compares a second ramp signal and a second pixel signal output from a second group of the pixel columns and performs AD conversion on the second pixel signal, in which the first ramp signal is a signal of which a level is decreased with a constant slope over time in a D-phase period for detecting a signal level of a pixel signal, and the second ramp signal is a signal of which a level is increased with a constant slope over time in the D-phase period.

Abstract: A time label combination method, comprising the steps: collecting data acquisition system digital measurement values and establishing a database for the measured values; identifying atomic time label quantities and shape fluctuation statistics; estimating a covariance matrix of each atomic time label; according to the least squares criterion, giving the time label combination. Also provided is a time label combination system, comprising a low-dose pre-acquisition data module, a digital identification module, a quantitative variance calculation module, and a time label combination parameter calculation module. By means of using the described time label combination method and system, system and resolution is effective increased, and the invention is particularly suitable for nuclear instrument time acquisition.

Abstract: Systems and techniques relating to a digital-to-analog converter (DAC) are described. A described DAC cell includes a differential switch pair coupled with a cross-coupled switch pair. Gate terminals of the differential switch pair are arranged to respectively receive an input signal to the cell and an inverted version of the input signal to respectively drive the gate terminals of the differential switch pair. Gate terminals of the cross-coupled switch pair are arranged to respectively receive the input signal and the inverted version of the input signal to respectively drive the gate terminals of the cross-coupled switch pair. The cross-coupled switch pair is configured to reduce or eliminate net differential transient current between switch output terminals of the differential switch pair. A current-to-voltage converter coupled with the switch output terminals of the differential switch pair generates a voltage that forms at least a portion of an output of the digital-to-analog converter.

Abstract: Embodiments herein describe a reference-less CDR circuit that receives electrical signals that may have been transmitted along either an electrical or optical interconnect which are then processed to identify the original data. To do so, the CDR circuit includes a frequency locking loop (FLL) and a phase locking loop (PLL) which generate control signals for a voltage controlled oscillator (VCO). In one embodiment, the FLL generates a coarse adjustment signal which the VCO uses to output a recovered clock that substantially matches the frequency of the received electrical signal. The PLL, on the other hand, generates a fine adjustment signal which the VCO uses to make small adjustments (e.g., half cycle phase shifts) to the recovered clock. The recovered clock outputted by the VCO is then fed back and used as an input in both the FLL and the PLL.

Abstract: Systems and methods are disclosed relating generally to data processing, and more particularly to applying low pass and rotation filtering in relation to data processing. For example, a system may include a phase modification value determination circuit operable to generate a phase offset value based upon an input data set derived from information sensed from a storage medium. The system may include an integrated low pass and rotation filtering circuit operable to simultaneously apply a low pass filtering function and phase rotation function to a series of digital samples derived from the information sensed from the storage medium to yield a modified output. Application of both the low pass filtering and phase rotation functions is governed at least in part based upon a selected coefficient set corresponding to a combination of the phase off set value and a boost value.

Abstract: A method for improving bandwidth of an oscilloscope involves, in preferred embodiments, the use of frequency up-conversion and down-conversion techniques. In an illustrative embodiment the technique involves separating an input signal into a high frequency content and a low frequency content, down-converting the high frequency content in the analog domain so that it may be processed by the oscilloscope's analog front end, digitizing the low frequency content and the down-converted high frequency content, and forming a digital representation of the received analog signal from the digitized low frequency content and high frequency content.

Abstract: One embodiment describes a reciprocal quantum logic (RQL) sense amplifier system. The system includes an input stage configured to amplify a sense current received at an input. The system also includes a detection stage configured to trigger at least one detection Josephson junction (JJ) in response to the amplified sense current and based on a clock signal to generate a single flux quantum (SFQ) pulse. The system further includes a Josephson transmission line (JTL) stage configured to propagate the SFQ pulse to an output of the RQL sense amplifier system based on at least one output JJ and to generate a negative SFQ pulse to reset the at least one detection JJ and the at least one output JJ based on the clock signal.

Abstract: An imaging apparatus includes: a pixel configured to generate a signal through photoelectric conversion; a comparator configured to compare a signal generated by the pixel with a first reference signal that changes with time; and a control unit configured to change the rate of change of the first reference signal with respect to time according to a comparison result of the comparator.

Abstract: A digital circuit arrangement for an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible. The arrangement converts the analog signals into N-bit digital signals at sample rate f0, and then subjects the converted signals to digital filtering. The value of N in some embodiments is 1 but, in any event, is no greater than 8, and f0 may be 64 times the Nyquist sampling rate but, in any event, is substantially greater than the Nyquist sampling rate. This permits digital processing to be used without incurring group delay problems that rule out the use of conventional digital processing in this context. Furthermore, adjustment of the group delay can readily be achieved, in units of a fraction of a micro-second, providing the ability to fine tune the group delay for feed forward applications.

Abstract: Pixels within an image sensor pixel array are sampled by corresponding conditional read circuitry. A zero pixel value is outputted for each pixel associated with a sample less than a conversion threshold, and a saturated pixel value is outputted for each pixel associated with a sample greater than or equal to a saturation threshold. Samples greater than or equal to the conversion threshold and less than the saturation threshold are converted by an ADC, and a converted pixel value is output for each associated above threshold pixel. The ADC (along with any corresponding amplifiers) are powered on for a variable period depending on the number of pixels needing conversion during the conversion of such samples during a read period, and are powered off for the remainder of the read period.

Abstract: Highly efficient digital domain sub-band based receivers and transmitters.

Abstract: A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off, during the direct path mode a current signal at an input node directly appears at an output node. The mirror path mode includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on. The current signal goes through a current mirror pair and appears at the output node with a gain which is controlled by slicing one of transistors of the current mirror pair and a second current source allowing multiple gains in the mirror path mode.

Abstract: Provided is a capacitive touch sensor which includes a flat panel display for displaying an image and a touch sensor panel positioned on the flat panel display or embedded in the flat panel display. The capacitive touch sensor may include: a driving clock generator configured to generate a plurality of time-periodic output signals by using a gate driver signal of the flat panel display, and apply the generated time-periodic output signals to the touch sensor panel and a receiver circuit unit; a driver configured to generate a driving signal of the touch sensor panel using a part of the output signals of the driving clock generator; and the receiver circuit unit configured to process noise contained in a signal received from the touch sensor panel, using the output signals.

Abstract: Present disclosure describes an improved mechanism for addressing component mismatch in a DAC. The mechanism is based on carefully selecting the first DAC unit of an ordered sequence of DAC units that are switched on to convert a particular digital value to an analog value. The mechanism benefits from recognition that selecting the first DAC based on a value of a band-limited dither signal, where the band of the dither signal is selected to be sufficiently removed from the band of the signal of interest, allows shifting effects of DAC units mismatch away from the signal of interest in a manner that is easy to implement and control. Because dither signal is not added to the signal of interest, but is only used to control which DAC units are turned on, drawbacks of a traditional dithering method can be avoided while benefiting from the use of dither.

Abstract: A method and apparatus is provided for on-the-fly calibration of and correction for time interleave error, including generation of correction data associated with an interleave corrector employed by a system for converting a time-domain input stream, corresponding to samples acquired from an interleaved system of digitizers having impairment due to interleave mismatch, to a time-domain output stream.

Abstract: A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. A first feedback loop generates the feedback signal. A second feedback loop disrupts fractional spurious tones and a third feedback loop provides approximately zero static error.

Abstract: According to one embodiment, a solid state imaging device includes a semiconductor substrate comprising a first surface and a second surface opposite the first surface; a circuit at a side of the first surface of the semiconductor substrate; a pixel in the semiconductor substrate and converting light from a side of the second surface into electric charge; and an element at a side of the second surface of the semiconductor substrate. The pixel includes a photo diode in the semiconductor substrate at the side of the first surface, and the photo diode includes a diffusion layer in an impurity region in the semiconductor substrate at the side of the first surface.

Abstract: A circuit for converting charge measured from a touch screen into a digital signal can include a sample and hold circuit. The sample and hold circuit can sample and integrate a charge from a capacitive sense matrix, and hold a voltage signal representing the measured charge. A sigma delta converter can convert the voltage into a digital value.

Abstract: An apparatus for generating an image of touch on or about a touch-sensitive surface comprising a touch panel is disclosed. The touch panel can include a plurality of touch sensors configured for detecting one or more touch events occurring at distinct locations at about the same time. Each touch event can comprise a touching of an object against the touch-sensitive surface. A plurality of receive channels can be coupled to the touch panel for generating values representative of detected touch events. The receive channels can include a charge redistribution successive approximation register digital-to-analog converter (SAR ADC) configured to convert an analog waveform into a digital representation via a binary search and outputting the digital representation to an output register. The SAR ADC architecture can be such that it the dynamic input range can be scaled and offset adjusted.

Abstract: An image pickup device is provided, capable of complete correction with data of once analog-to-digital conversion, and prevention of excess use of switches and analog devices and/or erroneous correction, including: an image sensor having a plurality of analog-to-digital converters determining conversion results from a digital signal of higher order bit through separate steps of two or more times; a first correction unit which has a correction factor for correcting nonlinear errors of the plurality of analog-to-digital converters so as to adapt to the analog-to-digital converters and corrects a nonlinear error of a digital signal output from respective analog-to-digital converters based on a correction factor corresponding to respective analog-to-digital converters, characterized in that the first correction unit corrects the nonlinear errors after converting the digital signals from the plurality of analog-to-digital converters into a serial output.

Abstract: Disclosed is a liquid crystal display panel driving circuit for driving a liquid crystal display panel with a resolution of N bits. N-bit digital data including upper X bits and lower Y bits is inputted. The liquid crystal display panel driving circuit includes a resistor string unit according to areas, a DAC converter switching unit according to areas, and an interpolation amplifier. The resistor string unit outputs analog reference voltages at different ratios according to three areas. The DAC converter switching unit receives the N-bit digital data, selects (Y+1) analog voltages from the analog reference voltages based on the upper X bits, outputs the (Y+1) analog voltages, and outputs the (Y+1) analog voltages of different combinations based on the lower Y bits. The interpolation amplifier receives the (Y+1) analog voltages and generates an interpolated output voltage by setting weights for the (Y+1) analog voltages by using multi-factors.

Abstract: A solid-state imaging device includes pixels, vertical signal lines, a high-order AD converter configured to convert M bits, a low-order AD converter, and first and second selection circuits. The first selection circuit is configured to output, in a normal mode, voltage of the selected vertical signal line and to output correction voltage in a correction mode. The high-order AD converter calculates 2M residual voltage values each corresponding to a difference between a signal voltage value and each of 2M threshold voltage values; outputs, in the normal mode, a high-order bit digital value corresponding to the maximum one of the 2M threshold voltage values in a range below the signal voltage value, and outputs voltage having a residual voltage value corresponding to the maximum threshold voltage value; and outputs, in the correction mode, voltage having a residual voltage value corresponding to a selected threshold voltage value.

Abstract: A two-step analog-digital converting circuit includes a comparator, an upper bit counter and a pulse residue conversion unit. The comparator is configured to compare a ramp signal and an input signal, and to output a resulting comparative signal. The upper bit counter is configured to receive the comparative signal and a clock signal, and to output upper bit values corresponding to a first time interval between a generation time point of the ramp signal and a first edge of the clock signal, the first edge of the clock signal immediately preceding a state transition time point of the comparative signal. The pulse residue conversion unit is configured to receive the comparative signal and the clock signal, and to output lower bit values corresponding to a second time interval between the first edge of the clock signal and the state transition time point of the comparative signal.