Abstract: A decoding circuit and a chip are disclosed. The decoding circuit includes, connected in a sequence, a charge/discharge unit, a capacitor and a conversion unit. The charge/discharge unit is able to charge and discharge the capacitor, and a ratio of a total time required to transfer any amount of charge into the capacitor to a total time required to transfer the same amount of charge from the capacitor is a predetermined value. The conversion unit is configured to output a third level when a voltage on the capacitor exceeds a predetermined voltage and to otherwise output a fourth level.

Abstract: Described herein is a method and apparatus for enhancing the dynamic range of a digital-to-analog conversion circuit. Dynamic range enhancement (DRE) is accomplished by modifying the gain of components of the circuit so that the gain of components generating noise is effectively reduced. In a circuit utilizing a plurality of 1-bit DACs, analog signal gain is decreased when the full nominal gain of the analog portion of the circuit is not needed to obtain a desired peak output amplitude. The reduction is accomplished by effectively “disconnecting” some of the plurality of 1-bit DACs. Some or all of the 1-bit DACs are configured to have a third or “tri-state” in which there is no connection to the normal two reference levels thus providing no output. If some portion of the 1-bit DACs is placed in the tri-state, both the signal and noise gain will be reduced.

Abstract: A radio frequency (RF) transmission circuit includes an input stage, a current-mode mixer coupled to an output of the input stage, an attenuator coupled to an output of the current-mode mixer, and a matching network coupled to an output of the attenuator. The input stage, current-mode mixer, attenuator, and the matching network are configured in a series stack.

Abstract: Several methods may be used to exploit the natural physical variations of sensors, to generate cryptographic physically unclonable functions (PUF) that may strengthen the cybersecurity of microelectronic systems. One method comprises extracting a stream of bits from the calibration table of each sensor to generate reference patterns, called PUF challenges, which can be stored in secure servers. The authentication of the sensor is positive when the data streams that are generated on demand, called PUF responses, match the challenges. To prevent a malicious party from generating responses, instructions may be added as part of the PUF challenges to define which parts of the calibration tables are to be used for response generation. Another method is based on differential sensors, one of them having the calibration module disconnected. The response to a physical or chemical signal of such a sensor may then be used to authenticate a specific pair of sensors.

Abstract: A decline in image quality that is caused by a variation of a gain in an amplification circuit is suppressed. The amplification circuit includes an amplification transistor, a cascode transistor, and a control circuit. The amplification transistor amplifies an input signal. The cascode transistor is configured to, in a case where a drain-source voltage between a drain and a source is higher than a predetermined voltage, supply a substantially-constant drain current to a reference potential line with a predetermined reference potential via the amplification transistor. Further, the control circuit is configured to, in a case where an initialization instruction is issued, control the drain-source voltage to be a value higher than the predetermined voltage.

Abstract: A computing device can include a comparator coupled to an I/O pin of the computing device; a storage unit coupled to the comparator; and a counter coupled to receive an output of the comparator, an output of the counter being coupled to a computation engine to provide a limit-exceeded signal to the computation engine, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter. The computing device can further include a backup power source coupled to the volatile counter; and readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events. The computing device can be a smart card.

Abstract: A driver of a display device is disclosed. In order to solve a signal processing error likely to occur in an analog-digital converter which processes a pixel sensing signal provided from a pixel of a display panel, the pixel sensing signal is converted, or an input range of the analog-digital converter is corrected.

Abstract: In methods, systems, and devices for wireless communications are described, a user equipment (UE) may receive a downlink control information (DCI) block including DCI for a set of transport blocks scheduled for the UE, the DCI including a set of fields. The UE may decode the DCI block to obtain the DCI for the set of transport blocks, where at least two fields of the downlink control information are jointly decoded according to an encoding scheme, and where each possible output of the encoding scheme corresponds to a jointly valid combination of the at least two fields. The UE may receive the set of transport blocks from a base station based on the DCI.

Abstract: A method for operating an ultrasonic measuring device, encompassing the steps of receiving echo amplitudes, ascertaining object distances for the received echo amplitudes, computing normalized echo amplitudes for the received echo amplitudes, a received echo amplitude with a certain object distance being divided by a reference echo amplitude for the same or a similar object distance, encoding the normalized echo amplitudes, and transmitting the encoded echo amplitudes to a control unit. Also described is a related computer program, a system for carrying out the method, and a vehicle that includes a driving assistance system.

Abstract: Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

Abstract: Most of the AC-DC converters have an analog control loop, which costs additional pins for the compensator, and there are limited options to change settings when, for example, the output voltage needs to change. This specification discloses systems and methods, where a delta-sigma ADC (analog-to-digital converter) is used to digitize the input voltage. The filter after the delta-sigma ADC can give a big delay, which reduces the phase margin of the control loop. To minimize the delay, this invention ensures that, when the setpoint is reached, the input of the delta-sigma modulator is in the middle of the input range. In some embodiments, a digital control loop can be implemented using a delta-sigma modulator together with a PI controller (proportional-integrator controller).

Abstract: Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

Abstract: Sound rate modification techniques are described. In one or more implementations, an indication is received of an amount that a rate of output of sound data is to be modified. One or more sound rate rules are applied to the sound data that, along with the received indication, are usable to calculate different rates at which different portions of the sound data are to be modified, respectively. The sound data is then output such that the calculated rates are applied.

Abstract: A method for correcting gain mismatch between a first segment and a second segment of a digital-to-analog converter is provided. The first segment generates a first contribution to an analog output signal of the digital-to-analog converter based on a first number of bits of a digital input word for the digital-to-analog converter, wherein the second segment generates a second contribution to the analog output signal based on a second number of bits of the digital input word. The method includes extending a numeric range of a second control word for the second segment by a predefined number of bits, wherein the second control word is indicative of the second number of bits. Further, the method includes multiplying the second control word by a correction value that is based on information about a gain error of the first segment. The method additionally includes digitally filtering the multiplied first control word.

Abstract: A sampling circuit in a successive approximation type analog-to-digital (A/D) converting device samples a pair of analog signals constituting a differential input signal. A capacitor circuit reflects a signal level of a reference signal in the pair of analog signals through an attenuation capacitance unit and a binary capacitance unit to generate a pair of voltage signals. A comparison circuit compares the pair of voltage signals. A control circuit determines a value of each bit of a digital signal on the basis of the result of the comparison and reflects the value in the reference signal. The attenuation capacitance unit includes a fixed capacitance unit connected between a signal node at which the sampled analog signals are held and a predetermined potential node and a variable capacitance unit connected between the signal node and the predetermined potential node in parallel with the fixed capacitance unit.

Abstract: Example embodiments of the systems and methods of non-invasive continuous adaptive tuning of digitally controlled switched mode power supply based on measured dynamic response disclosed herein rely on time domain measurements for the tuning rather than on frequency response to automatically tune the system for stability and good dynamic performance. In particular, an algorithm directly measures overshoot and settling time to transients. Using this information, the algorithm minimizes both overshoot/undershoot and settling time by adjusting the parameters of a digital compensator. Since time domain measurements are directly used, the implementation does not require an additional perturbation in the system that otherwise would be necessary.

Abstract: An amplifying circuit for analog to digital converter with multi-stage conversion range is used for dividing an analog input voltage into multiple voltage ranges to perform signal amplification and attenuation according to multiple magnifications (e.g., amplify the analog input voltage with low voltage level, and attenuate the analog input voltage with high voltage level). The analog to digital converter performs analog to digital conversion to the analog input voltage with amplification or attenuation to generate a digital bit with amplification or attenuation, and then generates an output digital bit according to the digital bit and the magnification. As a result, the analog to digital converter is adaptive to the analog input voltage with high voltage level, and precision and quantization error of the analog input voltage with low voltage level can be maintained as well.

Abstract: The present disclosure is directed towards a sensor interface module that delivers a supply voltage to a plurality of sensors, and which exchanges data signals between the plurality of sensors and a control unit (e.g., an ECU). The sensor interface often employs a single-bit comparator (or a coarse analog to digital converter (ADC), e.g., a 2-bit or 3-bit ADC) to track signals to be exchanged between the sensors and controller over the sensor interface. Compared to power hungry ADC with more bits (e.g., 32 bit ADC), the single-bit comparator/coarse ADC limits hardware complexity and power consumption. In addition, in some embodiments the sensor interface module can include an estimator and assist comparators to speed up the tracking ability of the sensor interface module. In this way, techniques provided herein facilitate reliable, low-power communication between a control unit (e.g., an ECU) and its corresponding sensors.

Abstract: A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Abstract: The present invention has been made in an effort to provide a display device comprising: a data driver; a display panel for displaying an image in response to a data signal supplied from the data driver; and a programmable gamma unit for supplying a gamma reference voltage to the data driver, wherein a different number of bits is allocated to each of decoders included in the programmable gamma unit.

Abstract: A method for controlling a multi-phase switching converter with a plurality of switching circuits, including: sensing the output current of the switching circuit and generating a current sensing signal; generating a digital phase current signal based on the current sensing signal; subtracting the digital phase current signal from a current reference signal and generating a current error signal; proportionally integrating the current error signal and generating a first bias signal; conducting a sigma-delta modulation of the first bias signal and generating a second bias signal, wherein the first bias signal is a P-bit digital signal, the second bias signal is a Q-bit digital signal, and P is larger than Q; and adjusting a control signal controlling the switching circuit based on the second bias signal.

Abstract: An analog amplifier for amplifying an analog signal and an analog filter is provided. In particular, an apparatus and method for controlling gain and cutoff frequency of the variable gain amplifier and the variable cutoff frequency filter that is capable of changing the gain and cutoff frequency are provided. The variable resistor includes a plurality of resistor segments in the variable resistor and, when a plurality of resistance candidates for the variable resistor is arranged in order of size, the resistance candidates form a geometric series.

Abstract: An analog-to-digital conversion loop adapted to generate a digital output signal corresponding to a low-pass filtered replica of an analog input signal, including an analog adder configured to receive the input analog signal and an analog feedback signal, adapted to generate an analog error signal corresponding to the difference between the analog input signal and the analog feedback signal; an analog-to-digital converter having a nonlinear input-output conversion characteristic defining a larger quantization step the more the input to be converted differs from a null value, configured to receive the analog error signal and to generate a corresponding digital error signal a digital integrator configured to receive the digital error signal, configured to generate the digital output signal corresponding to the time integration of the digital error signal; a digital-to-analog converter, configured to receive the digital output signal and to generate the analog feedback signal as analog replica of the digital out

Abstract: A driving circuit includes a plurality of reference voltage lines and a digital to analog converter. The reference voltage lines are configured for respectively transmitting different grayscale reference voltages, in which the grayscale reference voltages are divided into at least two groups, and the wire diameter/wire width of at least one reference voltage line among the reference voltage lines of a first voltage group among the at least two groups is different from the wire diameters/wire widths of the reference voltage lines of a second voltage group among the at least two groups. The digital to analog converter is coupled to the reference voltage lines to receive the grayscale reference voltages and is for converting a digital signal into a grayscale voltage according to the grayscale reference voltages.

Abstract: A system for controlling a digital sensor (CN) for measuring a physical quantity (GP) includes a transducer (TRD) delivering as output an analog signal representative of the physical quantity (GP), with means (MGD) for implementing gain and/or shift on the analog output signal (SA1) of the transducer (TRD), and with an analog-digital converter (CAN) at the output of the sensor (CN) so as to deliver a digital signal (SN1). A first means (MA1) applies a first shift to the analog signal of the physical quantity (GP), and a second means (MA2) applies a second shift to the digital signal (SN1). Control means (CMD) continuously controls the first application means (MA1), on the basis of the digital signal (SN1), as well as the second application means (MA2), on the basis of the digital signal (SN1) and/or of the first shift.

Abstract: An analog to digital converter includes: a first pulse delay circuit forming a multi-stage delay unit of which each delay unit have a pulse signal delayed with a delay time responding to an input voltage; a first encoding circuit that detects the number of delay units in the first pulse delay circuit through which the pulse signal passes during a predetermined measurement period, and outputs the AD conversion data based on the number of delay units; and a timing generation circuit which, in response to receiving the start signal, generates an end signal when the input voltage of the first pulse delay circuit is a specified voltage within an allowable input voltage range, in order to determine the measurement period which is a time required for the pulse signal to pass through a predetermined number of the delay units which is specified in advance.

Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter” by merging a traditional ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares concept. Two basic architectures include one based on two squaring cells in the feedforward and feedback paths and a second based on a single squaring cell in the forward path. High-order ?? LOG-RMS can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The embodiments as described allow the implementations of ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.

Abstract: The device comprises a successive approximation register, a capacitive digital-to-analog converter comprising a plurality of capacitors, the plurality of capacitors being coupled with a first side to a common node; a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage at the common node with another voltage level, and a SAR control stage for providing a digital code representing a conversion result. The device is configured to operate in a calibration mode, where the device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors by coupling one side of the first capacitor to the reference voltage, to perform a regular conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor and to provide the conversion result of the regular conversion cycle for calibrating the first capacitor.

Abstract: Methods, circuits, and systems for time encoder-based unmixing of hyperspectral imaging data are disclosed. A method of unmixing hyperspectral imaging data includes receiving mixed image data of one or more pixels. The mixed image data is generated by an imaging device that captures hyperspectral data. The mixed image data includes sensed spectral band intensities of materials in an area represented by a particular pixel. The mixed image data is converted from first analog domain signals into pulse domain signals. A solution to a mixing equation in the pulse domain is generated to identify abundances of one or more of the materials based on the sensed spectral band intensities. The sensed spectral band intensities are compared to reference spectral band intensities of a set of considered materials. The solution is converted from a pulse domain into an analog domain as second analog domain signals.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×M+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate.

Abstract: An analog to digital converter by using an exponential-logarithmic model includes an exponential circuit which acquires an analog input voltage and generates an analog output voltage that is an exponential function of the input voltage. A positive feedback circuit that succeeds the exponential circuit exhibits a natural logarithmic characteristic. A comparator is connected to the positive feedback circuit to compare an output voltage of the positive feedback circuit with a reference voltage. Via the exponential-logarithmic conversion technique, the time interval or pulse produced by the positive feedback circuit is a linear function of the magnitude of the input voltage. Based on the comparator output, a counter is employed to translate the analog input signal to its digital representation.

Abstract: A signal-linearization system and method reduces nonlinear distortions in a digitized signal generated by an analog-to-digital converter (ADC) when converting an analog input signal from analog to digital form. A signal adder adds a dither waveform to the analog input signal. An ADC includes sample-and-hold (S/H) circuitry and quantizer circuitry. The ADC converts the analog input signal with the added dither waveform into a digitized signal. The dither waveform operates to suppress nonlinear distortions attributed to the quantizer circuitry. A linearizer processor performs nonlinear equalization (NLEQ) on the digitized signal to suppress nonlinear distortions attributed to the S/H circuitry. A dither waveform removal module removes a digital counterpart of the dither waveform from the digitized signal.

Abstract: A logarithmic analog to digital conversion method for an analog input signal includes a logarithmic amplification with progressive compression of the input signal delivering a sequence of several secondary analog signals. The trend of the values of at least some of the secondary signals is a function of the values of the analog input signal including regions corresponding to a linear trend of the secondary signals as a function of that of the input signal expressed in a logarithmic scale. The method also includes a comparison of at least some of the secondary signals of the sequence with a common reference signal whose value lies within each of regions, supplying a thermometric code information item, and a generation of a first digital word from the thermometric code information item.

Abstract: An N-bit digital-to-analog converting device includes: a decoder for converting an N-bit binary digital signal into a multi-bit thermometer code during each cycle of a clock signal alternating between first and second states, N being an integer not less than two; a random number generator for generating a reset signal having at least one high logic level bit and at least one low logic level bit that are equal in number and that have a random, time-varying arrangement; and a converting module coupled electrically to the decoder and the random number generator, and configured to convert the thermometer code into an analog voltage corresponding to the digital signal when the clock signal is in the first state, and to reset the analog voltage to a reset value according to the reset signal when the clock signal is in the second state.

Abstract: A device for continuous time quantization of an input signal, in order to supply a continuous time output signal that is quantized as two bits, the device including: an electronic circuit, designed to supply a first bit of the output signal called the sign bit which at any time takes a first value when the input signal is positive and a second value when the input signal is negative, and an envelope analysis circuit designed to supply a second bit of the output signal called the envelope variation bit which at any time takes a first value, called high value, when an envelope signal of the input signal is increasing, and a second value, called low value, when the envelope signal is decreasing.

Abstract: An electronic device and a method for driving an internal function block of a processor of the electric device to operate in a linear region. The electronic device comprises a processor having two multiple purpose pins (MPP1 and MPP2), an external device connection port, and two resistance elements. The external device connection port is further connected to the MPP1 and at a tested voltage. The first resistance element is connected between a high level voltage and the external device connection port. The second resistance element is connected between the external device connection port and the MPP2. The processor is configured to output the high or low level voltage at MPP2 when the tested voltage is in a non-linear operating region, to guarantee the tested voltage to a linear operating region of the function block which is coupled to the MPP1 by a multiplexing design.

Abstract: A signal processing apparatus includes: a digital processing unit to which a digital input signal is supplied, which performs a digital process on the digital input signal to produce a digital signal, and which produces a control signal designating a specific time period when an amplitude of an analog output signal is to be lowered; a DA-conversion unit which converts the digital signal to produce an analog signal; and a variable gain unit which adjusts an amplitude of the analog signal to produce the analog output signal, and which lowers the amplitude of the analog output signal during the specific time period designated by the control signal.

Abstract: The present invention provides an analog to digital converter by using an exponential-logarithmic model. The exponential-logarithmic analog-to-digital converter includes an exponential circuit which acquires an analog input voltage and generates an analog output voltage that is an exponential function of the input voltage. A positive feedback circuit that succeeds the exponential circuit exhibits a natural logarithmic characteristic. A comparator is connected to the positive feedback circuit to compare an output voltage of the positive feedback circuit with a reference voltage. Via the exponential-logarithmic conversion technique, the time interval or pulse produced by the positive feedback circuit is a linear function of the magnitude of the input voltage. Based on the comparator output, a counter is employed to translate the analog input signal to its digital representation.

Abstract: For coarse resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row are fed into multiplexers, wherein the multiplexers produce output voltages. DAC circuit designs extend the resolution of the output voltages by feeding them into a voltage interpolation amplifier. A method and apparatus are disclosed for implementing Gray code to design coarse DAC architecture for voltage interpolation such that the number of switches required by the circuit is significantly reduced, thereby decreasing required surface area, and improving glitch performance without increasing design complexity.

Abstract: An adjustable analog-digital converter arrangement comprising: an input adapted for receiving an input signal; an analog-digital converter operating by successive approximation, having a signal input coupled with the input, wherein said converter is adapted for converting an analog signal at the signal input into a digital value; an attenuator with an output, wherein an input of said attenuator is coupled to the signal input and is adapted for an amplitude change of signals applied to its input, wherein the amplitude change is controllable by means of a control input, and wherein the attenuator comprises switchable capacitors and forms a part of a first stage of said analog-digital converter; a control circuit having an output coupled to the control input of the attenuator and adapted to initialize, as a function of a comparison of a signal output by the analog-digital converter with a threshold, an automatic adjustment of the attenuation by generating a control signal, and having an output for the output of

Abstract: A gain circuit comprises a main amplification unit and a first refresh unit. The main amplification unit comprises an amplifier, a first capacitor connected between a first input terminal of the gain circuit and a first input terminal of the amplifier, and a second capacitor connected between the first input terminal of the amplifier and a first output terminal of the amplifier. The first refresh unit comprises a first capacitor connected with a first terminal of the first capacitor to a common node of the first refresh unit, and a second capacitor connected with a first terminal of the second capacitor to the common node of the first refresh unit. The common node of the first refresh circuit is arranged to be supplied with a reference voltage (Vref, Vcm,ref) during a first phase of a refresh interval and connected to the first input terminal of the amplifier during a second phase of the refresh interval.

Abstract: A data driver having a positive-polarity reference voltage generation circuit, a positive-polarity decoder, a first amplifier that outputs a positive-polarity gray scale voltage, a negative-polarity reference voltage generation circuit that generates a plurality of negative-polarity reference voltages, a negative-polarity decoder that outputs first to nth negative-polarity reference voltages from among the negative-polarity reference voltages, a negative-polarity amplifier that receives the selected first to nth negative-polarity reference voltages and outputs a negative-polarity gray scale voltage, and an output switch circuit that switches and controls whether to directly connect the first output terminal and the second output terminal to first and second data lines, respectively, or to cross-connect the first output terminal and the second output terminal to the second data line and the first data line, respectively, based on a control signal.

Abstract: The digital-to-analog converter in accordance with the present invention comprises an R-2R transistor-only ladder converter and a digital controller. The controller connects to the R-2R transistor-only ladder converter and comprises at least one regulating transistor and at least one shifting transistor. The at least one regulating transistor has an aspect ratio of kR(W/L). The at least one shifting transistor has an aspect ratio of kS(W/L). Setting the aspect ratios kR(W/L) and kS(W/L) of the shifting and regulating transistors adjusts a linear output current waveform to a non-linear waveform. The method to output a non-linear current comprises acts of determining an optimum non-linear output current, dividing a linear output current into multiple sections, determining slopes of the waveform of the output current, adding a controller corresponding to an R-2R transistor-only ladder converter, setting aspect ratios kR(W/L) of regulating transistors and setting an aspect ratios kS(W/L) of shifting transistors.

Abstract: A programmable gain amplifier (PGA) includes a sample-and-hold (S&H) stage which provides an input capacitance value for storing a charge. The PGA also includes an amplifying stage, which has a gain dependent on the input capacitance value. The amplifying stage is configured to provide a variable gain, while the S&H stage is configured to provide a substantially constant input capacitance value, regardless of the gain.

Abstract: A non-linear interpolation circuit includes current interpolation units and an I-V converter. The current interpolation units receive an operating voltage corresponding to digital image data and corresponding reference voltages to generate corresponding operating currents. When the operating voltage changes, at least one of the corresponding current interpolation units generate the corresponding operating current, and the operating currents with respect to the operating voltage are superimposed to form an interpolation current. The I-V converter converts the interpolation current into an interpolation voltage. An interpolation current generating circuit and a method for converting digital data into analog data are also disclosed herein.

Abstract: Systems and methods to achieve a logarithmic digital-to-analog converter (DAC), which is easy to be implemented, and requiring reduced chip space have been disclosed. The logarithmic DAC is created by a simple and easy to scale linear DAC, which is linearly scaling a predefined voltage range. The output voltage of the linear DAC is converted to a logarithmic current value directly by the voltage-current characteristic of an integrated diode.

Abstract: A data readout system with non-uniform resolution has a pick up head for reading data stored in an optical disc and generating an analog signal, a reference voltage unit for producing a plurality of reference voltage levels, wherein voltage differences between two adjacent reference voltage levels are not all the same, a plurality of comparators for comparing the reference voltage levels with the analog signal and generating comparison results, and an encoder for encoding the comparison results into a digital signal.

Abstract: A data readout system with non-uniform resolution has a pick up head for reading data stored in an optical disc and generating an analog signal, a reference voltage unit for producing a plurality of reference voltage levels, wherein voltage differences between two adjacent reference voltage levels are not all the same, a plurality of comparators for comparing the reference voltage levels with the analog signal and generating comparison results, and an encoder for encoding the comparison results into a digital signal.

Abstract: Noise discrimination in signals from a plurality of sensors is conducted by enhancing the phase difference in the signals such that off-axis pick-up is suppressed while on-axis pick-up is enhanced. Alternatively, attenuation/expansion are applied to the signals in a phase difference dependent manner, consistent with suppression of off-axis pick-up and on-axis enhancement. Nulls between sensitivity lobes are widened, effectively narrowing the sensitivity lobes and improving directionality and noise discrimination.