Abstract: An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).

Abstract: The present disclosure provides a multi-phase clock signal phase difference detection and calculation circuit and method, and a digital phase modulation system. The detection and calculation circuit includes an auxiliary digital-to-time conversion circuit, a main digital-to-time conversion circuit, a phase detector, and a state machine. The auxiliary digital-to-time conversion circuit selects a first phase clock signal and outputs an auxiliary clock signal, adjusts the phase of the auxiliary clock signal; the phase detector detects the phases of the auxiliary clock signal and a target clock signal output by the main digital-to-time conversion circuit; the state machine adjusts the phase of the auxiliary clock signal, and adjusts the phase of the target clock signal. When the phase difference between the two signals is zero, the amount of phase adjustment by the main digital-to-time conversion circuit is the phase difference between the first phase clock signal and the second phase clock signal.

Abstract: A real-time clock device includes a resonator, a clock signal generation circuit, a time-counting circuit, a terminal, and a time-to-digital conversion circuit. The clock signal generation circuit outputs a time-counting clock signal based on an oscillation clock signal. The time-counting circuit generates time-counting data based on the time-counting clock signal. An external signal is input to the terminal. The time-to-digital conversion circuit measures a time difference between a transition timing of a first signal based on the external signal and a transition timing of a second signal based on the oscillation clock signal or the time-counting clock signal with a resolution higher than a time-counting resolution of the time-counting circuit, and obtains time difference information corresponding to the time difference.

Abstract: A serializer clock delay optimization system comprising a multiplexer configured to receive two or more low-rate data signals and a multiplexer control signal. The multiplexer generates a full-rate data signal by combining the two or more low-rate data signals such that the multiplexer control signal determines sampling time of the low-rate data signals. A data monitor monitors and evaluates the full-rate data signal to generate a quality value representing the quality of the full-rate data signal. The quality of the full-rate data signal is based on the accuracy of the sampling time of the low-rate data signals. A delay controller processes the quality value to generate a delay control signal or value. A delay receives a clock signal and the delay control signal or value. Responsive to the delay control signal or value, the delay modifies the timing of the clock signal to create the multiplexer control signal.

Abstract: Intraluminal medical devices, systems and methods are provided. In one embodiment, an intraluminal medical system includes a handheld interface device in communication with an intraluminal device to be positioned within a body lumen of a patient. The intraluminal device includes a sensor configured to obtain physiology data associated with the body lumen. The handheld interface device includes a housing sized and shaped for handheld use, a controller core disposed within the housing and configured to control a plurality of sensor types respectively associated with a plurality of intraluminal devices, a computing core disposed within the housing, and a first display integrated in the housing. The controller core is operable to identify the sensor of the intraluminal device, and control the sensor to obtain the physiology data associated with the body lumen.

Abstract: A switchable I2S interface including a multiplexer, a switchable FIFO memory and a switchable shift register, is disclosed. The multiplexer receives a transmission instruction or a receiving instruction, and configured to generate a switching signal according to the received instruction. The switchable FIFO memory is connected to the multiplexer and receives the switching signal, and comprise a transmission control circuit and a receiving control circuit. According to the switching signal, the switchable FIFO memory switches on the transmission control circuit to transmit the audio output signal, or switches on the receiving control circuit to receive the audio input signal. The switchable shift register is connected to the switchable FIFO memory, and receives and temporarily stores the audio output signal and the audio input signal.

Abstract: A microcontroller including a selection circuit, a sample and hold circuit, an analog-to-digital converter circuit, and a control circuit is provided. The selection circuit provides a first external voltage or a second external voltage as an output voltage according to a selection signal. The sample and hold circuit samples the output voltage according to a turn-on signal to generate an analog input. The analog-to-digital converter circuit converts the analog input to generate a digital output. The control circuit generates the selection signal according to the digital output, adjusts the sampling time, and then generates a turn-on signal according to the sampling time.

Abstract: An analog-to-digital converter (ADC) is based on single-bit delta-sigma quantization. The ADC includes an integrator, a threshold detector, a feedback block, a range control circuit and an output processing block. The ADC is configured to, based on its own generated digital bitstream, adjust the magnitude of a subtrahend signal in order to achieve autonomous auto-ranging of the ADC during the integration time of a measurement. In particular, the auto-ranging allows for the efficient conversion of an analog input signal with high dynamic range, for example ambient light, to a digital output signal.

Abstract: A communication system includes a digital data processor that produces a digital data sample and one or more control bits. A serialized transmit interface combines the digital data sample and the control bit(s) into one or more data packets and sends the data packet(s) over a signal line. A serialized receive interface receives the transmitted data packet(s) from the signal line and produces a reconstructed digital data sample and the control bit(s) from the transmitted data packet(s). A control circuit coupled to the serialized receive interface produces a control signal from the control bit(s). The communication system may include a converter circuit, which produces an RF input signal by performing a digital-to-analog conversion of the reconstructed digital data sample, and by upconverting the resulting analog data sample signal to RF. A power amplifier amplifies the RF input signal and modifies operation of a sub-circuit based on the control signal.

Abstract: An circuit includes: a plurality of analog-to-digital converters (ADCs) and a control chip. The control chip is utilized for instructing a target ADC to output audio data of a target channel during a target period, and utilized for instructing remaining ADCs not to output audio data in the target period. Then, the control chip defines data timing of the target channel and other channels based on the data receiving time point of the audio data of the target channel. The plurality of ADCs would process analog audio signals of a plurality of channels and output audio data of the plurality of channels according to an assigned order configured by the control chip to form a serial data signal. The control chip separates the audio data of different channels from the serial data signal according to the data timing of the plurality of channels.

Abstract: A receiver is configured to receive a series of command signals and a series of data signals. The receiver includes a first clock and data recovery (CDR) circuit, a control circuit and a second CDR circuit. The first CDR circuit is configured to process the series of command signal to generate a clock signal. The control circuit, coupled to the first CDR circuit, is configured to generate a control signal according to the series of command signals and the clock signal received from the first CDR circuit. The second CDR circuit, coupled to the control circuit, is configured to process the series of data signals according to the control signal received from the control circuit.

Abstract: The present invention provides a driving circuit for a gamma voltage generator of a source driver. The gamma voltage generator includes a resistor string having a plurality of tap nodes, among which a plurality of first tap nodes are respectively connected to a plurality of first buffers. The driving circuit includes a second buffer, a digital-to-analog converter (DAC) and a control circuit. The second buffer is connected to a second tap node other than the plurality of first tap nodes among the plurality of tap nodes. The DAC is coupled to the second buffer. The control circuit, coupled to the DAC, is configured to receive a plurality of first control signals for the plurality of first buffers and calculate a second control signal for the DAC according to the plurality of first control signals.

Abstract: The present disclosure provides a linear calibration system for a time-to-digital converter and a method thereof, and a digital phase-locked loop. The linear calibration system includes a digitally controlled reference delay circuit for receiving a first clock signal and delaying the first clock signal to generate a reference clock signal, a time-to-digital conversion circuit including at least two time-to-digital converters, and a state machine. The time-to-digital conversion circuit receives the first clock signal and the reference clock signal, delays the first clock signal to generate a first delay signal, compares a phase of the first delay signal with a phase of the reference clock signal, and outputs a phase detection result signal. The state machine generates a delay control signal for controlling the digitally controlled reference delay circuit, adjusts a calibration control signal to align the phases of the first delay signal and the reference clock signal.

Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits are configured to convert an input signal according to interleaved clock signals to generate first quantized outputs. The calibration circuit is configured to perform at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit further includes a first adjusting circuit. The first adjusting circuit is configured to analyze adjacent clock signals according to part of the second quantized outputs to generate adjusting information. The skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs and the adjusting information to generate adjustment signals. The adjustment signals are configured to reduce clock skews of the ADC circuits.

Abstract: Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.

Abstract: A phase-locked loop circuit included in a computer system includes time-to-digital converter and digital-to-time converter circuits. During a mode to test the time-to-digital converter circuit, the digital-to-time converter circuit is coupled to the time-to-digital converter circuit in a loop-back fashion. A control circuit supplies stimulus codes to the digital-time-converter circuit, which generates multiple delayed versions of a reference clock signal using the stimulus codes. The time-to-digital converter circuit, in turn, generates capture codes based on the delay between the reference clock signal and the delayed versions of the reference clock signal. The control circuit compares the capture codes to the stimulus codes to determine a linearity of a response of the time-to-digital converter circuit.

Abstract: According to an aspect of the inventive concept, there is provided a signal processing method performed in a distributed antenna system, includes extracting at least a part of sample data corresponding to an occupied frequency band from a digitized analog RF signal; and combining the extracted sample data.

Abstract: The power distribution device includes a power regulating device and a first auxiliary power distribution component. The power regulating device has a first output end connected to an AC power grid and a second output end. The first auxiliary power distribution component has a first movable end electrically connected to a load, a first fixed end electrically connected to the AC power grid and a second fixed end electrically connected to the second output end, and a ground line of the second fixed end is grounded. When the AC power grid is normal, the first movable end is connected to the first fixed end, such that the AC power grid supplies power to the load. And when the AC power grid is abnormal, the first movable end is connected to the second fixed end, such that the power regulating device supplies power to the load through the second output end.

Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

Abstract: An image sensing system is disclosed. The image sensing system includes an array of pixel circuits and a multiplexer configured to convey an output signal from a selected one of the pixel circuits. The output signal from the selected one of the plurality of pixel circuits is converted from analog to digital by a successive approximation register (SAR) analog-to-digital converter (ADC). A control circuit is provided to cause the SAR ADC power cycling with shaped power control signal. The SAR ADC comparator pre-amp with integrate-reset causes reduced power to the theoretical limit for imaging systems. The control circuit causes quantization process of selected ones of the pixel circuits to be repeated one or more times during the processing.

Abstract: An analog to digital converter (ADC) sampling time control method includes: grouping, by an electronic control unit, analog sensor signals received from a plurality of sensors based on a similar signal; setting, by the electronic control unit, a sampling time for converting the grouped analog sensor signals into digital signals; and obtaining, by the electronic control unit, a sensor value by converting the grouped analog sensor signals into the digital signals based on the set sampling time.

Abstract: A driving circuit of display apparatus includes an operational amplifier (OP), comprising a plurality of input terminals; a digital-to-analog converter (DAC); a multiplexer, coupled to the OP and the DAC, comprising a plurality of switches; and a boosting module, configured to decrease an equivalent time constant between the DAC and the OP to increase an output slew rate of the OP in a boosting period; wherein the boosting period is enabled before a steady state of the OP.

Abstract: An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage Vref=M*VDD, where M<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator.

Abstract: A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit.

Abstract: It is provided a provided a time-interleaved analog-to-digital converter (ADC) system comprising an input port configured to receive an analog signal, an ADC-array comprising M, M?2, ADCs arranged in parallel. Each ADC is configured to receive and to convert a portion of the analog signal into a digital signal at a sample rate fs. The ADC-system further comprises a reference ADC configured to receive and to convert the analog signal into a digital reference signal at an average sampling rate fref lower than fs. Each sampling instant of the reference ADC corresponds to a sampling instant of an ADC in the array of ADCs, and the ADC to select for each reference ADC sampling instant is randomized over time. The ADC-system also comprises a correction module configured to adjust the digital signal outputs of the ADC-array into a corrected digital output signal based on samples of the digital reference signal and the digital signals from the corresponding selected ADCs.

Abstract: A digital-to-analog conversion circuit (DAC) is operable to convert an input digital signal to an output analog signal. The DAC includes a digital signal processing circuit operable to process the input digital signal according to a first transfer function to generate a first processed digital signal and process the digital input signal according to a second transfer function to generate a second processed digital signal. The DAC includes a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal, and a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal. The DAC includes switching circuits and a combiner circuit to generate the output analog signal from the intermediate analog signals.

Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

Abstract: An analog-to-digital conversion apparatus includes a controller. The controller is configured to execute first control processing to cause the selection circuit of each of the circuit sets to perform switching which involves cyclically changing an analog signal to be selected at sampling timings with a predetermined time difference, and second control processing to calculate a digital data item at a reference sampling timing for each of the analog signals based on digital data items obtained from the analog-to-digital converter of the plurality of circuit sets, in accordance with the digital data items with the predetermined time difference, the sampling timings, and the time difference.

Abstract: A circuit includes a first external terminal, a first lower resolution analog-to-digital converter (LRADC) coupled to the external terminal and configured to perform a first conversion of an analog signal received at the external terminal to a digital value, and a higher resolution analog-to-digital converter (HRADC). The HRADC is configured to selectively receive the analog signal from the first external terminal based on the digital value. When the digital value outputted by the first LRADC indicates a change in value of the received analog signal, the HRADC is provided with the analog signal and performs a second conversion of the analog signal to a second digital value. The first LRADC has a lower conversion resolution as compared to the HRADC.

Abstract: An integrated charge redistribution successive approximate register (CR-SAR) analog-to-digital converter (ADC) includes a sample-and-hold switch, a digital-to-analog converter (DAC), a comparator and a logic circuit. The sample-and-hold switch obtains a sample input voltage (Vin). The DAC includes a plurality of digital multiplexers that selects between a superposition phase, which superimposes an analog offset voltage onto Vin, and a conversion phase which determines values for a digital output register which determines the input values to each control line. Each digital multiplexer presents input values to a control line. The comparator has two inputs coupled to the sample-and-hold switch and to the DAC such that the output of the converter determines a value of each successive bit in the digital output register. The logic circuit is coupled to the comparator and to digital multiplexers and includes the digital output register.

Abstract: An oscillator and method for operation of the oscillator are provided. The oscillator includes a control voltage generator configured to generate a control voltage based on dividing a power voltage that was received, an offset voltage generator configured to generate an offset voltage based on dividing the power voltage that was received, a phase locked loop (PLL) including a varactor circuit configured to modify a capacitance based on the control voltage and the offset voltage, and a calibration logic circuit configured to provide a selection control signal to the control voltage generator based on the oscillation signal, and configured to provide an offset control signal to the offset voltage generator based on the oscillation signal.

Abstract: An imaging device includes imaging elements 12 arranged in two-dimensional matrix in a first direction and a second direction, an analog-digital (AD) converter 13, and a pixel signal reading device 16. The pixel signal reading device 16 selects spatially at random the imaging element 12 that outputs a pixel signal to the AD converter 13, and randomly outputs the pixel signal of the imaging element 12 from the AD converter 13.

Abstract: Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

Abstract: Embodiments described herein include devices, methods, and instructions for managing beam interpolation in massive multiple-input multiple-output (MIMO) communications. In one example embodiment, an evolved node B is configured to transmit to a UE using massive MIMO by transmitting multiple beamformed reference signals on multiple transmission beams each associated with a different plurality of antennas. The eNB receives beam interpolation information back from the UE, and then generates a data transmission that is sent to the UE using an interpolated transmission beam from a first and second transmission beam.

Abstract: A method (10) of encapsulating digital communications signals for transmission on a communications link, comprising steps: a. receiving a first signal of a first signal type and comprising a first clock signal and receiving a second signal of a second signal type, different to the first, and comprising a second clock signal different to the first clock signal, each clock signal having a respective clock value and accuracy (12); b. obtaining the first clock signal (14); c. obtaining a difference between at least one of the clock values of the clock signals and the accuracies of the clock signals (16) and buffering the second signal for a time at least long enough to compensate for the difference (18); and d. assembling the first signal and the buffered second signal into a frame comprising an overhead and a payload comprising a first portion and a second portion, mapping the first signal into the first portion and the second signal into the second portion (20), wherein step d.

Abstract: An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

Abstract: Method and apparatus for nonlinear signal processing include mitigation of outlier noise in the process of analog-to-digital conversion and adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. Methods, processes and apparatus for real-time measuring and analysis of variables include statistical analysis and generic measurement systems and processes which are not specially adapted for any specific variables, or to one particular environment. Methods and corresponding apparatus for mitigation of electromagnetic interference, for improving properties of electronic devices, and for improving and/or enabling coexistence of a plurality of electronic devices include post-processing analysis of measured variables and post-processing statistical analysis.

Abstract: An electronic device includes a power management integrated circuit (PMIC) including a plurality of regulators. Each of the plurality of regulators has a current meter configured to measure a respective load current. A load device is configured to receive real-time load current information from the PMIC and to perform a performance improvement operation based on the real-time load current information.

Abstract: An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.

Abstract: A method of performing a hail communication attempt includes checking capacitor voltage of a capacitor in a battery pack powering a hailing device to determine whether the capacitor voltage equals or exceeds a threshold voltage, and responsive to determining that the capacitor voltage equals or exceeds the threshold voltage, transmitting a hail (ping) message to a target device, determining whether the hailing device has received a responsive pong message from the target device, and responsive to determining that the hailing device has received a responsive pong message, terminating the hail communication attempt in preparation for sending data to the target device. Hail communication attempts are limited according to a predetermined number of consecutive groups of consecutive hail messages, with the capacitor voltage check occurring before the sending of each group.

Abstract: A display driver is configured to drive a display device according to a video signal. The display signal includes a plurality of first to N-th output amplifiers (N is an integer greater than two) and an output electrical current capacity setting portion. The first to N-th output amplifiers are configured to amplify first to N-th gradation voltages a representing brightness level per pixel according to the video signal, so that the first to N-th output amplifiers obtain first to N-th pixel drive voltages. Further, the first to N-th output amplifiers are configured to output the first to N-th pixel drive voltages to the display device. The output electrical current capacity setting portion is configured to set an output electrical current capacity of each of the first to N-th output amplifiers individually or in a group of a plurality of output amplifiers.

Abstract: A method and apparatus are disclosed for asynchronous clock generation in analog-to-digital converters (ADCs). For example, an ADC may comprise a comparator, a first logic gate, a second logic gate, a first memory element, a second memory element, and a digital-to-analog converter (DAC). The comparator may initiate an evaluation or precharge operation of comparator inputs. The first logic gate may generate, based on comparator outputs, a first output signal indicating validity of first logic gate output. The second logic gate may generate a second output signal indicating timing reference of bit conversion. The first memory element may generate a third output signal indicating a current state of a bit. The second memory element may generate a plurality of next state bits based on the second output signal and the comparator outputs. The second logic gate may generate the second output signal based on the first and third output signals.

Abstract: An audio processing device that includes a first ADC, a second ADC, a register and a processing circuit is provided. The processing circuit executes a first audio application program corresponding to a first analog input audio stream and assigns the first analog input audio stream to the first ADC. When the processing circuit identifies that a second audio application program also corresponds to the first analog input audio stream, the processing circuit control the first ADC to process the first analog input audio stream. When second audio application program corresponds to a second analog input audio stream, the processing circuit assigns the second analog input audio stream to the second ADC for processing such that the first and the second ADCs process the first and the second analog input audio stream respectively.

Abstract: A control system for an analog to digital converter (ADC) including a programmable configuration memory, a trigger selector, an input selector, and a conversion controller. The ADC is configurable for adjusting multiple operating parameters including speed and accuracy. The programmable configuration memory stores at least one configuration variable and an input value. The trigger selector enables at least one trigger input. The input selector selects from among multiple analog inputs according to the programmed input value. The conversion controller configures the ADC using the configuration variable, interfaces the input selector to provide an analog input to the ADC, and interfaces the trigger selector to prompt the ADC to perform a conversion process to provide a digital output sample in response to the enabled trigger input.

Abstract: When imaging bright objects, a conventional detector array can saturate, making it difficult to produce an image with a dynamic range that equals the scene's dynamic range. Conversely, a digital focal plane array (DFPA) with one or more m-bit counters can produce an image whose dynamic range is greater than the native dynamic range. In one example, the DFPA acquires a first image over a relatively brief integration period at a relatively low gain setting. The DFPA then acquires a second image over longer integration period and/or a higher gain setting. During this second integration period, counters may roll over, possibly several times, to capture a residue modulus 2m of the number of counts (as opposed to the actual number of counts). A processor in or coupled to the DFPA generates a high-dynamic range image based on the first image and the residues modulus 2m.

Abstract: An electronic device includes a load device and a power management integrated circuit. The power management integrated circuit is configured to calculate a load power value and provide the load power value to the load device in response to a request from the load device. The power management integrated circuit includes a plurality of regulators and a controller. Each of the plurality of regulators includes a current meter for measuring a load current value to be provided to the load device, and the controller is configured to calculate the load power value by using the load current value measured by the current meter and a load voltage value provided from each of the plurality of regulators to the load device.

Abstract: A multiple impedance string, multiple output digital-to-analog converter (DAC) circuit that can include a shared coarse resolution DAC, two first fine resolution DACs to receive outputs of the MSB DAC, and a multiplexer to multiplex outputs of the first and second fine resolution DACs to output terminals. The multiplexer can be configured to interchange coupling of the outputs of the first and second fine resolution DACs using one or more MSBs.

Abstract: Embodiments of the present disclosure may include an ADC circuit including channel register sets, a conversion request flip-flop, a priority encoder circuit, and a controller circuit. The controller circuit may be configured to receive a conversion request signal, latch the conversion request signal into the conversion request flip-flop, determine by the priority encoder circuit a highest priority pending conversion request, and output an active channel identifier code. The channel identifier code may be configured to select the data channel register sets that are active by identifying received selection bits. The embodiments may include logic to store a converted value from a selected analog input to a data output register based on the channel identifier code.

Abstract: A system includes an apparatus and a processor. The apparatus includes a set of actuator elements that move between two positions. Each actuator element is comprised in: exactly one first subset out of a plurality of non-empty first subsets and exactly one second subset out of a plurality of non-empty second subsets. The processor is configured to generate one or more control commands for a group of subsets out of the first and the second pluralities of subsets in response to a number of moving elements which, if released from the first extreme position during a second sampling cycle, enables production by the apparatus during the second sampling cycle of a sound.

Abstract: An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/fs; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N?1)/fs; and by a delay of 1/fs. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of fs.