Abstract: A switched capacitor circuit includes an output capacitor, a first transmission switch, a first reference buffer, a second transmission switch, a second reference buffer and a charge compensation circuit. The output capacitor includes a first terminal and a second terminal, wherein the first terminal is coupled to an output terminal of the switched capacitor circuit, and the second terminal is coupled to a reference node. The first transmission switch is coupled to the reference node. The first reference buffer is coupled to the first transmission switch. The second transmission switch is coupled to the reference node. The second reference buffer is coupled to the second transmission switch. The charge compensation circuit is coupled to the reference node.

Abstract: The invention relates to the representation of digital signals. In order to improve the perception by a user of the quality of a digital signal, a first sample of first digital signal is approximated to a second sample of a second digital signal having a second number of significant bits lower than the first number of significant bits of the first sample. The second number of significant bits is also lower than a number of significant bits allowing the second digital signal, or a signal derived therefrom to match an expected bit depth of a processing unit said second digital signal, or a signal derived therefrom is to be sent to.

Abstract: Techniques described herein are related to spread amplifier having a differential amplifier spread (DAS) configured to receive a pair of input signals and to provide a plurality of graded outputs each having different output levels. The spread amplifier further includes a final driver stage having a plurality of final drivers, wherein each of the final drivers is configured to receive a respective one of the plurality of graded outputs. The spread amplifier may be used for the regulation of various voltages such as VDQS and VARY.

Abstract: A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device has a first input terminal and a second input terminal for receiving a received signal and an adjustable reference voltage respectively, and for generating an output signal at an output port. The first digital-slope quantizer is coupled to the output port and the second input terminal for generating a first set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer is coupled to the output port and the second input terminal for generating a second set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a second phase after the first phase according to a second quantization unit.

Abstract: A circuit for correlated double sampling is disclosed. In one aspect, the circuit comprises a reset switch connected with an input node, and with a first node of a first capacitor; a sampling switch connected with the input node, and with a first node of a second capacitor; a second node of the first/second capacitor is adapted to be connected with a first/second reference node, of which at least one using a reference switch; a first switch connected between the second node of the first capacitor and the first node of the second capacitor; a second switch connected between the first node of the first capacitor and the second node of the second capacitor.

Abstract: A method for virtually performing delta-sigma digitization is provided. The method is performed on a series of digital samples output from a communication stack of a communication network. The method includes steps of obtaining a delta-sigma digitization sampling frequency for the output series of digital samples, calculating an oversampling ratio for the output series of digital samples, interpolating the output series of digital samples at a rate equivalent to the oversampling ratio, and quantizing the interpolated series of digital samples to plurality of discrete predetermined levels.

Abstract: An array of antennae includes a monobit transmitter to insert dither into a transmit signal to form a dithered transmit signal. Monobit receivers process received signals that are combined with the dithered transmit signal to form composite received signals. Digital down converters process the composite received signals to form down converted received signals. A beam former circuit processes the down converted received signals to form recovered signals.

Abstract: A filter includes M filter circuits. The M filter circuits are sequentially cascaded from an input terminal to an output terminal, in order to generate an output signal according to an input signal, in which M is a positive integer greater than or equal to 2. The M filter circuits include at least one first filter circuit and at least one second filter circuit. Each of the at least one first filter circuit is set to be an active filter circuit, and each of the at least one second filter circuit is set to be a passive filter circuit.

Abstract: A system includes an analog-to-digital converter (ADC) and a digital modulator coupled to the ADC, wherein the digital modulator comprises an output for providing a digital signal, wherein the digital modulator comprises a main signal path and a feedback path, and wherein the feedback path comprises a first digital gain stage having a first adjustable gain range.

Abstract: The present disclosure discloses a communication apparatus including a receiver circuit and a transmitter circuit having a signal processing circuit and a DAC circuit having a primary conversion circuit and a first hybrid conversion circuit. The primary conversion circuit converts and transmits a transmission signal from the signal processing circuit to a signal transmission path. The first hybrid conversion circuit converts the transmission signal to a first receiver resistor to generate a voltage drop. The receiver circuit receives a first actual receiving signal through the signal transmission path and the first receiver resistor. The primary conversion circuit operates according to a first current including a first and a second part currents and the first hybrid conversion circuit operates according to a second current. The first part current does not change according to a resistive change. The second part current and the second current change according to the resistive change.

Abstract: A delta-sigma modulator generates a bit stream signal from an analog signal by operating according to a modulation period including a sampling period and a filtering period and includes a digital-to-analog converter (DAC) configured to generate a charge signal according to one of a first reference voltage and a second reference voltage according to the bit stream signal during the sampling period and to output a signal generated according to the charge signal and the other of the first reference voltage and the second reference voltage; a loop filter configured to charge a sampling signal corresponding to the analog signal during the sampling period and to filter an output from the DAC and a signal generated according to the sampling signal during the filtering period; and a quantizer configured to generate the bit stream signal according to an output from the loop filter in the modulation period.

Abstract: An analog-to-digital converter comprises a sigma-delta modulator; and an ADC filter configured to store a plurality of partial sums as respective entries in a plurality of lookup tables, retrieve at least one of the plurality of partial sums based on an output of the sigma-delta modulator, and calculate a filter output by adding retrieved ones of the plurality of partial sums together.

Abstract: Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches and/or errors. The mismatches and/or errors can degrade the quality of the analog output. To extract the mismatches and/or errors, a transparent dither can be used. The mismatches and/or errors can be extracted by observing the analog output, and performing a cross-correlation of the observed output with a switching bit stream of the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the respective mismatches and/or errors.

Abstract: A system, method, and non-transitory computer readable medium that detects trajectories of unmanned aerial vehicles (UAV) approaching a protected site is described. Airborne defense agents (ADAs) located at a fixed radius from the protected and equidistant from one another detect acoustic signals emitted by an approaching UAV. Circuitry included in each ADA use the detected acoustic signals to determine a direction and a distance of each UAV. A base station having a control center (BS-CC) located in the protected site communicates with the ADAs to aggregate direction and distance data from the ADAs. Using the aggregated direction and distance data, the BS-CC predicts routes towards the protected site of the approaching UAV and alerts the protected site of the predicted route of the approaching UAV.

Abstract: A delta sigma modulator includes a summation circuit, at least one integrator, a multi-bit quantizer and a negative feedback circuit. The summation circuit is configured to produce a difference signal between an analog input signal and an analog feedback signal. The integrator is operatively coupled to the summation circuit to integrate the difference signal. The multi-bit quantizer is operatively coupled to the integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1. The negative feedback circuit operatively couples the multi-bit quantizer to the summation circuit. The negative feedback circuit includes a digital-to-analog converter arrangement for receiving the N-bit digital output signal and providing the analog feedback signal such that digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another.

Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

Abstract: A signal compensation device is disclosed. The signal compensation device includes an operation circuit and a modulation circuit. The operation circuit is configured to generate a control signal according to a first data signal and a second data signal, in which the second data signal is generated according to the first data signal by a signal conversion circuit. The modulation circuit is configured to provide a loop gain according to the control signal to compensate an attenuation of the signal conversion circuit.

Abstract: An A/D converter includes: a sampler that includes a sampling capacitor and samples an input signal; a D/A converter that selectively outputs an analog voltage; an integrator that integrates an input from the sampler and an input from the D/A converter; Multiple switches that include a first switch independently connecting the sampler to the integrator, a second switch independently connecting the D/A converter to the integrator, a third switch, and, a fourth switch, a quantizer that quantizes an output of the integrator; a control circuit that outputs a digital value based on an output of the quantizer, and a reference potential generation circuit that provides a second reference potential to an integrator side of the sampler through the third switch and provides a first reference potential to the integrator side of the D/A converter through the fourth switch.

Abstract: A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.

Abstract: An analog-to-digital converter (ADC) is provided. The ADC receives an analog input signal and generates a digital code. The ADC includes a sigma-delta modulator (SDM), a decimation filter and a detection circuit. The SDM includes a loop filter, a quantizer and a digital-to-analog converter (DAC). The loop filter receives the analog input signal. The quantizer is coupled to the loop filter and quantizes an output of the loop filter to generate a digital output signal. The DAC is coupled to the quantizer and the loop filter. The decimation filter is coupled to the SDM and converts the digital output signal into the digital code. The detection circuit is coupled to the SDM and detects a node voltage of the SDM and generate a control signal. The control signal is utilized to control the loop filter, the quantizer, a feedback path of the SDM and/or a feedforward path of the SDM.

Abstract: A system, method, and non-transitory computer readable medium that detects trajectories of unmanned aerial vehicles (UAV) approaching a protected site is described. Airborne defense agents (ADAs) located at a fixed radius from the protected and equidistant from one another detect acoustic signals emitted by an approaching UAV. Circuitry included in each ADA use the detected acoustic signals to determine a direction and a distance of each UAV. A base station having a control center (BS-CC) located in the protected site communicates with the ADAs to aggregate direction and distance data from the ADAs. Using the aggregated direction and distance data, the BS-CC predicts routes towards the protected site of the approaching UAV and alerts the protected site of the predicted route of the approaching UAV.

Abstract: A delta-sigma (?-?) modulator and method for reducing nonlinear error and gain error. The ?-?modulator includes: a plurality of sampling capacitors, configured to sample an input voltage or simultaneously sample an input voltage and a reference voltage signal; an operational amplifier; a plurality of switches, configured to select to sample the input voltage and the reference voltage signal; an integrating capacitor, configured to perform integration superposition on the input voltage and the reference voltage signal sampled by the sampling capacitors; and a control assembly, configured to control, to select to sample the reference voltage signal or simultaneously sample the input voltage and the reference voltage signal within a cycle, and to perform clock control on the sampling capacitors that simultaneously sample the input voltage and the reference voltage signal within a next cycle.

Abstract: An A/D conversion device, which operates in one mode including at least one of a ?? mode, a cyclic mode, and a hybrid mode, includes: a first block that processes an analog input signal by a first amplifier; a second block including a second amplifier; a quantization unit that quantizes one of outputs of the first and second blocks; and a control circuit that switches the mode to perform a control corresponding to the mode.

Abstract: A system for generating a control signal for a capacitive sensor includes a waveform generator configured to generate a digital waveform, a first sigma-delta modulator (SDM) configured to generate a first output corresponding to the control signal based on the digital waveform and first adjustment data and a second SDM configured to generate a second output corresponding to an offset signal based on the digital waveform and second adjustment data. The first SDM is configured to selectively adjust a phase and an amplitude of the control signal and the second SDM is configured to selectively adjust a phase and an amplitude of the offset signal.

Abstract: An integrated circuit microprocessor device comprises a central processing unit (CPU) and a general purpose input or output subsystem (2) having at least one external connection (4). The external connection is configured to provide an input to or output from the device depending upon an associated setting in the general purpose input or output subsystem. At least one further module on the device is configured to be able to request at least a first or a second task which may control a state of the external connection, the general purpose input or output subsystem being configured, upon receipt of conflicting requests for the first and second tasks, to apply a predetermined priority to allow only one of the tasks to be applied to the external connection.

Abstract: Systems and methods for low power sample rate conversion are based on a noise shaping technique. A sample rate conversion circuit includes a clock synchronization circuit configured to receive an input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate. The valid sample sequence may include valid samples from a registered sequence sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence. The sample rate conversion circuit also includes a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

Abstract: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

Abstract: A method for differentiator-based compression of digital data includes (a) multiplying a tap-weight vector by an original data vector to generate a predicted signal, the original data vector comprising N sequential samples of an original signal, N being an integer greater than or equal to one, (b) using a subtraction module, subtracting the predicted signal from a sample of the original signal to obtain an error signal, (c) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (d) updating the tap-weight vector according to changing statistical properties of the original signal.

Abstract: According to an exemplary embodiment, a capacitively coupled continuous-time delta-sigma modulator includes an instrumentation amplifier amplifying an input voltage to an output voltage of a predetermined magnitude, a delta-sigma modulator outputting a bit signal quantized depending on a sampling frequency based on the output voltage and to convert the bit signal into a digital-to-analog conversion voltage, and a ripple reduction loop unit generating a demodulation voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency to feed the demodulation voltage back to the instrumentation amplifier. The RRL operating frequency is equal to the sampling frequency.

Abstract: An audio processing system can include an Analog to Digital Converter structured to receive an analog input signal and convert the analog input signal to a digital input signal, a first processor coupled with the Analog to Digital Converter, the first processor including at least one programmable bi-quadratic filter chain structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a first clock rate, and a second processor coupled with the first processor and the Analog to Digital Converter and structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a second clock rate that is different from the first clock rate.

Abstract: A sigma-delta analog-to-digital converter (ADC) includes a feed-forward circuit, a finite-impulse-response (FIR) digital-to-analog converter (DAC), and a decimation filter. The feed-forward circuit is configured to receive an analog input signal and a feedback signal and generate a set of digital signals. Each feedback element of the FIR DAC includes a flip-flop and a reset circuit. The reset circuit is configured to receive a corresponding reset signal of a set of reset signals and output a reference output signal when the corresponding reset signal is deactivated. The reset signal of each feedback element is deactivated sequentially after each cycle of a clock signal that is received by the flip-flop associated with a corresponding reset circuit of each feedback element. The feedback signal is generated based on the reference output signal. The decimation filter is configured to generate a digital output signal based on the set of digital signals.

Abstract: A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.

Abstract: Repetitive waveforms are processed to produce an averaged replica of the waveforms by first determining a stream of digital samples, with random time shifts of waveform starts relative to the samples. A mutual arrangement of a trigger signal and a following sample over a succession of sampling periods, enables k sections coinciding with segments [k·T/K, (k+1)·T/K]. K is determined and a distance D between the trigger signal and the following sample is calculated. Second, values of the samples are transformed so that waveforms represented by the samples, are shifted in time by D in relation to the sample positions. The mutual positions of the delayed waveforms and the sampling clock along multiple axes, exactly repeats so that values of the produced samples along the axes coincide. The discreet time delays before averaging avoid frequency component distortions in resulting replicas of the waveforms.

Abstract: A signal processing structure and method are presented. A first digital filter operates on received sigma-delta modulated (SDM) input signals. A second pre-processing digital filter receives a SDM input signal, directly low pass filter the SDM input signal and provides an output SDM signal. The output sigma-delta modulated signal is provided as an input for said first digital filter. In standard digital systems operating with digital microphones, filtering of the microphones' output signal requires to first convert the signal into pulse code modulation (PCM), then filter and finally convert back to pulse density modulation (PDM). This approach increases the latency of the system because decimation and interpolation must be performed in order to pass from PDM to PCM. By using filters that operate directly on the oversampled PDM output of the digital microphones it is possible to reduce the latency of the system and minimize the hardware area.

Abstract: A channel driver circuit includes a differential module and a driver module. In some examples, the channel driver circuit also includes a sigma-delta module. The differential module receives, via a single node of a load, a channel driving signal that is provided to the load at the single node (e.g., that is based on an electrical characteristic of the load) and generates an analog error signal that is based on the channel driving signal and a reference signal. The driver module is coupled to the differential module and generates the channel driving signal based on the analog error signal or a digital error signal corresponding to the analog error signal and transmits the channel driving signal via the single node to the load. The channel driver circuit simultaneously transmits the channel driving signal to the load at the single node and senses the channel driving signal at the single node.

Abstract: Described herein is an improved apparatus for increasing the performance of a ?? modulator, which may function as an ADC. In one embodiment, the ?? modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the ?? modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.

Abstract: Embodiments may relate to a circuit for use in an analog-to-digital converter (ADC) circuit. The circuit may include a first residue amplifier stage and a second residue amplifier stage. The circuit may further include a synthesized delay stage with a digital-to-analog converter (DAC) electrically positioned between a signal input and the input of the second residue amplifier stage. The circuit may further include a resistor electrically positioned between the signal input and the input of the second residue amplifier stage. Other embodiments may be described or claimed.

Abstract: An apparatus for calibrating an analog-to-digital converter is provided. The apparatus includes a reference input generation circuit configured to subsequently generate two reference inputs for calibrating the analog-to-digital converter. The two reference inputs both represent ramp waveforms, wherein the ramp waveforms represented by the two reference inputs are different from each other. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the analog-to-digital converter to either the reference input generation circuit or to a signal node capable of providing an analog input for digitization.

Abstract: A digital filter and a method for filtering a pulse density modulation (PDM) signal are presented. The digital filter has a first filter circuit to receive an input signal with input values at successive time steps to provide a filtered input signal with filtered values at successive time steps. The digital filter does not require sample-rate or data format conversions. Also, the digital filter is area and power efficient when implemented in hardware. Optionally, the digital filter has a sigma-delta modulator including the quantiser, the sigma-delta modulator being used to receive the filtered input signal and to process the filtered input signal before and/or after being quantised by the quantiser. This digital filter does not require sample-rate or data format conversions. This digital filter is area and power efficient when implemented in hardware.

Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.

Abstract: A voltage-controlled ring oscillator (VCRO) and a VCRO-based sigma delta modulator having capability of enabling and disabling the VCRO cells. A VCRO includes a plurality of inverters coupled in a ring and a transition detector. The transition detector detects a transition of a first inverter and sends a control signal to enable a second inverter if the transition of the first inverter is detected. The transition detector may include a comparator configured to compare an input and an output of an inverter(s) to detect the transition of the first inverter and a latch configured to hold the control signal until it is reset.

Abstract: A new SARADC has two low resolution SAR (Successive Approximation Register) ADCs coupled together by an amplifier to increase the overall resolution and enhance ADC conversion rate. The gain reduction of amplifier is corrected by shifting the digital binary output position. Two SAR ADC outputs are timing aligned and summed to produce final high-resolution high conversion rate ADC output.

Abstract: Described herein are apparatus and methods for low speed characterization of a high-speed signal. A circuit includes a sub-sampling circuit configured to sub-sample a high-speed signal received from a device, a reconstruction loop circuit configured to reconstruct a low-speed signal from the sub-sampled high-speed signal, a low pass filter configured to filter the reconstructed low-speed signal, a discrete time low pass filter configured to mitigate skew rate requirements of the filtered low-speed signal for a digitization circuit, a continuous time low pass filter configured to smooth the skew rate mitigated low-speed signal and the digitization circuit is configured to generate a digital representation of the smoothed low-speed signal for characterization by a characterization device, and shape a noise associated with the smoothed low-speed signal outside a frequency range of interest of the smoothed low-speed signal.

Abstract: A sigma-delta analog-to-digital converter (ADC) is disclosed. The sigma delta ADC has an analog input and a digital output. A sigma-delta modulator input is coupled to the analog input and a sigma-delta modulator output. A first filter having a first filter input is coupled to the sigma-delta modulator output and a first filter output. A second filter having a second filter input is coupled to the sigma-delta modulator output and a second filter output. The sigma-delta ADC operates in a first and second mode. In a first mode, the first filter output is coupled to the digital output. In a second mode, the second filter output is coupled to the digital output.

Abstract: VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.

Abstract: A circuit device includes a time-to-digital conversion circuit, to which a first clock signal generated using a first resonator, and having a first clock frequency, and a second clock signal generated using a second resonator, and having a second clock frequency different from the first clock frequency are input, and which converts time into a digital value using the first and second clock signals, and a PLL circuit adapted to perform phase synchronization between the first and second clock signals.

Abstract: A continuously or step variable passive noise filter for removing noise from a signal received from a DUT added by a test and measurement instrument channel. The noise filter may include, for example, a splitter splits a signal into at least a first split signal and a second split signal. A first path receives the first split signal and includes a variable attenuator and/or a variable delay line which may be set based on the channel response of the DUT which is connected. The variable attenuator and/or the variable delay line may be continuously or stepped variable, as will be discussed in more detail below. A second path is also included to receive the second split signal and a combiner combines a signal from the first path and a signal from the second path into a combined signal.

Abstract: A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value.

Abstract: Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.