Abstract: In some embodiments, a resistor string digital to analog converter (DAC) comprises a first plurality of resistors disposed in a first column. Each of the first plurality of resistors couples to an output of the first column via one of a first plurality of switches. The DAC also comprises a second plurality of resistors disposed in a second column. Each of the second plurality of resistors couples to an output of the second column via one of a second plurality of switches. The second plurality of resistors is configured to couple in series with the first plurality of resistors. A first row selection signal is to control a first switch of the first plurality of switches and a second switch of the second plurality of switches. The first switch corresponds to a first resistor disposed at a top of the first column, and the second switch corresponds to a second resistor disposed at a bottom of the second column.

Abstract: A decision feedback equalizer includes a comparator configured to output a constant voltage in a reset period and to output a differential voltage corresponding to differential input signals in an evaluation period, a latch circuit configured to hold the differential voltage in the evaluation period, and an adjuster configured to adjust a logical threshold of the latch circuit closer to the output voltage in the reset period.

Abstract: A cascaded integrator-comb filter (CIC) that includes a differentiator, a rate changer, an integrator, and a multiplier. The differentiator is configured to differentiate an input signal to produce a differentiated input signal. The rate changer is coupled to the differentiator and is configured to interpolate the differentiated input signal based on an interpolation rate to produce an upsample signal. The integrator is coupled to the rate changer and is configured to integrate the upsample signal to produce an output signal. The multiplier is coupled to the differentiator, rate changer, and integrator and is configured to increase the output signal amplitude based on the interpolation rate.

Abstract: A multiple output, multiple impedance string digital-to-analog converter (DAC) circuit can provide a first output having a first resolution in response to a first digital input signal and a second output having a second resolution in response to a second digital input signal. A main impedance string and a secondary impedance string can be coupled using switching networks to provide a first DAC output. By coupling additional switches to the main impedance string and by sharing the main impedance string, a second DAC output can be realized.

Abstract: In various embodiments of the present invention data is transmitted in light emitted by a light source by generating a continuous-time data signal and generating, based thereon, a drive signal that provides power to the light source, thereby causing the light source to emit light; variations in the amplitude of the drive signal represent information in the continuous-time data signal. A change in average power delivered to the light source as a result of the variations in the amplitude of the drive signal is detected and power to the light source is adjusted to compensate.

Abstract: Embodiments are described of devices and methods for processing a signal using a plurality of vector signal generators (VSGs). A digital signal may be provided to a plurality of signal paths, each of which may process a respective frequency band of the signal, the respective frequency bands having regions of overlap. The gain and phase of each signal path may be adjusted such that continuity of phase and magnitude are preserved through the regions of overlap. The adjustment of gain and phase may be accomplished by a complex multiply with a complex calibration constant. The calibration constant may be determined for each signal path by comparing the gain and phase of one or more calibration tones generated within each region of overlap. Each signal path may comprise a VSG to convert the respective signal to an analog signal, which may be combined to obtain a composite signal.

Abstract: A semi-digital finite impulse response, FIR, filter is configured as a sparse FIR filter and as a minimum phase lag FIR filter. The FIR filter has a delay line composed of a number of sets of delay units sequentially coupled to each other, and where some of the sets of delay units have one or more untapped delay units as part of a cascade of two or more single-sample delay units. An analog summing node is coupled to the taps and produces at its output an analog version of a digital input signal that is fed to an input of the delay line. Other embodiments are also described and claimed.

Abstract: Aspects of the present disclosure include a digital-to-analog converter (DAC). The DAC includes an output node and a plurality of equal sized cell transistors. Each of the plurality of equal sized cell transistors represents a distinct bit, the distinct bits including a least significant bit (LSB). The plurality of equal sized cell transistors are connected to the output node. The DAC includes at least one control circuit configured to modify a back gate voltage of one of the equal sized cell transistors representing the LSB to adjust a current output.

Abstract: Methods and systems are provided for spreading spectral density of pulse streams during digital to analog conversion. An example system may comprise an accumulator circuit, a bit generator circuit, and a feedback circuit. The accumulator circuit may be operable to receive a signal to be spread and generate an output based on the signal to be spread and on one or more inputs generated within the system. The bit generator circuit may be operable to input into the accumulator circuit sequences meeting at least one particular criterion. The feedback circuit may be operable to apply an adjustment to a signal corresponding to an output of the accumulator circuit to generate a feedback signal, and input the feedback signal into the accumulator circuit.

Abstract: A voltage dropping apparatus may include: a voltage dropping unit receiving an input voltage, outputting the input voltage in a first mode, and dropping a level of the input voltage in a second mode; a voltage output unit connected to the voltage dropping unit, receiving and outputting the input voltage in the first mode, and receiving and outputting the dropped voltage in the second mode; and a control unit receiving a mode signal and controlling a mode change of the voltage dropping unit and the voltage output unit based on a value of the mode signal.

Abstract: A device includes at least two digital-to-analog converters, each digital-to-analog converter having a digital-to-analog converter clock modulator, a system reference clock modulator, and a phase detector to track the phases of the clock and the system reference clock. A method of calibrating a phase detector includes providing a pulse waveform, aligning a phase of a digital-to-analog clock to a phase of an internal system reference clock, aligning a phase of a modulated system reference clock with a phase of a modulated, divided, digital-to-analog clock, storing the aligned phase of the modulated system reference clock as a calibration value, synchronizing the digital-to-analog converters and adjusting the phase of the digital-to-analog converters to a center of a desired phase, and storing the aligned phase of the digital-to-analog converters as a calibration value.

Abstract: A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

Abstract: An image processing circuit comprises a first sample-and-hold circuit that samples a first data from a pixel; a second sample-and-hold circuit that samples a second data from the pixel; a voltage-to-current circuit that includes a resistor and a current source, and receives the first data and the second data to output a difference data; and a black sun spot determination circuit. The black sun spot determination circuit compares a first VSL level at a first time with a second VSL level at a second time, both from the second sample-and-hold circuit, and determines the presence of a black sun spot based on a difference between the first and second level.

Abstract: The present disclosure describes aspects of current removal for digital-to-analog converters (DACs). In some aspects, a circuit for converting a digital input to an analog output includes a first resistor ladder having first resistors connectable to respective current sources and connected to a first output of the circuit. The circuit also includes second resistor ladder having second resistors connectable to the respective current sources and connected to a second output of the circuit. A common node is formed between common resistor terminals of the first resistor ladder and the second resistor ladder. Current removal circuitry is connected to the common node and referenced to an amount of current provided by the respective current sources. By removing current from the common node of the resistor ladders, common-mode current at outputs of the circuit can be reduced with minimal degradation of differential performance of the circuit.

Abstract: A scaling apparatus and method for compensating nonlinearity due to the finite output impedance of current sources in current-steering digital-to-analog converters (DACs) are disclosed herein. In an example, a DAC may receive a digital input signal. The DAC may determine an output current weight for each of a plurality of unit cells, based on an output impedance of the unit cell. Further, the DAC may generate an analog output signal by applying the plurality of output current weights to the digital input signal. Then, the DAC may output the analog output signal. The analog output signal may be a high frequency analog output signal, which may be an optical high frequency analog output signal. In an example, a transfer curve of the analog output signal may be linear in terms of analog output signal voltage versus digital input code. The output current weights may include one or more polynomial terms.

Abstract: An image sensor includes a pixel array, a plurality of comparators, a plurality of counters and a plurality of synchronization circuits. The pixel array includes a plurality of pixels configured to generate analog signals by sensing incident light. The comparators generate comparison signals by comparing the analog signals with a reference signal. The counters are grouped into a plurality of counter groups. Each of the counters generates digital signals corresponding to the analog signals by counting, the counting terminated by the comparison signals. Each of the synchronization circuits synchronizes input clock signals to a source clock signal to provide synchronized input clock signals to each of the counter groups.

Abstract: An organic light emitting display apparatus includes first and second pixels on a display region, first and second scan lines connected to the first and second pixels respectively, and a gate driver to output a first scan signal and a second scan signal to the first and second scan lines respectively. The first pixel includes a first pixel circuit and a first organic light emitting diode (OLED). The second pixel includes a second pixel circuit and a second OLED. Each of the first and second pixel circuits includes a driving transistor to output driving current to the anode of a respective one of the first and second OLEDs. The anode of the second OLED at least partially overlaps the gate of a driving transistor of the first pixel circuit.

Abstract: A digital-to-analog convertor for a driving module of a display device is disclosed. The digital-to-analog convertor includes a plurality of switches, forming a tree structure with a plurality of stages for outputting one of a plurality of gamma voltages to an output end according to a plurality of bits of a digital input signal; and a bypass unit, coupled between a first output end of a first switch in the plurality of switches and the output end for adjusting a connection between the first output end and the output end according to a most significant bit in among the plurality of bits and the bits between the most significant bit and a first bit controlling the first switch in among the plurality of bits.

Abstract: Described embodiments provide a radio frequency (RF) amplifier system having at least one amplifier. The at least one amplifier includes an RF input port, an RF output port and a drain bias port. At least one voltage modulator is coupled to the bias port of the least one amplifier to provide a bias voltage. The bias voltage is selected by switching among a plurality of discrete voltages. At least one filter circuit is coupled between the at least one voltage modulator and the at least one amplifier. The at least one filter circuit controls spectral components resultant from transitions in the bias voltage when switching among the plurality of discrete voltages. A controller dynamically adapts at least one setting of the at least one voltage modulator by using multi-pulse transitions when switching among the plurality of discrete voltages for a first operating condition of the RF amplifier.

Abstract: Pulse generation circuitry includes edge generation circuitry and edge combination circuitry. The edge generation circuitry includes a first digital-to-time converter (DTC) configured to input a first phase signal that includes a first phase edge and a second phase signal that includes a second phase edge. The edge generation circuitry is configured to generate a first pulse edge signal comprising a first pulse edge at a selected location between the first phase edge and the second phase edge. The edge combination circuitry is configured to combine the first pulse edge signal and a second pulse edge signal including a second pulse edge to generate a pulse signal.

Abstract: A management system, a smart meter, a server, an operation method and a management method are provided. The management system includes a remote server and at least one smart meter. The smart meter is coupled to the remote server via a communication network. The smart meter measures electrical energy of at least one power line to obtain at least one batch of electricity data. The smart meter detects whether the loading event occurs. If the loading event occurs, the smart meter performs data compression on the electricity data obtained during an event period corresponding to the loading event to obtain compressed data, and uploads the compressed data to the remote server. The remote server performs data decompression on the compressed data to obtain decompressed data. The remote server performs load identification according to the decompressed data.

Abstract: Embodiments of a multi-channel analog to digital converter (ADC) include: a first multiplying digital to analog converter (MDAC) having: first and second switched capacitor circuit paths respectively coupled between first and second input nodes and an input node of a first gain element, a second MDAC having: third and fourth switched capacitor circuit paths respectively coupled between third and fourth input nodes and an input node of a second gain element, a third MDAC having: fifth and sixth switched capacitor circuit paths respectively coupled between a fifth input node and an input node of a third gain element, seventh and eighth switched capacitor circuit paths respectively coupled between a sixth input node and the input node of the third gain element, the fifth input node coupled to an output node of the first gain element, the sixth input node coupled to an output node of the second gain element.

Abstract: In an example embodiment, an apparatus includes: a first sampling capacitor to switchably couple between an input analog voltage, a reference voltage (VREF) and a ground voltage; a second sampling capacitor to switchably couple between the reference voltage and the ground voltage; and a comparator having a first input terminal to couple to the first sampling capacitor and a second input terminal to couple to the second sampling capacitor. The comparator may be configured to compare a voltage level at the second input terminal to a sum voltage based at least in part on the input analog voltage to generate at least one bit of a digital output.

Abstract: Methods an systems for low-power transmission include biasing an emitter in a non-linear operating range of the emitter near a threshold current of the emitter. A data signal is distorted to add a precursor pulse to a rising edge of a data waveform to quickly bring the emitter into a linear operating range. The distorted data signal is transmitted at the emitter.

Abstract: One example includes network physical link (PHY) switch system. The system includes a multiplexer to output a first of a plurality of data streams that are input to a PHY device in response to a first state of a selection signal. The system also includes a data detector that monitors the first data stream and provides a trigger signal in response to a predetermined condition associated with the first data stream. The system further includes a switching controller that provides the selection signal, and in response to a switching command signal indicating a command to switch from the first data stream to the second data stream, monitors the data detector for the trigger signal and changes the selection signal from the first state to a second state in response to receiving the trigger signal to switch to the second data stream of the plurality of data streams.

Abstract: In various embodiments of the present invention data is transmitted in light emitted by a light source by generating a continuous-time data signal and generating, based thereon, a drive signal that provides power to the light source, thereby causing the light source to emit light; variations in the amplitude of the drive signal represent information in the continuous-time data signal. A change in average power delivered to the light source as a result of the variations in the amplitude of the drive signal is detected and power to the light source is adjusted to compensate.

Abstract: Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.

Abstract: Methods and systems are provided for spreading spectral density of pulse streams during digital to analog conversion. An example spreading circuit may comprise an accumulator circuit, a bit generator circuit, a comparator circuit, and an inverter circuit. The accumulator circuit may be operable to receive a signal to be spread and generate an output based on the signal to be spread and at least one other input. The bit generator circuit may be operable to input into the accumulator circuit zero-sum sequences. The comparator circuit may be operable to provide a stream of pulses based on the output of the accumulator circuit. The inverter circuit may be operable to invert output of the comparator circuit, wherein output of the inverter circuit is input into the accumulator circuit.

Abstract: A phase interpolator includes: a digital-to-analog converter to generate bias signals associated with phase signals; a multiplexer having an input interface and an output interface, wherein the digital-to-analog converter is coupled to the input interface of the multiplexer; a first current source; and a second current source; wherein the digital-to-analog converter is configured to provide bleeder current signals to the first current source and the second current source while bypassing the multiplexer.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: An image capturing device includes: an image capturing section having a plurality of pixels disposed in a matrix and configured to output a pixel signal via a first signal line connected to pixels arranged in a first direction among the plurality of pixels; a plurality of calculators including: a comparator configured to compare a magnitude of a first analog signal with a threshold value to generate a digital value according to a comparison result; an amplification section configured to amplify the first analog signal by multiplying the first analog signal by an amplification degree ? (1<?<2) and output a second analog signal by executing computation according to the digital value; and a switching section configured to output one of the pixel signal and a ? estimation signal as the first analog signal when a most significant bit of a first digital value sequence is computed.

Abstract: An image processing circuit includes a first sample-and-hold circuit that samples a first data from a pixel, a second sample-and-hold circuit that samples a second data from the pixel, a voltage-to-current circuit that includes a resistor and a current source and receives the first and second data to output a difference data, an adaptive gain control determination circuit that determines whether a rate of change of a signal from the pixel exceeds a threshold based on an output of the second sample-and-hold circuit, and a current-mode ADC that converts the difference data from an analog form to a digital form.

Abstract: Embodiments relate to an improved segmented resistor digital-to-analog converter (DAC) with resistor recycling. An input digital code word is segmented into M most-significant-bits (MSBs) and N least-significant-bits (LSBs). The DAC includes a MSB resistor ladder coupled with a first set of switches and a LSB resistor ladder coupled with a second set of switches. Based on the decoded bit pattern of the LSBs, embodiments are operable to either switch one or more LSB resistors from the bottom of the MSB resistor ladder up to the top, or to switch the LSB resistors from the top of the MSB resistor ladder down to the bottom. In at least one example embodiment, this technique can avoid redundant resistors in the circuit, which can solve mismatch problems due to redundant resistors in the circuit as in prior art solutions, which can lead to problems relating to non-linearity and non-monotonicity.

Abstract: The present invention provides a method, a device and a system for processing data during idle listening. The method includes: sampling, in an idle listening mode, a first analog signal by using an N-bit ADC, and sampling, in a transceiving mode, a second analog signal by using an M-bit ADC, where N and M are both integers, and N is less than M. Embodiments of the present invention can reduce power consumption of an ADC during idle listening.

Abstract: A digital-to-analog conversion (DAC) circuit has a resistor ladder circuit controlled by high order bits and a resistor string circuit controlled by low order bits. The resistor ladder circuit includes a stem resistor and a branch resistor. The stem resistor has a stem resistance, and the branch resistor has a branch resistance that is substantially equal to two times of the stem resistance. The resistor string circuit includes a string current source, a string resistor, and a bridge resistor. The string current source is configured to generate a string current that is based on a ratio of a reference voltage divided by a predetermined resistance. The string resistor has a string resistance that corresponds to the predetermined resistance, and it is configured to selectively receive the string current based on a selection signal decoded from the low order bits.

Abstract: Various aspects facilitate error reduction for an analog to digital converter (e.g., due to metastability). A digital to analog converter generates a scaled reference voltage based on a reference voltage. A comparator component performs a comparison between an input voltage and the scaled reference voltage based on a defined period of time to perform the comparison.

Abstract: A DAC may include a decoder configured to receive a digital input signal, and first and second sub-DACs coupled in parallel to the decoder, each of the first and second sub-DACs having first and second LSB banks, and an MSB bank coupled between the first and second LSB banks. The decoder may be configured to selectively control the first and second LSB banks, and the MSB bank based upon the digital input signal. The DAC may include an output network coupled to the first and second sub-DACs and configured to generate an analog output signal related to the digital input signal.

Abstract: Embodiments are described of devices and methods for processing a signal using a plurality of vector signal generators (VSGs). A digital signal may be provided to a plurality of signal paths, each of which may process a respective frequency band of the signal, the respective frequency bands having regions of overlap. The gain and phase of each signal path may be adjusted such that continuity of phase and magnitude are preserved through the regions of overlap. The adjustment of gain and phase may be accomplished by a complex multiply with a complex calibration constant. The calibration constant may be determined for each signal path by comparing the gain and phase of one or more calibration tones generated within each region of overlap. Each signal path may comprise a VSG to convert the respective signal to an analog signal, which may be combined to obtain a composite signal.

Abstract: Methods and apparatus for intelligent scheduling of client device tasks based on one or more network scheduling constraints. During normal network operation, a client device performs an array of scheduled maintenance tasks to optimize network performance (e.g., signal strength measurements, etc.) However, during hybrid network operation, regularly scheduled maintenance tasks for a first network can interrupt higher priority tasks on other networks. Consequently, the present invention in one embodiment provides a method for a client device to properly prioritize and re-schedule maintenance tasks. For example, CDMA 1X cell selection (or cell re-selection) procedures have flexible time constraints, and can be postponed (or expedited) to minimize impact on LTE network traffic.

Abstract: A system for transmitting modulation in a narrow band radio frequency channel include a first signal generator configured to modulate a first signal containing data for transmission to provide a primary signal, the primary signal utilizing a higher order modulation technique than would otherwise be permissible if the first signal is transmitted separately. The system further includes a second signal generator, configured to modulate a second signal containing a pulse signal to provide a second signal, wherein the peak signal level of the second signal results in a measurement of the bandwidth of the first signal at a higher signal level and a narrower bandwidth, and a digital signal processor (DSP), which receives and combines the primary signal and the secondary signal and outputs a combined modulated signal for further digital-to-analog conversion, processing and transmission in a radio frequency band.

Abstract: A successive approximation type AD converter includes a charge redistribution type DA conversion circuit, a comparator, and a control circuit. The charge redistribution type DA conversion circuit is configured such that each of k unit elements connects a switch and a unit capacitance in series and includes a unit capacitor array that is connected to a common output line in parallel and a selector that selects one voltage supplied to one input terminal, through m voltage supply lines, among at least three input terminals of switches included in j unit elements which are the targets for dynamic element matching (DEM) in k unit elements based on the DEM.

Abstract: A hybrid polar I-Q transmitter comprises an I-Q quantization circuit configured to receive an in-phase signal and a quadrature signal forming a first I-Q data pair, and generate a quantized in-phase signal and a quantized quadrature signal forming a second I-Q data pair, respectively, based on a resolution information of a digital-to-analog converter (DAC). Each of the first and second I-Q data pairs corresponds to a point in an I-Q constellation diagram comprising an I axis and a Q axis that are orthogonal to one another. The transmitter further comprises a quantization reduction circuit configured to determine a first rotation angle and a second rotation angle of the I-axis and Q-axis, respectively, based on the first I-Q data pair and the second I-Q data pair, and use the determined first rotation angle and the second rotation angle for generating an RF output signal.

Abstract: A D/A conversion circuit includes a plurality of resistors that are formed on a semiconductor substrate and that are connected in series to each other and a plurality of switches that are connected to the plurality of resistors, respectively, in which the plurality of resistors are configured using resistive element and a plurality of contacts that are provided to the resistive element, in which the plurality of switches are arranged side by side along a first direction when the semiconductor substrate is viewed from above, in which distances in the first direction between the plurality of contacts are equal to each other, and in which lengths in a second direction that is perpendicular to the first direction, of the plurality of resistors are unequal to each other.

Abstract: The invention relates to a combined display and input device for a vehicle, wherein a virtual first input unit is provided, which is designed as a touch-sensitive screen for operating a plurality of functions and for displaying information. According to the invention, a physical second input unit is provided, wherein the functions can be selected by means of the first input unit and/or the second input unit, and target values of the functions can be set by means of the first input unit and/or the second input unit, wherein the functions and/or target values can be displayed on the touch-sensitive screen.

Abstract: An IC that performs integer and fractional divisions is disclosed. The IC comprises a plurality of shift registers that forms a shift register ring. Consecutive shift registers are coupled to each other through a multiplexer. The IC also includes a multiplexer controller that determines the shift registers to be activated within the shift register ring. The multiplexer controller determines the activation based upon a divisional factor. The IC also includes a pattern controller that generates the control signal to program the shift register.

Abstract: A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current.

Abstract: A digital to analog converter (DAC) circuit to convert a digital input signal to an analog output signal, wherein the digital input signal comprises a plurality of Least Significant Bits (LSBs) and a plurality of Most Significant Bits (LSBs). The DAC circuit comprises a line decoder configured to receive the plurality of LSBs of the digital input signal and configured to generate line information based thereon. The DAC circuit further comprises a column decoder configured to receive the plurality of MSBs of the digital input signal and configured to generate column information based thereon. Further, the DAC circuit comprises one or more source cells arranged in a plurality of rows and a plurality of columns, wherein the one or more source cells are configured to be selectively activated and consequently generate an individual output signal based on the line information and the column information respectively.

Abstract: This application provides apparatus and methods for a capacitive digital-to-analog converter (CDAC) based power amplifier. In an example, a transmitter amplifier can include an input inductor, a switch having a first node coupled to the input inductor, and a control node, the amplifier configured to receive a first analog representation of an envelope signal at the first node, to receive a second analog representation of the amplitude signal from the inductor, to receive a phase signal at the control node, and to provide a first modulated signal using the phase signal, the first analog representation of the amplitude signal and the second analog representation of the amplitude signal, and a capacitive digital-to-analog converter (CDAC) configured to receive a digital representation of the amplitude signal and to provide the first analog representation of the amplitude signal.

Abstract: An asynchronous sample rate converter and method for converting an input signal to a resampled output signal is disclosed. An efficient and cost-effective sample rate converter for converting an input signal of arbitrary sample rate to a resampled output signal of a second sample rate is disclosed. A hardware-efficient sample-rate converter for resampling an audio input signal with an arbitrary sample rate to an output audio signal with a known sample rate for use in an audio processor is disclosed.

Abstract: The present disclosure includes switched capacitor transmitter circuits and methods. In one embodiment, a digital data signal is thermometer encoded and a negative thermo-encoded signal is bit order reversed to control capacitors in a switched capacitor transmitter circuit. In another embodiment, the present disclosure includes a plurality of switched capacitor transmitter circuits coupled to inputs of an inductive network. The inductive network combines voltages from the switched capacitor transmitter circuits to produce a combined voltage on an output.