Abstract: A headphone driver, a sound processor that incorporates the headphone driver and a computing system that incorporates the headphone driver, wherein the headphone driver includes an amplifier having an input terminal and an output terminal, an R-2R ladder network provided with an input signal and connected to the input terminal of the amplifier, and a feedback resistor group connected to the input terminal and to the output terminal of the amplifier. The R-2R ladder network includes a plurality of resistor branches and a first attenuator that is connected between the plurality of resistor branches.

Abstract: A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

Abstract: In accordance with an embodiment of the present invention, a chip set for a mobile device includes a slave device chip and an interface circuit chip that includes a slave bus interface for controlling the slave device chip through an analog bus. The slave bus interface is coupled to a master bus interface via a digital bus of the mobile device. The slave bus interface is configured to be driven by the master bus interface.

Abstract: In one embodiment, a method for converting an input digital signal into an analog signal is provided. The method comprises modulating the input digital signal into a modulated digital signal, and converting the modulated digital signal into the analog signal using a digital-to-analog converter (DAC). The modulation shapes quantization noise of the DAC to place a notch at a frequency within an out-of-bound frequency band to reduce the quantization noise within the out-of-bound frequency band.

Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with partial constant switching. A digital-to-analog converter (DAC) comprising a plurality of conversion elements may be configured to apply constant switching in only some of the conversion elements. Only conversion elements applying constant switching may incorporate circuitry for providing such the constant switching. Alternatively, each conversion element may incorporate constant switching circuitry and functionality, and the constant switching may then be turned on or off for each conversion element adaptively, such as based on input conditions.

Abstract: The disclosure provides a delta sigma modulator. The delta sigma modulator includes a summer. The summer generates an error signal in response to an input signal and a feedback signal. A loop filter is coupled to the summer and generates a filtered signal in response to the error signal. A quantizer is coupled to the loop filter and generates a quantized output signal in response to the filtered signal. A digital to analog converter (DAC) is coupled to the summer, and generates the feedback signal in response to a plurality of selection signals. A modified data weighted averaging (DWA) block is coupled between the quantizer and the DAC. The modified DWA block receives a clock signal and generates the plurality of selection signals in response to the quantized output signal and a primary coefficient. The primary coefficient varies with the clock signal.

Abstract: A pseudo resistor circuit and a charge amplifier include a first field effect transistor; a second field effect transistor having electrical characteristics matched with electrical characteristics of the first field effect transistor; and a voltage dividing circuit with terminal of a reference resistor electrically connected to a source terminal of the second field effect transistor. Further, a first operational amplifier with an output terminal is connected to a gate terminal of the first field effect transistor and a gate terminal of the second field effect transistor and in which midpoint voltage of the voltage dividing circuit is input into either an inverting or non-inverting input terminal and reference voltage is input into the other of the inverting and non-inverting input terminal. Furthermore, a second operational amplifier supplies voltage resulting from inversion and amplification of drain voltage of the first field effect transistor into the other terminal of the resistor.

Abstract: A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input sample have different signs, comprises generating a first analog signal corresponding to the first input sample using a first subset of the number of cells of the digital to analog conversion circuitry with a local oscillator signal having a first polarity. The method further comprises applying a second local oscillator signal with an inverted polarity to a second subset of cells of the digital to analog conversion circuitry when a number of cells from the first subset of cells are used and selecting a number of cells from the second subset of cells to generate a second analog signal corresponding to the second input sample.

Abstract: A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.

Abstract: Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

Abstract: The invention relates to a receiving unit for performing a calibration of a reference voltage, comprising a reference voltage unit for generating and applying a reference voltage on the evaluation unit depending on a converter value, an evaluation unit for receiving a single-ended data signal and being configured to determine an evaluation signal based on the data signal and the reference voltage, and a logic unit configured to perform a calibration process for calibrating the reference voltage. The logic unit is configured to command a memory device to apply a permanent digital logical state on a data line, to iteratively adapt a converter voltage to substantially match the voltage level of the logical state on the data line, and to determine the reference voltage depending on the converter voltage for which the voltage level of the logical state on the data line has been substantially matched.

Abstract: Techniques are provided for a switched output digital to analog converter employing an N-path cascode output switch. An example system may include a plurality of cascode transistors coupled in parallel to an output stage of a current mode digital to analog converter (DAC) circuit. The system may also include a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors. The system may further include a plurality of output ports, each output port coupled to one of the cascode transistors. The cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor. The cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride.

Abstract: In an example, there is disclosed a multi-stage Digital to Analog Convertor, including: a first stage having a first set of circuit components, a second stage having a second set of circuit components and a third stage having a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths; wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components. A corresponding system and method is also disclosed.

Abstract: A decoder for a current-steering digital-to-analog converter (DAC) is described herein. In an embodiment, the decoder is a dynamic element matching (DEM) row/column decoder that randomizes pairs of row control signals and column control signals that are provided to a matrix of current cells. The randomization is performed in a manner that ensures that the pairs of row control signals are randomized as pairs. In another embodiment, the decoder is an N-dimensional decoder, where N is any integer greater than two. The N-dimensional decoder comprises an N number of decoders that are each configured to provide respective control signals that are provided to current source(s) in current cell(s) in a respective dimension of an N-dimensional matrix of current cells for enabling current source(s) included therein. Such decoders advantageously allow for a simpler, more efficient design compared to a non-segmented, unary DAC due to the smaller area and lower power consumed.

Abstract: In an example, there is disclosed a digital to analog converter (DAC) architecture that in a first aspect provides first and second parallel paths through the DAC so as to allow a separation of a coarse and fine aspect of the DAC transfer function is described. In another aspect a DAC architecture is provided that comprises at an output of the DAC an interpolator arranged to extend the resolution of the overall DAC architecture by interpolating within the voltage range of the DAC stages that precede the interpolator. Such an interpolator can be used with both an amplifier and/or comparator to provide one or more of a buffering of the output and/or a comparison of the DAC output with signals from other circuit elements. Features of the first and second aspects may be used independently of one another.

Abstract: The present invention discloses an electronic device using pulse density modulation for communication, comprising: a pulse density modulation interface; a first circuit to output a clock signal and a data signal through the pulse density modulation interface; and a second circuit to receive the clock and data signals and thereby determine whether the level change times of the data signal reach a predetermined threshold while the clock signal remains unchanged, so as to verify whether the clock and data signals satisfy a start protocol. In an embodiment of the present invention, the above-mentioned predetermined threshold is equal to or more than three.

Abstract: A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source.

Abstract: A method for the design synthesis of an exponential current digital-to-analog (IDAC) using a binary-weighted MSB. The design synthesis involves defining an exponential LSB and exponential MSB current mirrors according to a defined methodology. A method to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a binary-weighted most significant bit (MSB) comprising (1) defining a differential non-linearity (DNL); (2) defining number of LSB bits needed for the targeted DNL with a binary weighted MSB; (3) calculating the number of bits to be used for the binary-weighted MSB to get the desired IDAC base; (4) deriving the minimum current for the Imax; (5) defining the LSB as an exponential current mirror according to the specified relationship for the ILSB; and (6) defining a binary-weighted MSB according to the specified relationship for IMSB.

Abstract: One or more high-order bit linear branches of a segmented DAC are implemented as R-2R networks geometrically down-scaled from the DAC binary portion by a selected factor. The resulting increase in closely-located mismatch is compensated for by implementing a trim circuit at a low-order end of each such linear branch. The trim circuit is designed with a number of trim steps to compensate for the selected linear branch down-scaling factor. Each trim step switches a resistance into the low-order end of the linear branch resulting in an even resistance increment or decrement at the lumped linear branch output. The trim circuit is calibrated to provide an amount of trim at the linear branch output such that the lumped resistance of the trimmed linear branch matches the lumped resistance of the binary portion within a selected tolerance (e.g., generally +/?0.5 LSB).

Abstract: An apparatus for driving a display includes a shift register, a first latch unit, a second latch unit, a data comparison unit and a level select unit. The shift register generates multiple latch signals according to a sync signal. The first latch unit latches a data signal in response to the latch signals to obtain multiple first data corresponding to multiple channels. The second latch unit is coupled to the first latch unit and latches the first data of the channels as multiple second data in response to a latch data signal. The data comparison unit responds to the latch data signal to respectively compare the first data and the second data corresponding to the same channel to output multiple third data corresponding to the channels. The level select unit selects multiple voltage levels corresponding to the channels according to the third data.

Abstract: In an embodiment, a digital-to-analog converter (DAC) converts an input digital signal into an output analog signal, and includes first and second segments, a combiner, and a controller. The first segment includes a first number of first elements that are configured to generate a first analog signal in response to a first portion of the digital signal, and the second segment includes a second number of second elements that are configured to generate a second analog signal in response to a second portion of the digital signal. The combiner is configured to combine the first analog signal and the second analog signal to generate the output analog signal, and the controller is configured to deactivate one of the first elements and to activate one of the second elements in place of the deactivated first element. For example, such a segmented DAC may be suitable for use in a sigma-delta ADC.

Abstract: Embodiments of the disclosed invention address a method, apparatus and computer program product for enabling enhanced transmitter noise shaping. Thereby, a first digital-to-analog conversion is performed on a digital signal resulting in first analog signal, a noise shaping on the digital signal is performed for obtaining a noise shaped signal and performing a second digital-to-analog conversion on the noise shaped signal resulting in a second analog signal, and the first analog signal and the second analog signal are added for obtaining an output signal.

Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.

Abstract: Embodiments of the present invention may provide string DAC architecture with multiple stages for efficient resolution extension. A first stage may include an impedance string (e.g., resistor string). A second stage may include a switch network with each switch having more than two states (impedance values). A third stage may include a string DAC with an impedance string with a set of corresponding switches. In multi-channel embodiments, multiple second and third stages may be provided for each channel while sharing the same first stage (i.e., impedance string). Each second stage switch networks may be controlled based on the relationship between the different channels such as MSB values. Thus, the second stage switch networks may provide different impedance values to compensate for loading effects in multi-channel, multi-stage string DAC designs.

Abstract: An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage inputs and outputs, with the stage inputs of the first scrambling stage connected to the scrambler inputs, the stage outputs of each scrambling stage except the last scrambling stage connected to the stage inputs of a next scrambling stage, and the stage outputs of the last scrambling stage connected to the scrambler outputs.

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. A control loop is provided to control the Ron of the switching network and provide code dependent control of switches in a DAC switching network.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: The perceived sample rate at which a DAC can operate can be increased by allowing multiple DACs to process different portions of a digital signal in parallel. In this way, the outputs of multiple DACs can be combined into a single analog signal to achieve the desired speeds and resolutions of the analog output. This parallel processing can be implemented using a time-interleaving technique or a sub-band reconstruction technique. Pre-distortion can be applied to the digital input signal to compensate for degradation detected in the analog output signal. By applying pre-distortion, waveforms having high sampling rates can be efficiently generated.

Abstract: A digital-to-analog converter includes a first decoder, a second decoder and a voltage summing buffer. The first decoder receives upper bits of a digital signal and upper reference voltages to output an upper voltage corresponding to the upper bits. The second decoder configured to receive lower bits of the digital signal and lower reference voltages to output a lower differential voltage corresponding to the lower bits. The voltage summing buffer generates an output voltage based on the upper voltage and the lower differential voltage, such that the output voltage corresponds to the digital signal including the upper bits and the lower bits.

Abstract: A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.

Abstract: A digital to analog converter includes a first switch, a second switch, and a driver module. The first switch includes a first differential pair of transistors connected to first inputs to receive digital data for conversion to analog data based on a clock signal output by a clock, and first outputs to output the analog data. The second switch includes second and third differential pairs of transistors connected to second inputs and the first outputs. The driver module drives one of the second inputs based on the digital data and toggles the second switch during a first cycle of the clock signal if the first switch is not toggled during the first cycle of the clock signal.

Abstract: Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Abstract: Systems and methods provide for the control of a fully-segmented digital-to-analog converter. The selected lead-most current cell of an array in the digital-to-analog converter is addressed individually using a row/column scheme and a decoder. The remaining current cells behind the lead-most current cell are enabled via a ripple enable signal that propagates backwards from the lead-most current cell. The ripple enable signal snakes through the array to enable all the current cells behind the lead-most current cell in a cell-by-cell fashion. The current cells in front of the lead-most current cell are not enabled.

Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).

Abstract: A display driver maps a selection code (a digital signal) to a reference voltage which is then used to produce a particular intensity of the radiation emitted from a pixel on a display screen (e.g., a LCD display). This mapping may be performed by one or more DACs in the display driver. However, instead of transmitting all of the different possible reference voltages to the DACs, only a subset of the reference voltages are transmitted. Each DAC may include an interpolator circuit that uses the received reference voltages to interpolate the reference voltages that were not transmitted. In this manner, the display driver may still provide the same number of unique reference voltages to a display screen while transmitting fewer reference voltages along the driver's optical channel.

Abstract: A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to ½ of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.

Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/?1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.

Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: A digital to analog converter and a method for controlling a current source array in a digital to analog converter relate to the field of electronics technologies, and are used to reduce a system error. The digital to analog converter includes: a decoding module, a switch array, and a current source array, where the decoding module is configured to generate a 2n?1-bit first temperature code by using high n bits of an input 2n-bit binary digital signal, generate a 2n?1-bit second temperature code by using low n bits of the 2n-bit binary digital signal, and control, by using the 2n?1-bit first temperature code and the 2n?1-bit second temperature code, a working sequence of 2n×2n?1 unit switches.

Abstract: Embodiments of the present invention may provide a multi-string DAC with leakage current cancellation. A leakage cancellation circuit may be coupled to output node(s) of the—multi-string DAC. The leakage cancellation circuit may replicate leakage current present at the coupled output node(s) and generate a corresponding complementary signal, a leakage cancellation signal. The leakage cancellation signal may be injected into the coupled output node(s) to cancel (or reduce) the net impact of the leakage current.

Abstract: Embodiments of the present invention may provide a string DAC with charge boosting. The string DAC may include multiple strings, such as an MSB DAC and an LSB DAC, for converting a digital word into a corresponding analog voltage. The string DAC may also include a charge boost system to couple a charge into or out of the DAC during a code transition, such as a MSB code transition. The string DAC may operate in a break-before-make connection technique where all relevant connections are substantially open-circuited before new connections are made. Therefore, the charge boost may shorten the settling time of impedance elements in the string DAC between code transitions and may substantially reduce (or eliminate) glitches.

Abstract: A digital-to-analog converter for converting digital values to an analog output signal includes a first converter section and a second converter section operating at different conversion rates. A first analog signal provided by the first converter section and a second analog signal provided by the second converter section are combined to obtain the analog output signal. The concept may be used in fields of DAC applications where the sample rate is much higher than the signal bandwidth. The limited signal bandwidth means that the maximum change between two neighboring samples is a small fraction of the whole DAC range. The first converter section may cover a large range of values, whereas for the second converter section a relatively small range of values may be sufficient.

Abstract: Polarity compensating dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a secondary voltage divider of a dual-string DAC includes a switch logic unit. The switch logic unit is configured to compensate for polarity changes in the dual-string DAC to maintain monotonicity. Monotonicity means an output voltage of a DAC either increases or stays constant for monotonically increasing functions or either decreases or stays constant for monotonically decreasing functions given an incremental change in a DAC input code. The switch logic unit is configured to compensate for polarity changes in the input voltage from the primary voltage divider to the secondary resistor string. The switch logic unit is configured to select a secondary switch among the plurality of secondary switches in a secondary voltage divider, to divide an input voltage based on a polarity indicator and a DAC input code, to maintain monotonicity.

Abstract: A system includes an N-bit digital-to-analog converter and an M-bit sub-digital-to-analog converter. The N-bit digital-to-analog converter includes 2N resistances connected in series across first and second reference voltages and converts N most significant bits of B bits of data. The M-bit sub-digital-to-analog converter converts M least significant bits of the B bits of data. The M-bit sub-digital-to-analog converter includes a first converter that converts a voltage across one of the 2N resistances to a first current, a current-mode digital-to-analog converter that interpolates the first current and outputs a second current, and a second converter that converts the second current to an output voltage representing the N most significant bits and the M least significant bits of the B bits of data.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: A digital-to analog-converter (DAC) has a MSB resistor ladder with a plurality of series connected resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential, a LSB resistor ladder with a plurality of series connected resistors, and a plurality of switching units for connecting one of the series connected resistors of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit has a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein each switch is configured form a resistor of similar value of the resistors of the LSB resistor ladder when switched on.

Abstract: An N-bit digital-to-analog converter (DAC) includes N input stages each of which generates the same amount of current and includes a pair of similarly sized transistor switches responsive to differential bits. The 2M?1 input stages associated with the M most significant bits of the DAC are connected in parallel and deliver their currents differentially to the DAC's current summing nodes. Each of the remaining (N?M) stages includes a resistive network that supplies a current defined by a binary weight of the stage's bit position within the DAC. The (N?M) stages deliver their currents to the current summing nodes differentially. The DAC further includes an impedance attenuator adapted to maintain the impedance of the current summing nodes and the voltage difference between the current summing nodes within a range defined by a gain of a differential amplifier disposed in the impedance attenuator.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: Systems and techniques for performing binary divarication digital-to-analog conversion are described. A described converter includes voltage range adjusters arranged in series to convert a digital sequence to an analog representation, each of the adjusters being responsive to a respective bit of the digital sequence, and a combiner. The first adjuster produces first high and low output voltages based on first high and low input voltages and a most significant bit value of the digital sequence. The last adjuster produces last high and low output voltages based on last high and low input voltages and a least significant bit value of the digital sequence. The last high and low input voltages are responsive to the first high and low output voltages as modified by any of zero or more intermediate voltage range adjusters. The combiner produces an analog output signal based on the last high and low output voltages.