Abstract: A D/A converter of switched capacitor type capable of shortening the time for D/A conversion process without increasing power consumption is provided. The D/A converter comprises capacitors Cx and Cy for receiving input voltage corresponding to the digital data and charging the amount of charge corresponding to the input voltage, and an operational amplifier A21 including a first amplified output terminal To1 and a second amplified output terminal To2 for individually outputting amplified signals generated based on a signal inputted to the input terminal. During the conversion process, the amplified signal is outputted from the first amplified output terminal To1, after the conversion process is completed, the amplified signal is outputted through an output switch Sw6 from the first amplified output terminal To2.

Abstract: A return-to-zero current-steering DAC is presented. The presented return-to-zero technique can isolate the analog output nodes of the DAC from the coupling of the control signals of the DAC without sacrificing speed. The topology uses a bank of return-to-zero circuits, which employs return-to-zero and isolation transistors to implement the presented return-to-zero technique.

Abstract: An analog-to-digital converter having a minimal amount of circuitry for conversion of an input analog signal to a series of digital bits. A differential comparator is provided for generating digital values to which the digital bits correspond. A pair of digital-to-analog converters are provided for generating, via successive approximation, a differential feedback analog signal based on bits previously generated by the differential comparator. The analog-to-digital converter compares the differential feedback analog signal to the input analog signal, and based on the comparison generates a digital value that corresponds to a digital bit. In the method of the invention, an analog signal is converted to a digital value using the analog-to-digital converter, and a pair of digital-to-analog converters each generate, via successive approximation, a differential feedback analog signal that is applied to a differential comparator for comparison to the input analog signal being digitized.

Abstract: A digital to analog converter includes first and second capacitors, an operational amplifier and a switching circuit. The operational amplifier includes first and second input terminals and an output terminal, the second input terminal receiving a reference voltage. The switching circuit includes multiple switches which switch in response to corresponding switching signals. The switching circuit connects the second capacitor between the output terminal and the first input terminal of the operational amplifier, while respectively sending first and second voltages to first and second terminals of the first capacitor during a first period. The switching circuit also connects the first capacitor between the output terminal and the first input terminal of the operational amplifier, while respectively sending third and fourth voltages to first and second terminals of the second capacitor during a second period consecutively following the first period.

Abstract: A method of Digital to Analogue conversion of an input signal Do for suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor to a reference voltage value (Vref) during a first phase (?) of a clock signal, discharging the capacitor during a second phase (?2) of the clock signal, wherein the discharge is regulated by a biased transistor, responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitor before the end of the second phase; and providing an output (Ud, OUT) as a function of the discharge current and the input signal Do. The output signal Ud, may be applied as a feedback signal to a loop filter in a Delta-Sigma converter. Alternatively, the output may represent the output of a Class D amplifier.

Abstract: A system having a signal converter device, and a method for operating a system having a signal converter device is disclosed. One embodiment provides loading a capacitive device to a preparation voltage in a first operating phase, and loading the capacitive device to a measuring voltage in a second operating phase after the first operating phase.

Abstract: A cyclic digital to analog converter (CDAC) in a pipeline structure includes a first CDAC block and a second CDAC block. The first CDAC block receives a first digital signal and converts the first digital signal to a first analog value. The first CDAC block includes a charging capacitor for charging according to the first digital signal and a first storing capacitor for storing the first analog value. The second CDAC block receives a second digital signal and converts the second digital signal to a second analog value. The second CDAC block includes the charging capacitor for charging according to the second digital signal and a second storing capacitor for storing the second analog value. The first CDAC block and the second CDAC block share the charging capacitor.

Abstract: A digital-to-analogue conversion arrangement is disclosed which includes first and second groups of the same number of bi-directional bufferless digital-to-analogue converters. The output of at least one converter in each group is connected to a respective capacitive load (CLOAD, CLOAD?). During a calibration phase of operation the converter inputs receive first and second different codes representing the same output level. The arrangement also includes a respective switched capacitor network connected to each converter output, a comparator for comparing the output voltages of the first and second groups, and a control circuit. The control circuit controls the capacitor networks in response to the comparator so as to make the output voltages of the first and second groups substantially equal.

Abstract: In a digital to analogue converter, a plurality of digital inputs are used to select one of first and second binary voltage levels as binary inputs (10) to the converter. A capacitor circuit (C, 2C, . . . , 32C) is associated with each input, and these are controlled to output an effective voltage to an output load comprising the first binary voltage level, the second binary voltage level or an average of the first and second binary voltage levels in dependence on the bits of the digital input word. The plurality of capacitor circuits can be operated in either a voltage divider mode (to provide an average output) or a resistor mode depending on the value of the digital data. Operation of the capacitor circuits in this way can result in a reduction in the currents flowing and can therefore reduce the power consumption.

Abstract: This disclosure relates to systems and methods for analog to digital conversion using delta sigma modulation. To this end, the delta sigma modulator includes a double sampling DAC and integrator and a 1-bit comparator, with reference loading insensitivity.

Abstract: It is an object to provide a method of coding the position information of a digital map in a small data volume by utilizing a compressing and coding technique. In a coding method of coding data indicative of a shape vector on a digital map, an arithmetic processing is carried out over position information about a node string and a shape which indicate the shape vector to be represented by data having a statistical deviation, and the data having the statistical deviation are coded to reduce a data volume. It is possible to considerably decrease a transmission data volume in the case in which the vector shape of the digital map is to be transferred.

Abstract: A digital to analog converter is provided comprising a charge sharing circuit, a discharging circuit and a voltage boosting circuit. The charge sharing circuit sequentially receives first to (N?1)th bits of serial digital signals. The charge sharing circuit shares and stores charges between a first capacitor and a second capacitor according to a charging voltage, a ground voltage, a first clock signal and serial data signals. The discharging circuit discharges the charge sharing circuit according to a reset signal. After the voltage boosting circuit receive the (N?1)th digital signal, the charge boosting circuit whether to boost a first terminal and a second terminal of the second capacitor or not based on an Nth digital signal. After the voltage boosting circuit receives the Nth serial digital signal, the charge sharing circuit outputs an analog signal from the second terminal of the second capacitor.

Abstract: A switched capacitor circuit includes a first level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level. A first waveform generator generates a first predetermined waveform and a second waveform generator generates a second predetermined waveform. A second level-crossing detector generates a second level-crossing detection signal when said second predetermined waveform crosses a voltage reference level a second time. A second switch is coupled to the second level-crossing detector, and a third switch is coupled to the first level-crossing detector. The second switch turns OFF when the second level-crossing detection signal indicates the second predetermined waveform crossed the voltage reference level a second time. The third switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first predetermined level.

Abstract: A system for displaying images is provided. A capacitor type digital-to-analog converter is coupled between a first node and a second node and generates a first analog signal according to a digital signal with N bit data. An analogue buffer is coupled between the second node and a third node and generates a second analog signal according to the first analog signal and a bias voltage. A first switch is coupled between a predetermined voltage and the second node. A second switch is coupled between the first node and the third node. A third switch is coupled between the third node and an analog output signal. The second switch is turned on and the third switch is turned off when the first switch is turned on, and the first and second switches are turned off when the third switch is turned on.

Abstract: A multi-bit digital to analog converter is implemented by a switched-capacitor arrangement in which a reservoir capacitor (Cf) accumulates charge representing the desired analog output signal (Vout+/Vout?). An array of further capacitors (C0-CN) correspond in number at least to the number of data bits (D0-DN) to be converted. The capacitors (Cf, C0-CN) are selectively interconnected with one another and with reference voltage sources (Vmid, Vdd, Vss) in a repetitive sequence of phases including (i) a sampling phase (P2) in which the further capacitors are connected (S3, S4) to reference voltages selected in accordance with the values of the data bits, (ii) an equalization phase (P6a) in which the further capacitors are connected (S2) in parallel with one another without connecting them in parallel with the first capacitor, followed by (iii) a transfer phase (P6b) in which the parallel connected further capacitors are connected (S1, S5) in parallel with the first capacitor.

Abstract: A D/A converter with reduced power consumption is offered by reducing an amount of electric charges that is charged and discharged as D/A conversion is performed. A terminal of each of four capacitors C1, C2, C3 and C4 is connected to a common node. The capacitors C1, C2, C3 and C4 have capacitances C, C, 2C and 4C, respectively. A selection circuit SEL is provided with selection transistors ST1, ST2, ST3, ST4, ST5 and ST6, and selects and outputs either a first reference electric potential V1 or a second electric potential V2 according to a value of each bit of the digital signals D0, D1 and D2. Each of transfer transistors TT1, TT2 and TT3 transfers each of outputs of the selection circuit SEL to another terminal of corresponding each of the capacitors C2, C3 and C4, respectively, in response to a start pulse STP.

Abstract: A digitally controlled analog circuit comprises a finite state machine configured for receiving a digital input word and generating at least two digital codes in a manner determined by a state of the finite state machine. The digital codes are decoded into respective sets of binary data. The sets of binary data control respective switched-circuit arrays to generate an analog output corresponding to the digital input word. To establish a monotonic function between the digital input word and the analog output during steady state operations, the finite state machine switches states when a wrap-around condition is detected for one of the digital codes. The finite state machine uses different sets of equations in different states to derive the digital codes.

Abstract: A system having a signal converter device, and a method for operating a system having a signal converter device is disclosed. One embodiment provides loading a capacitive device to a preparation voltage in a first operating phase, and loading the capacitive device to a measuring voltage in a second operating phase after the first operating phase.

Abstract: This invention provides a digital-analog converter circuit capable of appropriately correcting the optical characteristics of the liquid crystals according to the change in design or the preference of the user, and achieving goals of miniaturization, cost-lowering, as well as wide design suitability. The digital-analog converter circuit includes a storage device for storing a voltage characteristic curve, a modulating device for generating a frequency signal in accordance with a data from the voltage characteristic curve stored in the storage device in response to a selected data, a variable resistance device connected between a first power source and a second power source, in which the resistance value of the variable resistance device is changed in accordance with the frequency signal from the modulating device, a holding device for holding a voltage generated at the variable resistance device, and an output device for outputting the voltage to a desired output end.

Abstract: A sub-A-D converter circuit converts a sampled analog signal into a digital signal of a predetermined number of bits. a D-A converter circuit converts the digital signal converted by the sub-A-D converter circuit into an analog signal to generate a residual signal to be processed by a subsequent conversion processing where the analog signal is to be removed from an analog signal to be sampled by the sub-A-D converter circuit. The D-A converter circuit is of a capacitor array type, and an offset compensation voltage used to compensate for at least part of an offset voltage added to the analog signal sampled by the sub-A-D converter circuit is supplied to at least one capacitor in the capacitor array.

Abstract: A variable gain amplifier for amplifying an input voltage at a gain defined by a binary code includes: a signal input terminal; a signal output terminal; a charge division means that accumulates a charge, divides an accumulated charge, and accumulates a divided charge; a charge cumulation means that accumulates a charge, adds or subtracts an accumulated charge with or from the divided charge in the charge division means, and accumulates a resultant charge; and a controller that initially executes to accumulate the charge corresponding to the input voltage in the charge division means, executes to accumulate the charge corresponding to the input voltage or a predetermined voltage in the charge cumulation means, executes a charge dividing operation according to each bit of the binary code sequentially from a most significant bit, and executes a charge adding or subtracting operation according to an data value in each bit.

Abstract: A digital-to-analog converter (DAC) with a digital segment having a digital data input and an analog segment coupled to the digital segment and having an analog output to output an analog signal corresponding to the digital data. The analog segment includes one or more gain stages and a feedback structure to couple the analog output to the one or more gain stages to attenuate signal distortion at the analog output. A combined gain of the one or more gain stages determines a signal distortion attenuation characteristic of the analog segment.

Abstract: The present patent application comprises a digital to analog converter reference circuit, comprising a capacitor connected to a current source, a positive terminal of the capacitor connected to a first switch, the first switch electrically connecting the positive terminal of the capacitor to a positive input terminal of a DAC circuit, a negative terminal of the capacitor connected to a second switch, the second switch electrically connecting the negative terminal of the capacitor to a negative input terminal of the DAC circuit. In another example, the present patent application comprises a method for converting digital code to an analog signal, comprising charging a reservoir capacitor to a reference voltage level, transferring stored charge from the reservoir capacitor to DAC feedback capacitors, and transferring the stored charge from the DAC feedback capacitors to DAC output terminals.

Abstract: A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n?1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.

Abstract: A fabricated cylinder capacitor having two or more layers is provided, each layer having a bottom plate and top plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor. The layers may comprise five metal layers and may be produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more cylinder capacitors where a set of connectors connect all top plates of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Abstract: An electronic circuit has a voltage selection and output circuit, e.g. digital-to-analog converter (DAC), and a switched capacitor filter (SCF), in which operational conditions of the input side switches of the SCF are incorporated in the selection conditions for selecting respective multiple selection switches of the voltage selection and output circuit. This arrangement permits the selection switches to serve as the input side switches, thereby reducing in number serial switches such as MOS transistors in the circuit, and hence reducing the on-resistances of the serial switches, while preventing the clock feed-through thereof from increasing and suppressing output errors due to the linearity error of the buffer amplifier involved.

Abstract: A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

Abstract: A layered capacitor having top and bottom plates formed from multiple layers. The capacitor has a bottom layer comprising a bottom plate portion and at least one upper layer, each upper layer comprising top and bottom plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a U-shaped bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor device. The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, which may be used in a SAR ADC.

Abstract: For PWM (pulse width modulation), a counter generates a count signal by counting a clock signal 2n times for one period of the count signal. A PWM circuit generates a PWM signal from an n-bit pulse code modulation (PCM) data. The PWM signal includes a first pulse and a second pulse that are symmetric within one period of the count signal for positive and negative values of the n-bit PCM data. A same pulse width for the first and second pulses is determined by a respective value of each bit of the n-bit PCM data excluding the most and least significant bits of the n-bit PCM data.

Abstract: An error canceling comparator based switch capacitor (CBSC) circuit cyclically works through multiple phases including a sampling phase and a transfer phase. During the sampling phase, an input voltage and also an error due to circuit non-idealities are sampled. During the transfer phase, the sampled input voltage is amplified by a fixed ratio and transferred to an output load, while the error is cancelled by reversing the polarity of connection for an internal capacitor within the CBSC circuit.

Abstract: A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Abstract: A digital to analog converter (DAC) comprises X capacitive DACs that are connected together in series, wherein X is an integer greater than one. Each of the X capacitive DACs comprise M switches wherein M is an integer greater than one; a signal input; a signal output; and M capacitances that communicate with the M switches, respectively, and that have first and second ends and substantially equal capacitance values. The M switches selectively connect the first ends of the M capacitances to the signal output. The M switches connect the second end of a selected one of the M capacitances to the signal input. A first DAC has a signal output that communicates with the signal input of one of the X capacitive DACs.

Abstract: A digital-to-analog converter (DAC) comprises a capacitive DAC that comprises N first capacitances that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one, and N first switches that selectively connect a selected one of the second ends of the N first capacitances to a common node and non-selected ones of the second ends of the N first capacitances to one of a voltage potential and a reference potential. Capacitance values of the N first capacitances are substantially equal. A second DAC communicates with the common node.

Abstract: A digital/analog converting apparatus and digital/analog converter are provided. The digital/analog converter includes an operational amplifier, a first filter, a first switch, a second filter, a number of conversion units and a second switch. The operational amplifier has an output terminal, an inverse-phase input terminal and a non-inverse-phase input terminal coupled to a reference voltage. The first filter is coupled between the output terminal and the inverse-phase input terminal. The second filter is coupled between the output terminal via the first switch and the inverse-phase input terminal. Each of the conversion units includes a capacitor. The second switch is coupled between the inverse-phase input terminal and the conversion units, and the conversion units are connected in parallel between the second switch and the output terminal.

Abstract: A cyclic digital to analog converter (CDAC) includes: first and second capacitors C1 and C2; an arrangement of switches selectively controllable to connect C1 and C2 in one of at least two charging-and-sharing configurations, the first configuration having the first capacitor C1 as a charging capacitor CCH and the second capacitor C2 as a sharing capacitor CSH, namely CCH=C1 and CSH=C2, and the second configuration having CCH=C2 and CSH=C1; and a controller to toggle the arrangement of switches between the first and second configurations based upon adjacent bits of a given input word.

Abstract: A digital to analog converter (DAC) includes a first continuous-time stage that receives an input signal associated with a digital signal and performs continuous-time digital-to-analog conversion operations on the input signal. The first continuous-time stage outputs a first output signal. A second switched-capacitor stage receives the first output signal and performs switched-capacitor filtering of the first output signal. The second switched-capacitor stage outputs a second output signal that is sent to a low pass filter to form a continuous analog signal associated with the digital signal.

Abstract: A digital to analog converter includes first and second capacitors, an operational amplifier and a switching circuit. The operational amplifier includes first and second input terminals and an output terminal, the second input terminal receiving a reference voltage. The switching circuit includes multiple switches which switch in response to corresponding switching signals. The switching circuit connects the second capacitor between the output terminal and the first input terminal of the operational amplifier, while respectively sending first and second voltages to first and second terminals of the first capacitor during a first period. The switching circuit also connects the first capacitor between the output terminal and the first input terminal of the operational amplifier, while respectively sending third and fourth voltages to first and second terminals of the second capacitor during a second period consecutively following the first period.

Abstract: A D/A converter of switched capacitor type capable of shortening the time for D/A conversion process without increasing power consumption is provided. The D/A converter comprises capacitors Cx and Cy for receiving input voltage corresponding to the digital data and charging the amount of charge corresponding to the input voltage, and an operational amplifier A21 including a first amplified output terminal To1 and a second amplified output terminal To2 for individually outputting amplified signals generated based on a signal inputted to the input terminal. During the conversion process, the amplified signal is outputted from the first amplified output terminal To1, after the conversion process is completed, the amplified signal is outputted through an output switch Sw6 from the first amplified output terminal To2.

Abstract: The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.

Abstract: A digital capacitor array with individually shielded unit capacitors and combination binary—thermometer coded addressing is disclosed. Such a capacitor array may be part of a digitally controlled oscillator in a MEMS-based frequency reference.

Abstract: A digital-to-analog converter (DAC) for a sigma-delta modulator is provided. The DAC has a switched capacitor structure using an operational amplifier (OP amp) and performs a function exceeding 3-level using a switching method employing only one capacitor in single ended form. Thus, DAC non-linearity caused by capacitor mismatching does not occur, and the number of output levels of the DAC is increased. Also, the DAC capacitor may be applied to a general DAC to increase the ratio of DAC output levels to capacitors.

Abstract: A digital/analogue converter (10) for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and comprises: an array of (n?1) switched capacitors; and a switching arrangement. The switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage (V1) to the first plate of at least one capacitor (Ci) of the array and to connect a second plate of the at least one capacitor to a voltage (V2, V3) that, for at least one value of the input digital code, is different from the first reference voltage (V1) and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor (Ci). The converter may be a bufferless converter having an output for direct connection to a capacitive load.

Abstract: The present invention discloses a digital-to-analog converter (DAC), including a bias voltage generating unit, a digital-to-analog converting stage, and an operating amplifier. The bias voltage generating unit is utilized for generating a first bias voltage. The digital-to-analog converting stage is utilized for converting a digital signal into a voltage signal, the digital-to-analog converting stage includes a current source for providing a current, and a switching unit is coupled to the current source for controlling the current to pass the switching unit according to the digital signal, and a load. The current flows through the load to generate the voltage signal. The operating amplifier is coupled to the bias voltage generating unit and the digital-to-analog converting stage for controlling the current source according to the first bias voltage.

Abstract: A method of Digital to Analogue conversion of an input signal Do for suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor to a reference voltage value (Vref) during a first phase (?) of a clock signal, discharging the capacitor during a second phase (?2) of the clock signal, wherein the discharge is regulated by a biased transistor, responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitor before the end of the second phase; and providing an output (Ud, OUT) as a function of the discharge current and the input signal Do. The output signal Ud, may be applied as a feedback signal to a loop filter in a Delta-Sigma converter. Alternatively, the output may represent the output of a Class D amplifier.

Abstract: A polarization switching digital to analog converter has a ferroelectric capacitor. A number of switches are coupled to the ferroelectric capacitor. A summing circuit is coupled to the one of the switches.

Abstract: A digital-to-analog converter using capacitors and an operational amplifier, which can be highly integrated due to its small area and which can rapidly perform a stable converting operation. The digital-to-analog converter includes a data input unit, a first conversion unit, a second conversion unit, and a signal output unit. When digital data is input to the data input unit, the data input unit is connected to the first conversion unit or the second conversion unit. The first conversion unit charges a first charging capacitor with a voltage corresponding to the input digital data and distributes the charged charges to a first distribution capacitor. The second conversion unit charges a second charging capacitor with the voltage corresponding to the input digital data and distributes the charged charges to a second distribution capacitor.

Abstract: Data of a zeroth bit is supplied via a charge control transistor for the zeroth bit to a corresponding capacitor, data of a first bit is supplied via a charge control transistor for the first bit to a corresponding capacitor, and data of a second bit is supplied via a charge control transistor for the second bit to a corresponding capacitor. The capacitors for the zeroth bit, first bit, and second bit have capacitances which are set in a ratio of 1:2:4 and capabilities of the corresponding charge control transistors for respective bits are set in a ratio of 1:2:4. With this structure, charging of capacitors corresponding to the bits can be performed under similar conditions.

Abstract: A digital-to-analog converter converts a digital input signal into an analog signal. The digital-to-analog converter includes: a power-supply unit for outputting voltages of different magnitudes through plural output terminals thereof; plural switches connected to the plural output terminals, which are controlled on and off, and are for applying the output voltages of the power-supply unit or a ground voltage to a next stage; and plural source transistors connected to the plural switches for outputting currents of magnitudes corresponding to the voltages applied from the respective connected switches of the plural switches. The plural source transistors are designed to have the same operating characteristics, thereby improving glitch characteristics.

Abstract: Embodiments of the invention provide a digital-to-analog converter (DAC) that is configured to process upper data bits, a control data bit, and a lower data bit using two decoders and a control logic. The resulting DAC provides high resolution output using a minimum circuit area. Embodiments of the invention also provide a sample and hold circuit for a DAC that reduces the effects of parasitic capacitance at the input of an operational amplifier (OP-AMP).

Abstract: The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.