Abstract: The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresponding analog voltage corresponding to the variable digital input code. The apparatus also includes an on-chip comparator circuit configured to receive the analog voltage output by the digital-to-analog converter and a test analog voltage as inputs and to provide an output indicating the test analog voltage. Further, the apparatus includes an on-chip logic operative to determine the test analog voltage based on the output of the comparator circuit. A corresponding method is also disclosed.

Abstract: An analog to digital converter (ADC) with interference rejection capability and method thereof are disclosed. The ADC includes a threshold generator, a comparator circuit, a counter and an integrator. By comparing a signal with positive and negative threshold signals from the threshold generator, the comparator circuit converts the signal from analog to digital based on the result of the comparison. The counter counts a percentage of the digital signal and generates a bit signal based on the counted percentage. In response to the bit signal, the integrator supplies a control signal to the threshold generator to regulate the positive and negative threshold signals so as to maintain the counted percentage at a predetermined percentage threshold.

Abstract: In an analog-to-digital conversion method for converting a difference signal component representing a difference between a reference component and a signal component in an analog signal to be processed into digital data, in a first process, a signal corresponding to one of the reference component and the signal component is compared with a reference signal for conversion into the digital data. Concurrently with the comparison, counting is performed in one of a down-count mode and an up-count mode, and a count value at a time of completion of the comparison is held. In a second process, a signal corresponding to the other one of the reference component and the signal component is compared with the reference signal. Concurrently with the comparison, counting is performed in the other one of the down-count mode and the up-count mode, and a count value at a time of completion of the comparison is held.

Abstract: An analog-to-digital converter includes a comparator, a latch, and a bias control unit. The comparator is turned on by an applied bias voltage for comparing an analog voltage with a ramp voltage. The latch activates an end signal when the ramp voltage becomes greater than the analog voltage as indicated by the comparator. The bias control unit uncouples the bias voltage from the comparator when the end signal is activated for reducing power consumption.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: A semiconductor integrated circuit device is provided which has a plurality of photo detector circuits and a plurality of processing elements. Each of the photo detector circuits includes a comparing circuit, which compares an output of a photo detector element with a reference voltage. A/D conversion is performed by counting the elapsed time until the output of the photo detector element drops below the reference voltage, and a level of the reference voltage as a function of time to be applied to the comparing circuit and time intervals of the counting are uniquely determined based on given quantization intervals of an amount of current generated by the photo detector element. In addition, the photo detector elements may be reset locally based on the result of the corresponding processing element.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Abstract: A circuit, method and microcontroller apparatus for performing an analog to digital conversion with continuously variable resolution is disclosed. The circuit includes a integrating modulator for converting an analog input signal, corresponding to an input voltage, to a digital signal at its output over an integrate time. The circuit also includes a counter with an enable input coupled to the integrating modulator output. The counter accumulates the number of cycles where the digital signal is positive during the sample period and provides a corresponding conversion result. Further, the circuit has a pulse width modulator; its output gates a clock to the counter enable input. The pulse width modulator is user programmable on-the-fly to set said integrate time and said sample period.

Abstract: A digital-to-analog converter in which a counter tracks the elapsed time since the beginning of a conversion cycle. Simultaneously, a reference analog signal such as a voltage ramp is generated. When the count reaches a stored digital number value, a sample-and-hold circuit is triggered and acquires the value of the reference analog signal. Multiple stored digital number values can be converted using multiple sample-and-hold and trigger circuits which share the counter and the reference analog signal. Such parallel digital-to-analog conversion is useful in many applications such as digital communications, image display, and shared parallel analog-to-digital conversion.

Abstract: A comparator is arranged to compare a series of analog voltage signal samples on a first capacitor with a voltage on a second capacitor which is linearly increased or decreased to equal the sample value. The comparator's single output freezes the count of the counter at counts which are proportional to the voltage of the respective samples. In this manner, analog to digital conversion can be accomplished using a single line between the analog and digital sides of a circuit, thereby reducing parasitic capacitance.

Abstract: An integrated circuit includes an input pad for receiving an externally generated analog signal, and a pre-sampling circuit for pre-sampling at least one internally generated analog reference signal. An analog-to-digital converter is connected to the input pad for providing a numerical value of the externally generated analog signal, and is connected to the pre-sampling circuit for providing a numerical value of the internally generated analog reference signal. A fault signaling circuit is connected to the pre-sampling circuit and to the analog-to-digital converter for generating a fault signal when the numerical value of the externally generated analog signal is equal to the numerical value of the internally generated analog reference signal. The fault signal indicates that an electrical connection providing the externally generated analog signal to the input pad is faulty.

Abstract: Differential measurements allow correction of fixed-pattern noise errors in digital imaging arrays which use time-to-threshold A/D conversion techniques. Two time-to-threshold measurements are made with the same sensor and threshold-detecting circuitry. The measurements are made in quick succession so that the amount of incident energy is substantially unchanged. However, the two measurements use differing initial sensor output levels or threshold levels. The difference between the two measurements then reflects the time required for each sensor output signal to change by an amount equal to the difference between the initial sensor output values or the threshold values. Repeatable noise terms are cancelled in the computed difference measurement.

Abstract: The invention relates to an analog-to-digital converter (301), comprising several comparators (303) and a reference network, said reference network having several reference elements (302). At least one input (304) of at least one comparator (303) is connected between the individual reference elements (302) of the reference network in the analog-to-digital converter (301), respectively. A digital evaluation circuit (311) with which the statistical evaluation of the output signals generated by the comparators (303) can be carried out is linked to the outputs (309) of the comparators of the analog-to-digital converter (301). The invention also relates to a corresponding method for converting an analog signal (Ua) into a digital signal (D).

Abstract: A rectified analog input signal is compared with a threshold voltage by a voltage comparator, and counting direction of an up/down counter is switched based on the comparison result, and a latch circuit retains an output of the up/down counter, and then an analog-digital converting circuit converts an output of the latch signal into a direct-current voltage. In addition, two input terminals, to which a clock for up-count operation and a clock for down-count operation are independently provided, is provided in the up/down counter, and a timing pulse generating circuit for determining reset timing of the up/down counting circuit and latch timing of the latch circuit is provided.

Abstract: The present invention herein describes a tracking analog-to-digital converter, in particular of the differential input type. In an embodiment thereof the tracking analog-to-digital converter, having a differential analog input including a first analog input and a second analog input, and a digital output at a first number of bits comprising: a back and forth counter having a direction input and an output, with a second number of bits; a digital-to-analog converter having a data input coupled to said output of said converter, a reference input and an output, with a second number of bits; a first comparator having a positive input, a negative input coupled to said output of said digital-to-analog converter and an output coupled to said direction input; characterized in that said reference input is coupled to said first analog input and said positive input of said first comparator is coupled to said second analog input.

Abstract: The present invention relates to a digital control circuit of the P.I. (Proportional Integral) type, receiving an error signal (Error) at an input terminal (IN1) and adapted to provide, at an output terminal (OUT1), a PWM [Pulse Width Modulated] output signal (PWM Output). The circuit is of a type comprising at least one analog-to-digital converter (100, 100*) connected to the input terminal (IN) and to the output terminal (OUT1) through at least one integrative/proportional branch (120, 121, 130, 134). Advantageously in this invention, the analog-to-digital converter (100, 100*) is an integration converter adapted to integrate the error signal (Error) before an analog-to-digital conversion thereof.

Abstract: A dual function superconducting digitizer circuit which can selectively function either as an analog-to-digital converter (ADC) or as a time-to-digital converter (TDC). Superconducting ADCs and TDCs can provide performance far superior to that obtained using conventional electronics by taking advantage of the intrinsic properties—high switching speed, quantum accuracy, dispersion-less transmission lines, radiation hardness, and extremely low power dissipation—of superconductivity. Since both ADC and TDC functions are desired in most measurement systems, a dual-function digitizer is not only more attractive from a system integration perspective but is also more marketable.

Abstract: A method and system for converting a plurality of input signals being indicative of a signal to be converted to a digital output including: setting a plurality of codes each being indicative of a corresponding reference level; and, for each one of the codes, converting the one code to a first analog signal, and summing the first analog signal with a first of the input signals to provide a first summed signal; complementing the one code to provide a complemented code, converting the complemented code to a second analog signal; summing the second analog signal with a second of the input signals to provide a second summed signal corresponding to the first summed signal. The corresponding first and second summed signals are compared to provide a comparison signal. At least a portion of the digital output is set according to the comparison signal.

Abstract: An A/D converter has a successive approximation register having a plurality of A/D registers each corresponding to one of A/D inputs. A capacitor in a comparator is charged by a voltage determined based on a value held in an A/D register corresponding to an A/D input to be A/D converted before starting A/D conversion of the A/D input, thereby reducing noise generated at the time of selecting A/D inputs to enhance A/D conversion accuracy.

Abstract: Monitoring a converter (1) includes detecting whether a value of an input variable (2) for the converter (1) assumes a first prescribed input reference value (41) and checking whether an output variable (3) from the converter (1) likewise assumes a corresponding, second prescribed output reference value (61). This means that the operation of the converter is tested only at occasional instants, specifically only using individual, prescribed values. The fact that only prescribed values (41, 61) are compared with instantaneous values of the input and output variables (2, 3) means that the invention can be implemented using very simple means. The method is particularly suitable for monitoring the operation of a converter (1) in a control or protective device for an electrical switchgear assembly. In this context, when a malfunction in the converter (1) is detected, all protective functions which are dependent on the converter (1) are preferably turned off.

Abstract: A reference voltage generator for use in an image sensor provides a reference voltage to an S/H block during a pixel read-out operation and another reference voltage to an analog-to-digital converter (ADC) during a digitization operation. The reference voltage generator includes a variable voltage generator, a sample-and-hold circuit to sample a reference voltage prior to the pixel read-out operation or the digitization operation, and a buffer amplifier to drive the appropriate reference voltage to the relatively high impedance load presented by the S/H block and the variable impedance load provided by the ADC.

Abstract: A machine used for acquisition of digital images. A counter tracks the elapsed time since the beginning of image acquisition. When an analog sensor output changes by a pre-set amount, the count is stored as the digital number value representing the sensor output. This eliminates the need for a traditional analog-to-digital (A/D) conversion of the sensor output. In an array of sensors, the circuitry of the invention is simple enough to enable massively parallel A/D conversion. The invention can be implemented in an array using a separate counter for each sensor, but it is also possible to reduce costs by sharing counters among the sensors.

Abstract: An A/D converter including a counter for counting a clock signal to output a digital signal corresponding to an analog input signal; a D/A converter for converting the output signal of the counter into an analog signal; a comparator for comparing the analog input signal with the output signal of the D/A converter to control the counter in accordance with the comparison result; and a clock supply circuit for supplying the counter with the clock signal, wherein the frequency of the clock signal is changed in accordance with a difference signal exhibiting the difference between the analog input signal and the output signal of the D/A converter.

Abstract: The present invention herein describes a tracking analog-to-digital converter, in particular of the differential input type.

Abstract: A method for controlling an analog/digital converter circuitry includes generating a digital signal by accumulating a predetermined increment at a predetermined time interval in accordance with a value of a first analog signal input to the analog/digital converter. The digital signal is converted to a second analog signal, the second analog signal is subtracted from the first analog signal, and a detection signal is generated in accordance with a subtraction result. An accumulation mode is selected from accumulation modes in accordance with the detection signal and accumulation is performed at the time interval and in the increment in accordance with the selected accumulation mode.

Abstract: An impedance control circuit designed to match the impedance between a semiconductor device and a transmission medium (PCB) by using a current source installed in the semiconductor device instead of using an external resistor is provided. Since the impedance control circuit does not use an external resistor for impedance matching, the PCB size can be reduced. In particular, a controllable current source matches the impedance more precisely compared to the external resistor.

Abstract: A successive-approximation analog-digital converter including a logic control circuit timed by means of an external clock signal clock. The logic control circuit includes a register containing a first digital signal formed of N bits, which is the product of a first analog-digital conversion. The logic control circuit is suitable for producing a second digital signal formed of N bits through a second analog-digital conversion in N clock cycles. This analog-digital converter converts the second digital signal sent by the logic circuit to a second analog signal. A comparator compares the first analog signal with the second analog signal which has been input to the analog-digital converter.

Abstract: According to an embodiment of the present invention, an input signal is provided to an oscillator, which creates a count signal with a greater frequency than the input signal. The input signal triggers the oscillator to oscillate depending on the value of the input signal. The oscillator output is provided to a counter, which counts the number of oscillations undergone by the oscillator during a single period of the input signal or a number of periods of the input signal, whichever is desired. Since the oscillator frequency is greater than the frequency of the input signal, the oscillator effectively acts like a clock to time the input signal; the counter effectively acts to record the ‘time’ measured by the oscillator (clock). More formally, the counter generates a count value based upon the width of the input signal pulses. The counter output is provided to a decoder, which interprets the count generated by the counter.

Abstract: The invention relates to a tracking analog to digital converter that includes a comparator circuit for comparing an analog input signal with an analog reference signal. The comparator circuit emits a comparator output signal and an evaluation circuit is provided for evaluating the comparator output signal. The analog to digital converter includes a counter unit with an adjustable counter increment for emitting a digital counter value. The analog to digital converter also includes a digital to analog converter for converting the digital counter value into the analog reference signal. The evaluation circuit adjusts the counter increment in accordance with the evaluated comparator output signal.

Abstract: An A/D converter including a counter for counting a clock signal to output a digital signal corresponding to an analog input signal; a D/A converter for converting the output signal of the counter into an analog signal; a comparator for comparing the analog input signal with the output signal of the D/A converter to control the counter in accordance with the comparison result; and a clock supply circuit for supplying the counter with the clock signal, wherein the frequency of the clock signal is changed in accordance with a difference signal exhibiting the difference between the analog input signal and the output signal of the D/A converter.

Abstract: An apparatus for time-multiplexing a thermal sensor includes a digital-to-analog converter. The digital-to-analog converter provides an output to a comparator. The thermal sensor also provides an output to the comparator. A sequencer selects one of several input values to be applied to the digital-to-analog converter input. The sequencer further selects one of several latching devices to latch the output of the comparator. Once the result of the compare operation between the output of the thermal diode and the output of the digital-to-analog converter is latched, then the sequencer selects another one of the several input values and also selects another one of the several latching devices and another comparison is made between the output of the digital-to-analog converter and the output of the thermal sensor. The sequencer continues to select from among the several input values and corresponding latching devices in a rotating fashion.

Abstract: An A/D converter has been described that compares the bounds of a voltage window with an analog input signal Vin. When Vin is not within the boundaries of the voltage window, the position of the voltage window is moved either upwards or downwards depending on the disposition of the analog input signal. The position of the voltage window is sequentially moved until either the analog signal Vin is within the bounds of the window or the absolute upper or lower position limits are reached.

Abstract: A highly efficient analog-to-digital (A/D) converter circuit that converts an external analog signal sequentially generated from an external analog signal source into an n-bit digital data signal (n is an integer equal to or more than two) includes a digital-to-analog (D/A) converter circuit that converts an n-bit digital data signal into an analog signal and outputting the analog signal from a first output terminal, a comparator that compares a signal level of an external analog signal supplied from an external device with a signal level of the analog signal outputted from the first output terminal, and a digital integrator circuit that digitally integrates a 1-bit digital data signal outputted from the comparator and thereby producing an n-bit digital data signal.

Abstract: A digital-to-analog converter 41, capable of setting a voltage V41 of an offset value using information JS. At the time of an offset correction operation, the voltage V41 of the offset signal is sequentially varied to automatically set it to a value that is extremely close to a lower executable conversion limit Vbottom within the convertible range of the analog-to-digital converter. With this structure it is possible to provide a sensor circuit that is capable of preventing lowered precision with temperature variations.

Abstract: An analog-to-digital converter is provided. The analog-to-digital converter capable of increasing the processing speed of the converter by using a number of SAR registers.

Abstract: An analog comparator compares an analog signal to be converted with an analog ramp signal. The output of the comparator enables a digital latch having a binary Gray code counter input. When the analog ramp equals the analog signal, the digital latch captures the state of the Gray code counter. Metastability in the digital latch is resolved by a latch train. The Gray coded output is then decoded by a Gray decoder to a standard binary output. An array of converters are constructed on a monolithic integrated circuit where each converter shares a single analog ramp generator, binary Gray code counter and Gray decoder. A multiplexer selects a particular converter and switches the standard binary output from the selected converter to line drivers to be used off-chip. The two least significant bits of the Gray code are generated with phase shifting circuits.

Abstract: A clock signal is frequency divide to generate a plurality of signals CK, CK′ having different periods, and a plurality of the control signals C, TZS are generated from them. One of the control signals C, TZS is selected as control signal TZ1, depending on the comparison section T1-T4, so as to change the period of the control signal for each comparison section. The reference voltage and the input voltage are compared according to the control signal TZ1. The period of the control signal is made shorter at the comparison sections other than the section T2 which requires a longer comparison time for the stabilization of the reference voltage, due to the large difference of the former reference voltage and the present reference voltage.

Abstract: An integrated circuit includes a variable bit-depth successive approximation analog-to-digital converter. The variable bit-depth successive approximation analog-to-digital converter can select from at least two clock signals of different frequencies to drive the variable bit-depth successive approximation converter for each bit depth application. Within each bit-depth application, the converter may employ more than one clock frequency.

Abstract: The subject invention relates to a type of multi-bits successive-approximation ADC to convert analog signals into a N-bits digital output code, wherein N is the number of bits of output code. The ADC includes (a) an input sample/hold circuit that takes the sample of analog input signals during the first half of clock cycle, and maintains the analog input signals after the sampling and during a conversion process. The ADC also includes (b) a reference voltage generator, to produce different reference voltages, (c) CLOCK pulse generation circuitry to continuously produce CLOCK pulse signals, (d) several comparators for comparison of the sampled input signals with a rough reference voltage to produce a rough digital output code. The ADC applies a temperature scale to roughly estimate the sampled analog input signals, this to be completed in a second half of the CLOCK cycle.

Abstract: Embodiments of the invention include a method and apparatus for determining values for data reproduced or retrieved from data storage media such as in holographic memory systems. The method includes initially approximating the value of data members retrieved initially from the data storage medium of interest (e.g., by their intensity levels based on an absolute scale), using those approximations collectively to establish one or more threshold levels for defining ranges for the data values to be determined, and determining values for the retrieved data members by comparing the initial data value approximations of the retrieved data members to the established threshold levels. Alternatively, the threshold level(s) are set initially and adjusted iteratively based on the initial approximations of the individual data members until a final established threshold level is established.

Abstract: A tracking analog-to-digital converter (ADC) which incorporates an input device, such as a superlattice, which produces a pulsating output current corresponding to the voltage level of an analog input voltage and an encoding device to provides a unique digital code which can be read to yield an approximation of the analog input voltage level. By simultaneously tracking the analog input voltage, the device operates at higher speeds than previously attainable. The resolution of the new ADC is increased by composing the input device to respond to narrow voltage ranges. When the input device is a superlattice, narrow response ranges are accomplished by composing the superlattice to have an increased number of resonances or by vertically stacking a plurality of superlattices.

Abstract: An analog to digital converter includes a comparator, an up/down counter and a pulse width modulator. The analog input to the comparator initially causes the counter to count up. The counter output is the converted digital word. The word is used to vary the modulation duty cycle of the modulator output which is compared with the analog input to the comparator. When the modulator output exceeds the analog input, the comparator output changes and the counter counts down, maintaining a digital output from the counter at the value of the converted analog signal.

Abstract: A low cost, easily manufactured analog to digital converter uses MOS switching technology easily combined on an integrated circuit with other signal processing circuitry. An input capacitor stores an input analog voltage, and a pumping capacitor is switchably connected to the input capacitor to charge or discharge that input capacitor to a reference value. The number of charge or discharge events is used to generate a digital value for the input analog voltage.

Abstract: A system is provided for digitizing the setting of a potentiometer of the type used in an analog joystick for computer games. The analog output of the potentiometer is applied to one of two inputs of a voltage comparator. When a readout of the joystick position is desired, a "write" input is applied to a counter to permit it to commence counting at a predetermined frequency from an initial or zero count. The digital outputs of the counter are coupled to the inputs of a digital-to-analog converter, the output of which is coupled to the second input of the voltage comparator. When the count in the counter produces a voltage at the output of the digital-to-analog converter corresponding to the voltage setting of the potentiometer, the comparator provides an output signal. The time delay from the time the write pulse occurs until this signal is obtained is representative of the potentiometer setting.

Abstract: An A/D converter includes a three-state comparator for detecting a higher state, a lower state and a equal state of a sampled analog signal with respect to a sequence of reference signals which are supplied from a counter or register after D/A conversion. After the equal state is detected, the D/A converter and the three-state comparator are stopped for power saving. The A/D converter further includes a frame memory and a control section which provide the counter or register with an initial code for each conversion cycle based on the last code of the previous conversion cycle constituting the previous digital output of the A/D converter. The A/D converter well follows the sequential change of the input level between the conversion cycles.

Abstract: A successive approximation A/D having dual comparators for allowing a larger range of analog input signals to be converted into digital form. One comparator is an N-channel device, and the other comparator is a P-channel device. The A/D switches to either the N-channel device or the P-channel device based upon whether the first two comparisons the determine the most-significant bit and the next-most significant bit are a "11", in which the N-channel device is selected, or anything else, in which the P-channel device is selected. Switching circuitry is included to output the proper comparator based on these two comparisons.Control circuitry is also provided to allow for successive conversions using only a single address read.

Abstract: In an analog/digital converting circuit, when an analog input voltage exceeds a reference voltage, the analog input voltage is modified into analog voltages not exceeding the reference voltage, and comparison voltages generated by dividing the reference voltage are compared with the modified analog voltages.

Abstract: A successive approximation circuit and method are disclosed for digitally approximating a moving signal using an analog-digital converter (ADC) and a comparator for generating a comparison signal from the moving signal. An estimate register and a bit and conversion control circuit are provided, with the bit and conversion control circuit including a bit control circuit and a conversion control circuit, where the bit control circuit adjusts a current plurality of output bits to compensate for an error due to a slew rate to generate the digitally approximated moving signal. An adder is included for adding the control value to the current plurality of output bits to generate the next plurality of output bits. Alternatively, an adjustment selection circuit and a logic chain circuit are included.

Abstract: A low-power delta modulator analog-to-digital converter is provided that is suitable for use in a cardiac stimulating device for monitoring intracardial signals. The delta modulator consumes less power than previously available delta modulators because portions of the delta modulator circuitry are shut down when the signal to be digitized is not rapidly varying. The device uses slow clock pulses for sampling the input signal and subsequently digitizes the sampled signal using a faster clock. After a sampled signal has been digitized, the result is held until the next slow clock pulse. Power consumption is reduced since the delta modulator does not draw substantial amounts of power during this holding period. Further, the output of the delta modulator reflects the magnitude of the change in the analog input, with a separate bit for representing direction.

Abstract: A receive signal strength indication analog-to-digital converter includes a digital portion and an analog portion. The digital portion includes structure for approximating radio frequency receive signal strength in digital form and a state machine implementing a successive approximation algorithm. The analog portion includes a digital-to-analog converter, an analog comparator, and structure for transmitting the output of the digital-to-analog converter to the analog comparator. The receive signal strength indication analog-to-digital converter also includes structure for transmitting the approximate radio frequency receive signal strength in digital form to the digital-to-analog converter and structure for transmitting the output of the comparator to the state machine.