Abstract: Systems and methods are provided for low-power asynchronous data links. A receiver may obtain from signals, received from a transmitter over low-power asynchronous links, recovery information embedded into the signals at the transmitter, and may determine based on the recovery information, control parameters that may be used in configuring a control signal applied during processing of the signals. The signals may be processed based on the control signal, with the processing comprising extraction of data embedded in the signals at the transmitter. The transmitter may generate, based on an input datastream, signals configured for transmission to the receiver, over low-power asynchronous data links, and may embed into the signals, the recovery information that enables determining, at the receiver, parameters relating to the signals and/or to the generating of the signals. The control parameters may comprise parameters relating to the signals and/or processing of the signals at the transmitter.

Abstract: A data communication device is provided. The data communication device includes a data array configured to receive pieces of data, register cells, each register cell of the registers cells being configured to be activated based on a respective one of the pieces of data, and an outputter configured to output information corresponding to a register cell that is activated among the register cells.

Abstract: In one implementation, an apparatus estimates body core temperature from an infrared measurement of an external source point using a cubic relationship between the body core temperature and the measurement of an external source point is described, estimates temperature from a digital infrared sensor and determines vital signs from a solid-state image transducer, or determines vital signs from a solid-state image transducer and estimates body core temperature from an infrared measurement of an external source point using a cubic relationship between the body core temperature and the measurement of an external source point; after which the estimated and/or determined information is transmitted to an external database.

Abstract: In one implementation, an apparatus estimates body core temperature from an infrared measurement of an external source point using a cubic relationship between the body core temperature and the measurement of an external source point is described, estimates temperature from a digital infrared sensor and determines vital signs from a solid-state image transducer, or determines vital signs from a solid-state image transducer and estimates body core temperature from an infrared measurement of an external source point using a cubic relationship between the body core temperature and the measurement of an external source point; after which the estimated and/or determined information is transmitted to an external database.

Abstract: The proposed technology generally relates the field of data transmission, in particular it relates to decoding an encoded data signal received at an audio interface of a portable electronic device, wherein the encoded data signal is encoded with an encoding scheme having an adjustable encoder clock frequency. The proposed method comprises pre-processing the received encoded data signal; scanning the received encoded data signal for a known start sequence and when a known start sequence is successfully detected then calculating an actual frequency based on the detected start sequence; interpreting, a data block succeeding the start sequence using the assessed actual frequency; and assessing whether to request adjustment of the adjustable encoder clock frequency based on the scanning and/or the interpretation. The proposed technology relates to a method performed in a portable communications device well as a corresponding device and computer program.

Abstract: A coded light receiver comprising a sensor for receiving coded light, a filter, and a timing and data recovery module. The coded light comprises a signal whereby data and timing are modulated into the light according to a self-clocking coding scheme. The filter is arranged to match a template waveform of the coding scheme against the received signal, thereby generating a pattern of filtered waveforms each corresponding to a respective portion of the data, and the timing and data recovery module recovers the timing from the signal based on characteristic points of the filtered waveforms. The timing and data recovery module is configured to do this by separating the filtered waveforms into different sub-patterns in dependence on the data, and to recover the timing by processing each of the sub-patterns individually based on the characteristic points of each sub-pattern.

Abstract: A network device includes a communication interface and a transmitter coupled to the communication interface. The transmitter is configured to determine to start an auto-negotiation page with a link partner, and transmit, through the communication interface, a start delimiter for the auto-negotiation page. The transmitter transmits the start delimiter by transmitting a first pulse comprising a first encoding violation, followed by a second pulse comprising a second encoding violation. The transmitter may shorten the first pulse and the second pulse relative to a different pre-defined start delimiter to define spectral content for the first pulse and the second pulse that passes different first and second receiver filters in the link partner for different first and second communication standards.

Abstract: The invention relates to a safety system comprising a safety unit having an output and a safety input, a bus line and at least one safety related participant. The bus line and the safety related participant form a test signal path having a forward path and a return path. The safety related participant comprises an interconnection module with a test signal input and a test signal output and a protective device integrated in the test signal path by means of the interconnection module. The protective device comprises two switches which are respectively connected to the interconnection module via a forward line and a return line of the interconnection line for the formation of a first and a second electric switching path. The interconnection module comprises a test circuit for the two switching paths with a controlled current source, a controlled current sink and a current direction element.

Abstract: In a decoding device for a Manchester-encoded signal, at least one moving data average and/or one moving clock average is/are formed relative to mutually differing average times using moving-type averaging units, and from these moving average values, binary output signals are made available as data signal and/or clock signal with the aid of comparators.

Abstract: The effect of timing inaccuracy is compensated for in a communication receiver that receives a transmission of bits temporally separated by a bit interval. The compensation employs an oversampling clock whose frequency defines a sampling interval that is smaller than the bit interval, which bit interval is nominally a predetermined integer multiple of the sampling interval. The oversampling clock samples the received transmission to produce an incoming sample stream. The incoming sample stream is decoded by a plurality of different decoding operations to produce, respectively, a plurality of decoded sample streams. It is determined whether the received transmission is decodable from any of the decoded sample streams.

Abstract: A method for demodulating at least one received frame is provided, where the frame includes of a succession of bits coded according to a Manchester code. The method includes the steps of: generating an interruption at least at each appearance of a rising and/or falling edge of the frame of coded bits; determining the time between each interruption from at least one first counter; reinitializing the demodulation of the frame as soon as one of the determined times is less than a first predetermined value or greater than a second predetermined value, the first and second predetermined values being dependent on the duration of a bit coded according to the code; and demodulating, for each determined time, if the determined time is greater than the first predetermined value and is less than the second predetermined value, at least one binary value of the frame from the determined time.

Abstract: In a decoding device for a Manchester-encoded signal, at least one moving data average and/or one moving clock average is/are formed relative to mutually differing average times using moving-type averaging units, and from these moving average values, binary output signals are made available as data signal and/or clock signal with the aid of comparators.

Abstract: In a decoding device for a Manchester-encoded signal, at least one moving data average and/or one moving clock average is/are formed relative to mutually differing average times using moving-type averaging units, and from these moving average values, binary output signals are made available as data signal and/or clock signal with the aid of comparators.

Abstract: A coding method, a decoding method, a coder, and a decoder are disclosed herein. A coding method includes: obtaining the pulse distribution, on a track, of the pulses to be encoded on the track; determining a distribution identifier for identifying the pulse distribution according to the pulse distribution; and generating a coding index that includes the distribution identifier. A decoding method includes: receiving a coding index; obtaining a distribution identifier from the coding index, wherein the distribution identifier is configured to identify the pulse distribution, on a track, of the pulses to be encoded on the track; determining the pulse distribution, on a track, of all the pulses to be encoded on the track according to the distribution identifier; and reconstructing the pulse order on the track according to the pulse distribution.

Abstract: A data processing apparatus that is capable of reducing the garbling of characters caused by the difference among the character codes when setting data are transferred to another apparatus by the import-export function. A storage unit stores setting data for the data processing apparatus. A receiving unit receives an instruction for exporting the setting data stored in the storage unit. A converting unit converts Unicode data included in the setting data into character code data of language, which is set to the data processing apparatus. An export unit exports the character code data converted by the converting unit and the Unicode data.

Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.

Abstract: In a data carrier (1) which includes receiving means (5) for receiving a modulated carrier signal (MTS) which contains a data signal (DS1) encoded in conformity with an encoding method (MA, PW, MI, RTZ, FSK, PSK), demodulation means (9) for demodulating the received modulated carrier signal (MTS) and for outputting the encoded data signal (DS1) contained therein, decoding means (10, 20) for decoding the encoded data signal (DS1) and for outputting data (D1, D2), and data processing means (11) for processing the data (D1, D2) output by the decoding means (10, 20), the decoding means (10, 20) are provided with at least a first decoding stage (12) and a second decoding stage (13), the first decoding stage (12) being arranged to decode a data signal (DS1) encoded in conformity with a first method (RTZ) whereas the second decoding stage (13) is arranged to decode a data signal (DS1) encoded in conformity with a second method (MI).

Abstract: Disclosed are a Multiple User Multiple Input Multiple Output (MU-MIMO) codebook design method, and a communication device using the codebook. A MU-MIMO codebook design method includes analyzing beam patterns of candidate vectors included in a predetermined candidate codebook, and eliminating at least one of the candidate vectors based on the beam patterns of the candidate vectors to generate the MU-MIMO codebook for a MU-MIMO system being comprised of the remaining vectors.

Abstract: In a control unit for passenger protection and a method for triggering passenger protection devices, a Manchester-coded signal is supplied by an interface and the Manchester-coded signal is decoded by a coding unit, so that an analyzer unit performs the triggering of passenger protection devices as a function of the decoded signal. The decoding unit uses a shift register structure for decoding and oversampling for the Manchester-coded signal.

Abstract: There is provided an information processing apparatus, including a signal receiver that receives a signal encoded in such a way that a signal containing a first bit value and a second bit value, wherein the first bit value is represented by first amplitude values, the second value is represented by a second amplitude value, and polarity of the encoded signal amplitude value is reversed in each period, a conversion processor performs conversion to add a delayed signal that is delayed by delaying a signal received by the signal receiver by one period of the received signal, an inversion processor that performs inverse processing of the conversion on the signal output from the conversion processor, and an input data decoder that decodes an input data by determining the first and second values based on the amplitude value of the signal output from the inversion processor.

Abstract: Biphase mark codes (BMC) are used in digital communications. Most BMC formats use preambles for rate determination and synchronization. A decoder compares the intervals of continuous high or continuous low voltages in a BMC stream to predetermined minimum and maximum values of half cell, full cell and one-and-a-half cell intervals for all supported sampling rates. If a pattern matching a preamble is found, the sampling rate is locked in and the decoder is synchronized to the BMC stream. Once locked, the decoder uses the predetermined minimum and maximum values at the locked rate to generate half cell, full cell and one-and-a-half cell indicators for a decoding state machine which decodes data in the BMC stream or decodes expected preambles.

Abstract: A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.

Abstract: Information that includes first information identifying integer quotients obtained by divisions using prediction residuals or integers not smaller than 0 that increase monotonically with increases in the amplitude of the prediction residuals, as dividends, and a separation parameter decided for a time segment corresponding to the prediction residuals or a mapped integer value of the separation parameter, as a modulus, and second information identifying the remainders obtained when the dividends are divided by the modulus is generated as a code corresponding to the prediction residuals, and each piece of side information that includes the separation parameter is subjected to variable length coding.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: A decoding method for biphase-encoded data is provided. The decoding method includes detecting falling-edge transitions in the biphase-encoded data to decode according to a time difference (?t) between each two adjacent falling-edge transitions and the logic value of previous bit. When ?t is 1 bit period and previous bit is logic 1, it's determined that present bit is logic 1. When ?t is 1 bit period and previous bit is logic 0, it's determined that present bit is logic 0. When ?t is 1.5 bit periods and previous bit is logic 1, it's determined that present and next bits are both logic 0. When ?t is 1.5 bit periods and previous bit is logic 0, it's determined that present bit is logic 1. When ?t is 2 bit periods and previous bit is logic 1, it's determined that present and next bits are logic 0 and 1 respectively.

Abstract: The present invention discloses a transmitted/received data decoding method and apparatus, which achieve effects of decoding performance improvement and synchronous detection. The decoding method includes setting a coded edge pattern, and filtering a received data by using the set coded edge pattern as a window; respectively computing absolute values of filtered values filtered by using the coded edge pattern windows; detecting a maximum absolute value from the computed absolute values; determining a sign (+/?) for the detected maximum absolute value; outputting an intermediate bit value of the corresponding original data as a resultant decoded value according to the determined sign and a window type (i.e. coded edge patter) with the selected maximum absolute value.

Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.

Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.

Abstract: This application relates to decoding signals that carry clock and data information. In particular, it relates to construction a time-varying histogram of inter-arrival times between pulse edges and using the histogram to identify whether a pulse edge encodes a single length interval, a double length interval or some longer length interval. Further details and embodiments of the technology disclosed are provided in the drawings, detailed description and claims.

Abstract: An information processing device is provided that includes a signal receiving portion, an absolute value conversion portion, and an input data decoding portion. The signal receiving portion receives a signal that is encoded such that mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the first and second bit values also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle. The absolute value conversion portion converts into absolute values the amplitude values of the signal that has been received by the signal receiving portion. The input data decoding portion decodes the first and second bit values based on the amplitude values in the signal that have been converted into absolute values by the absolute value conversion portion.

Abstract: A coding method, a decoding method, a coder, and a decoder are disclosed herein. A coding method includes: obtaining the pulse distribution, on a track, of the pulses to be encoded on the track; determining a distribution identifier for identifying the pulse distribution according to the pulse distribution; and generating a coding index that includes the distribution identifier. A decoding method includes: receiving a coding index; obtaining a distribution identifier from the coding index, wherein the distribution identifier is configured to identify the pulse distribution, on a track, of the pulses to be encoded on the track; determining the pulse distribution, on a track, of all the pulses to be encoded on the track according to the distribution identifier; and reconstructing the pulse order on the track according to the pulse distribution.

Abstract: A signal encoding apparatus and method of a radio frequency identification (RFID) reader capable of removing a high frequency component without using a digital filter, and performing Manchester encoding by using two symbols. The signal encoding apparatus of the RFID reader including an encoding unit that stores a first symbol and a second symbol; transmits the first symbol if data received after an initial state is zero (0), and returns to the initial state; delays for a given time period if the data received after the initial state is one (1); transmits the second symbol if data received after the delayed given time period is zero (0), and returns to the initial state; and transmits the first symbol if the data received after the delayed given time period is one (1), and stands by.

Abstract: The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments.

Abstract: Disclosed herein are one or more embodiments that facilitate compression of a source file having a fixed-length record therein. One or more of the disclosed embodiments detect the fixed-length records and determine a reordering plan for the source file, including determining a plurality of column groupings within the detected fixed-length records.

Abstract: Digital data encoding and decoding method and system is provided. The data encoding includes encoding a frame signal into a bit stream, including detecting a specific bit pattern in the bit stream when the frame signal is present, generating a control signal in respect to the specific bit pattern, and encoding the bit stream into one or more marks and one or more spaces so that encoded data include a unique encoding pattern for the frame signal. The data decoding includes detecting at least one of mark and space from encoded data, recovering a bit stream from the encoded data when the at least one of mark and space is present, detecting a specific bit pattern associating with a frame signal from the encoded data when the at least one of mark and space is present, and recovering the frame signal from the encoded data.

Abstract: A galvanic isolator having a transmitting section and a receiving section is disclosed. The transmitting section includes a frame input circuit, a data encoder, and a data transmitter. The frame input circuit receives an input data frame that includes a plurality of input binary bits. The data encoder encodes the input binary bits to generate an encoded data frame that includes a sequence of encoded binary bits in which two successive encoded binary bits represent each input binary bit. The successive encoded binary bits representing a 1 are 01 or 10, and the successive encoded binary bits representing a 0 are 00 or 11. The sequences are chosen to maximize the number of transitions in the encoded data frame. A data receiver recovers the encoded data frame by examining successive pairs of encoded data bits using a clock that is reset on the edges in the encoded data frame.

Abstract: The present invention discloses a transmitted/received data decoding method and apparatus, which achieve effects of decoding performance improvement and synchronous detection. The decoding method includes setting a coded edge pattern, and filtering a received data by using the set coded edge pattern as a window; respectively computing absolute values of filtered values filtered by using the coded edge pattern windows; detecting a maximum absolute value from the computed absolute values; determining a sign (+/?) for the detected maximum absolute value; outputting an intermediate bit value of the corresponding original data as a resultant decoded value according to the determined sign and a window type (i.e. coded edge patter) with the selected maximum absolute value.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: An ASK modulator for reducing the difference in the On/Off ratio due to the difference in the envelope frequency components without deteriorating an adjacent wave leakage power is disclosed. The ASK modulator includes a Manchester encoder that generates Manchester-encoded signals by applying Manchester encoding to an input signal sequence, a waveform shaping unit that generates band-limited encoded signals from the Manchester-encoded signals, and detects and limits minimum values of waveforms of the band-limited encoded signals to generates shaped signals, and a modulating unit that modulates carrier waves based on the shaped signals.

Abstract: A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a plurality of threshold values after the each increment of the UI number, where each threshold value is associated with at least one of a plurality of sum values. For each threshold value, once exceeded by the UI number, its sum value is incremented for each cycle of the clock signal, and a plurality of window lengths are calculated, where each window is calculated based at least in part on at least one of the sum values at predetermined values of the UI number.

Abstract: An encoding apparatus that converts input digital data and an input clock into three-bit six-state transition encode outputs and outputs them is disclosed. The encoding apparatus has a first state transition control section, second state transition control section, and an output selection section. The first state transition control section changes a state of first data at a positive edge of the input clock. The second state transition control section changes a state of second data at a negative edge of the input clock. The output selection section alternately selects the state of the first state transition control section and the second state transition control section.

Abstract: A signal encoding apparatus and method of a radio frequency identification (RFID) reader capable of removing a high frequency component without using a digital filter, and performing Manchester encoding by using two symbols. The signal encoding apparatus of the RFID reader including an encoding unit that stores a first symbol and a second symbol; transmits the first symbol if data received after an initial state is zero (0), and returns to the initial state; delays for a given time period if the data received after the initial state is one (1); transmits the second symbol if data received after the delayed given time period is zero (0), and returns to the initial state; and transmits the first symbol if the data received after the delayed given time period is one (1), and stands by.

Abstract: A system, method, and computer program product are provided for estimating a clock signal. Specifically, during use, a clock signal associated with an audio signal is digitally estimated.

Abstract: A decoding apparatus is disclosed. The decoding apparatus is applied to a data signal comprising a plurality of bits. A plurality of sampled data is generated by sampling the data signal. Each of the bits has a same cycle. The decoding apparatus comprises a calculating module and a determining module. When the calculating module sets a first interval and a second interval in the cycle of a specific bit, the calculating module generates a first count according to the sampled data in the first interval corresponding to a first logic level and generates a second count according to the sampled data in the second interval corresponding to a second logic level. The determining module determines a digital logic value of the specific bit.

Abstract: A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter is incremented for each UI received upon receipt of a valid UI, and the value of the UI counter is compared to a plurality of threshold values after the UI counter is incremented. When the value of the UI counter exceeds each of the threshold values, for each clock cycle, a sum counter is incremented corresponding to the exceeded threshold value, and a plurality of window lengths are calculated, where each window is calculated based at least in part on the value of one of the sum counters at predetermined values of the UI counter.

Abstract: A decoding apparatus is disclosed. The decoding apparatus is applied to a data signal comprising a plurality of bits. A plurality of sampled data is generated by sampling the data signal. Each of the bits has a same cycle. The decoding apparatus comprises a calculating module and a determining module. When the calculating module sets a first interval and a second interval in the cycle of a specific bit, the calculating module generates a first count according to the sampled data in the first interval corresponding to a first logic level and generates a second count according to the sampled data in the second interval corresponding to a second logic level. The determining module determines a digital logic value of the specific bit.

Abstract: The invention provides a memory code generator. In one embodiment, the memory code generator comprises a code memory, a preparation buffer set, and a correlation buffer set. The code memory stores code data. The preparation buffer set retrieves a first code segment of the code data from the code memory, and shifts the first code segment to obtain a second code segment with a desired code phase required by the correlation buffer set. The correlation buffer set loads the second code segment from the preparation buffer set, and provides a correlation code for correlation according to the second code segment. The preparation buffer set prepares the second code segment corresponding to a subsequent correlation when the correlation buffer set is providing the correlation code for a current correlation according to the first code segment.

Abstract: Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.

Abstract: A method and circuit are shown for decoding a Manchester encoded data input signal, wherein preamble found, data input, and recovered clock signals are received and a phase of the data input signal stored responsive thereto. A decision time signal alternates state responsive to the recovered clock signal. A switch pulse signal asserts when the decision time signal is active and the stored phase and current phase of the data signal have the same logic value, which is stored and cleared responsive to the recovered clock signal. A data output is decoded from a decision pair of phases responsive to the recovered clock, preamble found and decision time signals. The stored and current phases of the data input signal are selected to be the decision pair when neither the switch pulse signal or stored switch pulse signal are asserted and, otherwise, the stored phase and inverted stored phase are selected.

Abstract: A method and circuit are shown for decoding a Manchester encoded data input signal, wherein preamble found, data input, and recovered clock signals are received and a phase of the data input signal stored responsive thereto. A decision time signal alternates state responsive to the recovered clock signal. A switch pulse signal asserts when the decision time signal is active and the stored phase and current phase of the data signal have the same logic value, which is stored and cleared responsive to the recovered clock signal. A data output is decoded from a decision pair of phases responsive to the recovered clock, preamble found and decision time signals. The stored and current phases of the data input signal are selected to be the decision pair when neither the switch pulse signal or stored switch pulse signal are asserted and, otherwise, the stored phase and inverted stored phase are selected.