Abstract: A receiving device is provided. A pulse width is measured, it is selected whether a determination process is performed for a pulse width having the length of one bit in accordance with the measured value of the pulse width or a pulse width having the length of ½ bit, it is discriminated whether a current pulse edge is a pulse edge at the center of the bit or a pulse edge at the boundary between bits while considering the bit data right before the determined bit, and when it is determined that the current pulse edge is the pulse edge at the center of the bit, the bit data is determined by the rising edge or the falling edge of the pulse edge.

Abstract: Encoding and/or decoding a wideband signal produces high frequency band spectra from low frequency band spectral information. Linear prediction filter coefficients are determined for the entire wideband spectrum of an input signal. An energy value in each of a plurality of sub-bands in the high frequency band is determined and encoded. The short-term correlation removed input signal is then down-sampled to form a low frequency band signal. At a decoder, the high frequency band signal is generated using the encoded low frequency band signal. The energy in each sub-band of the high frequency band is adjusted using the encoded energy value. Thus, the spectral envelope for the entire wideband signal is synthesized and decoded using linear predictive synthesis.

Abstract: Method, system and computer program product for replacing a portion of a digital signal by applying a first difference correction that, after range limiting, converts the samples in the replacement portion to extremum values; then applying a second difference correction based on the difference between the extremum values and the desired replacement values. The first and second sets of correction values are thus independent of the original values in the first digital signal.

Abstract: A system and method for decoding a received data stream is disclosed. The method includes detecting first and second data transitions of a received data stream. Each of the data transitions is of a first transition type (e.g. rising or falling transition). The time interval between the data transitions is measured, and a logic value of a data bit encoded in the data stream is decoded based on the measured time interval. By decoding the data stream based on the time intervals between data transitions, the number of decoding errors due to timing changes in the data stream (such as changes due to drift or jitter in the data stream) is reduced.

Abstract: A receiving device is provided. A pulse width is measured, it is selected whether a determination process is performed for a pulse width having the length of one bit in accordance with the measured value of the pulse width or a pulse width having the length of ½ bit, it is discriminated whether a current pulse edge is a pulse edge at the center of the bit or a pulse edge at the boundary between bits while considering the bit data right before the determined bit, and when it is determined that the current pulse edge is the pulse edge at the center of the bit, the bit data is determined by the rising edge or the falling edge of the pulse edge.

Abstract: A method and apparatus for data encoding such as 3 to 4 encoding (base64, uuencode etc.) is provided. Bytes of data to be encoded having negative values are made positive while preserving the information to be encoded. The positive values may be manipulated by addition (e.g. to a common store) and bit shifting to efficiently obtain encoded data such as by indexing an encoding alphabet.

Abstract: A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream.

Abstract: A method and a corresponding decoder for decoding a Manchester encoded binary data signal includes receiving the Manchester encoded binary data signal having a first sequence of central bit transitions and a second sequence of initial bit transitions. A local clock signal is generated, and the central bit transitions of the Manchester encoded binary data signal are determined. Determination of the central bit transitions includes measuring the time interval elapsing between a pair adjacent central bit transitions, expressed as a number N of cycles of the local clock signal, and selecting each successive central bit transition based upon the time interval N measured between the pair of central bit transitions which immediately precede the successive central bit transition.

Abstract: A receiver for a data communication system which comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream based on the samples.

Abstract: An encoder circuit and a related method for its operation, in which digital encoding, such as differential phase-shift keyed (DPSK) encoding, is performed as a parallel operation on N bits at a time. Each encoded bit is both output in parallel with the others of the N bits and is coupled as an input to encode the immediately next bit in the input data stream. The Nth encoded bit is fed back to the first encoder stage for use in encoding the (N+1)th bit in the input stream. The encoder typically includes a serial-to-parallel converter at the encoder inputs, and a parallel-to-serial converter at the encoder outputs.

Abstract: A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger to separate “ones” and “zeros” one-shots. The equalized Manchester data signal is also integrated, compared with a threshold value to determine the negative and positive peaks of the data signal. Then after the appropriate peak is determined, a mid-bit signal is sent as input to a set-reset flip-flop which thereby outputs an asynchronous recovered non-return to zero signal. This asynchronous recovered non-return to zero signal then provides an enable input to the “ones” one-shot and the complementary asynchronous recovered non-return to zero signal provides an enable input to the “zeros” one-shot. The “ones” one-shot outputs a “ones” clock signal and the “zeros” one-shot outputs a “zeros” clock signal. These two signals are verified and a recovered clock out signal is provided.

Abstract: A method and apparatus for accurately decoding a Manchester data stream having transition time distortion and noise spikes. Briefly, in an embodiment using a protocol where a falling edge at the mid-point of a bit represents a “1” bit and a rising edge at the mid-point represents a “0” bit, the coded data can be accurately determined by comparing the time period tp1 from the start of the bit to the first falling edge and the time period tp2 from the last rising edge to the end point of the bit. If tp1 is less than tp2, the bit represents a bit value of “0” and if tp2 is less than tp1, the bit represents a bit value of “1”.

Abstract: An S/P converter 120 converts input data from serial to parallel for every two bits in different timings, thereby outputting two types of parallel data. Based on the input data, a timing detector 130 detects a timing which corresponds to boundaries between bits of a data portion before biphase encoding. Based on the detection result of the timing detector, a selector 140 selects either one of the two types of parallel data output from the S/P converter 120.

Abstract: A pulse decoder for decoding digitally coded data, each data bit being represented by a coding scheme consisting of a combination of short and long duration pulses having a predetermined interrelationship. The decoder has an input for receiving an input signal defining respective long and short time periods derived from the digitally coded data. An analog signal processing element generates output pulses from the input signal. The output pulses have a variable duty cycle dependent on the input signal and a control parameter. A feedback loop generates a control signal for adjusting the control parameter so that the duty cycle of the output signal matches the predetermined relationship.

Abstract: A method and associated structures for coding a sequence of data bytes (BY1,BY2), in which two bits (B1, B2) of a data byte form a double bit (D1-D4). Each double bit is represented by a time slot frame (ZR1-ZR4) that has at least four time slots (ZS1-ZS4). The time slots can assume an on or off value (Z1, Z0). The coding is carried out in a time slot frame such that at least one time slot is preloaded with an off value (Z0) at a position (AF). The time slots that have not been preloaded have, at most, one time slot with an on-value in order to form a logic value (00, 01, 10, 11) of a double bit. The method can be used for identification systems (IS), for mobile data memories (DT) and for reader/writers (SLG). Therein, a higher data rate and/or a greater transmission distance between the reader/writer and the mobile data memory is achieved.

Abstract: There is provided a digital image encoding device which can enhance image compression performance while maintaining an image quality. When coefficient bits are decomposed/aligned in four encoded paths for each context by a procedure called coefficient bit modeling of a JPEG 2000 encoding system, if an appearance frequency of “1” is low in subbit plane coefficients of a clean-up path of a low-order bit plane n (bit plane n is lower in order than bit plane np represented by threshold value np), coefficients of subbit planes of this clean-up path are all reset to “0.” Thus, a run length used when a symbol and a context are generated is made longer and, as a result, the amount of codes after arithmetic encoding at a subsequent stage is reduced while an image quality deterioration is suppressed.

Abstract: A method and system for decoding a biphase-mark input stream is disclosed. Aspects of the present invention include receiving an external biphase-mark input stream by a receiver module; recovering timing information from the input stream; decoding the input stream to generate decoded data and storing the decoded data in a data buffer; reading, by an audio out module, the decoded data from the data buffer at a rate determined by a programmable clock; using the timing information from the receiver module to calculate a sampling frequency of the input stream; and adjusting a frequency of the programmable clock to substantially match the sampling frequency so that the audio out module reads the decoded from the buffer at substantially the same rate that the receiver module inputs the decoded data into the data buffer.

Abstract: Two or more digital signals are encoded using two or more respective line codes. The line codes are chosen in conjunction with the data rates of the digital signals such that the encoded signals are substantially orthogonal to each other in the frequency domain. As such, the two or more encoded signals may be combined and transmitted via a single physical medium with little or no interference. A transmitter for encoding and transmitting the digital signals contains line coders for encoding the digital signals and a combiner for combining the encoded signals for transmission via a single physical medium. A receiver for receiving and decoding the combined encoded signal contains filters for extracting the individual encoded signals and line decoders for decoding the individual encoded signals to generate the original digital data signals.

Abstract: Methods and systems for processing data are disclosed. An exemplary system for parsing and modifying data stored in an array of storage elements includes a parsing system configured to access the data stored in selected storage elements of the array of storage elements and output the data in one of a plurality of register formats and a write system configured to write data to selected storage elements of the array of storage elements, wherein the data is received in one of the plurality of register formats. The plurality of register formats includes a first set of register formats corresponding to a packed representation of the data and a second set of register formats corresponding to an unpacked representation of the data.

Abstract: A method and apparatus for a state-driven decoder for decoding a Manchester encoded signal. The decoder comprises an input sampling stage, an over-sampling clock, and a digital logic state machine. The over-sampling clock operates at a frequency which is less than five times the data rate of the encoded signal. The input sampling stage asynchronously samples the encoded signal at the frequency of the over-sampling clock and a produces a stream of pulse samples. The digital logic state machine analyzes the stream of pulse samples in groups and based on the logic levels of each group of pulse samples generates an output bit corresponding to the decoded Manchester signal.

Abstract: A pulse decoder for decoding digitally coded data, each data bit being represented by a coding scheme consisting of a combination of short and long duration pulses having a predetermined interrelationship. The decoder has an input for receiving an input signal defining respective long and short time periods derived from the digitally coded data. An analog signal processing element generates output pulses from the input signal. The output pulses have a variable duty cycle dependent on the input signal and a control parameter. A feedback loop generates a control signal for adjusting the control parameter so that the duty cycle of the output signal matches the predetermined relationship.

Abstract: Sampling data with wide bi-phase code symbols includes sampling a wide bi-phase code symbol in the data a number (N) of times to produce samples of data, selecting a subset of the samples, determining which sample in the subset of samples has a largest magnitude, and selecting a subset of samples in a subsequent wide bi-phase code symbol based on a sample in a previous subset that has the largest magnitude.

Abstract: The invention relates to a method for the sampling of biphase coded digital signals by reception means which have at least one signal input having switchable signal edge sensitivity or at least two signal inputs having different signal edge sensitivity for the reception of such signals. The signals to be received are sampled precisely once per data bit, namely during the transmission of the first half-bit. The signal edges (F1-F5) of each bit are utilized for synchronizing the signal input with the control signal and for detecting transmission errors. Each signal sampling (S1-S5) is followed by a time window (&Dgr;t) within which the reception of the signal edge of the present bit is expected and evaluated as permissible. The signal edge sensitivity of the at least one signal input is set as a function of the sampled logic level of the first half-bit of the respectively transmitted bit of the signal.

Abstract: In a Manchester encoded data decoder a clock component is extracted from input data inputted at a prescribed rate, the extracted clock component is taken as input and transition points are extracted from the signal waveform of the filter output, a clock signal of the same rate as the input data and which is in synchronism with the phase of the extracted transition points is generated, a data component is extracted from the input data, results of comparing the extracted data component and a prescribed value are outputted as a binary level signal; and the binary level signal, taken in using the clock signal, is outputted as NRZ encoded data corresponding to the input data.

Abstract: Apparatus, and an accompanying method, for transmitting a frame synchronization signal and a data signal simultaneously through a serial transmission medium (170). Specifically within a data transmitter (105), a frame synchronization signal, a clock signal and a data signal, are encoded to form a single bi-phase mark signal that is defined by a specific modulation protocol and the frame synchronization signal is incorporated into the bi-phase mark signal as a protocal violation. The bi-phase mark signal is then transmitted through a suitable serial transmission medium. A receiver (175), connected to the transmission medium, receives and amplifies an incoming bi-phase mark signal appearing on the medium, and, in turn, synthesizes the clock, frame synchronization, and data signals from this bi-phase mark signal.

Abstract: A circuit for switching digital signals on a plurality of signal lines where signals on different signals line may have different signal rates includes a controller that prevents a switch from being turned off until after another switch is stably turned ON. This allows more than one switch at a time to supply a correspondingly received digital signal to an output. Substantially identical digital signals may be supplied to two inputs of such a circuit while the circuit is switched between the respective inputs. The circuit may be driven by an encoder that supplies encoded signals without recursion but that conforms to encoding conventionally supplied by recursion. The encoder may be implemented in parallel configuration for rapid encoding of a signal, and may be implanted to perform a data strobe signal encoding conforming to IEEE standard 1394.

Abstract: An encoder which includes a flip-flop; a first, second and third NAND gate; a first and second inverter; and a first and second delay cell. The first inverter couples the flip-flop with the first NAND gate. The first delay cell couples the first NAND gate with the third NAND gate. The second inverter couples the second delay cell with the second NAND gate. Further, the second NAND gate couples the second inverter with the third NAND gate. The third NAND gate of the encoder produces a glitch-free encoded signal.

Abstract: A line-driver receives as an input a Manchester-encoded digital data signal, which is then converted into an analog signal by a wave-shaping circuit. The wave-shaping circuit comprises a bank of current sources with a combined output, each current source being actuated by a switch controlled by a switching signal. The current sources are each scaled by a coefficient, and are actuated in a selected sequence during each input data pulse, thereby generating as a combined output a staircase pulse signal with n steps for each input data pulse.

Abstract: Various modem designs are described, along with systems that use the modem designs for communicating data between a large number of remote locations and one or more central locations preferably over CATV. One aspect features a modem having a transmitter which uses a state machine and digital waveform signals stored in a memory to create a modulated signal. Another aspect features a modem having a receiver which uses a digital correlator including an SRAM for detecting a bipolar phase shift keyed signal. Still another aspect features a modem comprising an oscillator circuit having a feedback loop, wherein the feedback loop utilizes a downlink signal, and a protection circuit which prevents a malfunction in the modem from causing system-wide shutdown.

Abstract: The method and associated apparatus of the present invention decodes digital signals by appropriately weighting the respective noise portions of the two phase segments generated by the detector, such as an APD in an optical communications system, such that the digital signal can be reliably decoded despite the presence of multiplicative noise induced by the detector. The detector detects a digitally encoded communications carrier signal having a waveform defining first and second portions. The detector then generates an electrical signal in response to the digitally encoded communications carrier signal. The electrical signal has two phase segments, namely, one phase segment corresponding to the first portion of the digitally encoded communications carrier signal and another phase segment corresponding to the second portion of the digitally encoded communications carrier signal. Each phase segment also includes a respective noise portion.

Abstract: A device including a mechanism (4) for generating a counting clock signal (CKM) whose frequency is less than or equal to n times twice the transmission frequency. The device also includes a detection mechanism (10) for detecting the transitions (TD) of the signal (DS) at the counting frequency and for delivering corresponding detection signals (ST), a selection mechanism (2) for receiving each detection signal (ST) and for delivering or otherwise a selection signal (RS) depending on the satisfying or otherwise of a predetermined selection criterion, and a frequency divider-by-n (30) which receives the counting clock signal, in order to sample the carrier signal after a predetermined time delay (Tr) after each detected transition. Provided are a sampling control device and method which are completely digital and therefore use no analog component of the phase-locked loop type and are very simple to produce at an industrially economical cost.

Abstract: An encoding system including an encoder that Manchester encodes a data value to produce a coded data value and produces a first invalid Manchester encoded sequence as a start of frame. Also produced is a second invalid Manchester encoded sequence as an end of frame. A transmission packet is produced including the start of frame followed by the coded data value followed by the end of frame. The start of frame is a sequence of "110110" and the end of frame is a sequence of "001000".

Abstract: According to a broad aspect of the invention, an apparatus (34) for decoding a Manchester encoded data stream is provided. The apparatus includes a transition detector (45) for receiving the Manchester encoded data stream to produce a transition indicating output when a transition of the Manchester encoded data stream is detected. Also, a circuit (105) is provided to generate an output control pulse a predetermined time after the transition indicating output is produced. A sampling flip-flop (120) receives the Manchester encoded data stream, and is controlled by the output control pulse to output a state of the Manchester encoded data to an output control circuit (125) when the output control pulse is generated. In a preferred embodiment, the sampling flip-flop (125) operates to generate a binary NRZ form of the Manchester encoded data stream.

Abstract: A delay-locked loop which phase-locks the reference clock of crystal oscillation by certain identical delay units for generating certain precise time-sharing phase signals. These time-sharing phase signals can be utilized to recover the clock/data. The advantages of the invention, when comparing with the typical phase-locked loop, are: (1) it can be easily stabilized; (2) the phase error does not accumulate; (3) the loop filter requires only one capacitor, which reduces the area of chip; (4) no additional loop filter is need in multiport application, which further reduces the area of chip.

Abstract: A phased array antenna system having an array of antenna elements coupled to radio frequency energy feed network through a plurality of phase shifter sections with digital control data being fed to the phase shifter sections with radio frequency energy signal modulated with the digital control data. A modulator is fed by the source of the radio frequency energy and a modulating signal to produce the modulated radio frequency energy signal. A modulating signal generator/encoder, fed by the digital control data, encodes each bit of such digital control data into the modulating signal, such modulating signal being a bipolar signal having a pair of electrical signal changes corresponding to a binary state represented by such bit. The modulated radio frequency energy signal may be fed to the demodulator through the radio frequency feed network or through the antenna element coupled thereto.

Abstract: A horizontal period counter 3 determines one bit period of bi-phase codes by measuring the period of a horizontal scan line immediately preceding one containing bi-phase codes to be decoded. An edge pulse generator 6 generates edge pulses at rising and falling edges of inputted bi-phase codes. A compensating pulse generator 7 is triggered by the edge pulse and generates a compensating pulse in a predetermined period, which is shorter than one bit period of the bi-phase codes and longer than one half bit period, according to one bit period that has been determined. A rise judging circuit 11 generates sampling pulses by superimposing compensating pulses on the edge pulses. The bi-phase codes are decoded according to the sampling pulses.

Abstract: A clock encoding circuit, e.g., for Manchester encoding, for high speed data transmission (IEEE 1394) and a circuit for controlling data and encoded clock transmission. The clock encoding circuit includes two parallel to serial shift registers, a DATA register and a STROBE register, receiving data in parallel and shifted out at 100 MHz, 200 MHz or 400 MHz. The STROBE register receives every other bit of the data inverted. When both registers are clocked at the data transmission rate, data is shifted out of DATA register and the transmission clock is encoded in STROBE, shifted out of the STROBE register. Bit inversion may be with invertors receiving data as it is passed to the DATA register, or alternatively, after it is loaded into the DATA register. The circuit for controlling DATA and STROBE transmission includes the clock encoding circuit, a frequency matching register array and a loopback shift register.

Abstract: A method and an apparatus are disclosed for recording a binary signal onto a magnetic record carrier. The binary signal is supplied to an input terminal. The apparatus comprise generators for generating at least two write pulses (P.sub.1,P.sub.2) for each bit of the binary signal to be written. More specifically, the generators are adapted to(i) generate at least two write pulses of a third polarity for the first bit of the first polarity in the first sequence,(ii) generating a write pulse of the third polarity and a write pulse of a fourth polarity for the at least second bit of the first polarity occurring in the first sequence, the third polarity being opposite to the fourth polarity,(iii) generating at least two write pulses of the fourth polarity for the first bit of the second polarity in the second sequence,(iv) generating a write pulse of the third polarity and a write pulse of the fourth polarity for the at least second bit of the second polarity occurring in the second sequence.

Abstract: A data and clock recovery circuit includes a front end circuit for receiving a data signal encoded with a Manchester or other bi-phase level code having a sequence of bit frames, and for outputting a recovered data signal and a recovered clock signal in accordance with transitions in the data signal that overlap with a window signal. A window generation circuit generates the window signal in accordance with a delay control signal, and includes circuitry that delays and transforms the recovered clock signal into the window signal. A delay control circuit generates and adjusts the delay control signal. A phase comparison circuit compares the recovered clock signal with leading and lagging portions of the window signal, and generates signals that adjust the delay control signal when the recovered clock signal overlaps with either of the leading and lagging portions of the signal.

Abstract: A Manchester decoder blanks random transitions prior to the reception of a valid Manchester encoded signal. Specifically, the decoder according to the present invention comprises a data input, and edge detector, and a blanking device. The edge detector is used to detect edges in a signal which is received by the data input. Thus, in the event that edges are not detected at predetermined intervals (signifying that a valid signal is not being received), the blanking device blanks a data output of the decoder. Advantageously, the decoder circuit filters random transitions prior to the reception of a valid Manchester encoded signal, is of simple construction, and may be implemented in conjunction with a decoder circuit which is used to separate the Manchester encoded signal into its data and clock components.

Abstract: An improved decoding apparatus for a Manchester code receives an asynchronous Manchester code, synchronizes to a received clock signal, and decodes an output NRZ code and an output synchronous clock signal. A first decoding unit samples an asynchronous Manchester code by synchronizing the asynchronous Manchester code to a shift of a received clock signal to produce a synchronous Manchester code and a synchronous clock, and computes an NRZ code. A tolerance check unit receives the synchronous Manchester code and checks a tolerance with respect to a shift at a bit cell center of the synchronous Manchester code. A multiplexer unit receives the NRZ code and the synchronous clock signal and selectively outputs a multiplexed NRZ code and a multiplexed synchronous clock signal in accordance with a detection signal outputted from the tolerance check unit.

Abstract: A method and apparatus for recovering clock and data signals from a Manchester code is provided. The present invention uses a phase lock loop with a digital delay line wherein an adjustable delay is introduced into the Manchester coded signal for synchronizing the coded signal with the local clock of the decoding apparatus. This delaying technique enables the present invention to successfully receive Manchester coded signals having substantial jitter. The present invention also conserves energy by reducing power consumption when no signals are present.

Abstract: An optical wireless communication method and apparatus configured to distinguish optical LAN data from optical noise is disclosed. The apparatus communicates using Manchester coded data via a connector connected to a personal computer. The Manchester coded data from the computer are converted to NRZ transmission data to be temporarily stored and read out. A frame of the read out data is appended with a head leader, and end data, at the head and end of the frame respectively to be convened to the DMI transmission optical data. The optical data inserted between the head leader and END data are receivable and can be distinguished from optical noise. The DMI received data removed from the head leader and end data are convened to data of the Manchester code in contrast with the transmission side to be delivered as the Manchester data via the connector. As the optical data with the head leader and end data are distinguishable from optical noise, high sensitive optical receivers are available.

Abstract: A dual clock tracking decoder for use in a local station of a token ring local area network extracts the mostly repetitive bit-cell transitions corresponding to the imbedded clock of a received phase encoded message from which a short term and a long term moving average estimate is made of the clock transitions relative to a local stable clock. The short term moving average adjusts rapidly to short term jitter and is used to sample the received phase encoded message twice each bit-cell and generate an intermediate phase encoded message that is resynohronized with a clock derived from the long term moving average of the estimated imbedded clock transition and having a rate that is twice the bit-cell rate of the received phase encoded message. This provides a mechanism for sampling the states of the incoming message with a clock that is adaptive to fast short term jitter while restoring an imbedded clock that is only responsive to slow longer term jitter.

Abstract: The method and associated apparatus of the present invention decodes optical signals by appropriately weighting the respective noise portions of the two phase segments generated by the photodetector, such as an APD, such that the optical signal can be reliably decoded. The photodetector detects an optical signal having a light portion and a dark portion. The photodetector then generates an electrical pulse in response to the optical signal. The electrical pulse has two phase segments, namely, one phase segment corresponding to the light portion of the optical signal and another phase segment corresponding to the dark portion of the optical signal. Each phase segment also includes a respective noise portion. The optical decoding method and apparatus determines a weighting factor based upon the respective noise portions of the two phase segments. Thereafter, at least one phase segment is weighted by the weighting factor. For example, the noisier phase segment can be attenuated by the weighting factor.

Abstract: A digital conversion circuit for receiving a Non-Return to Zero Level Data tream and then converting the Non-Return to Zero Level Data stream to a Bi-Phase Data stream. Combinational logic including an EXCLUSIVE-NOR circuit, three D-type Flip-Flops, AND gates, a NAND gate and inverters are utilized to convert the incoming Non-Return to Zero Level Data stream to the Bi-Phase Data stream while eliminating from the Bi-Phase Data stream any undesirable spikes or noise.

Abstract: A signal converter for converting a bi-phase-level data stream to non-ret-to-zero-level data. The bi-phase-level data stream is input to a detector circuit. When the detector circuit detects a high level for more than half of a bit period, the detector circuit provides a logic zero pulse at a state S7. If the high level is not at the logic one state for a sufficient time period the detector circuit will not reach state s7. If the time period is to short than the detector circuit is reset to state s0. This high level pulse occurs whenever the second half of a bit period is high followed by a high in the first half of the following bit period. A sample is taken on the first half of every bit period. A low at the detector circuit keeps the detector circuit at state s0. A clock signal generating circuit receives the logic zero pulse and then proceeds through its states s0-s10. When state S1 is reached a clock pulse is provided by the clock signal generating circuit.

Abstract: A modulation scheme and system, compatible with both the asynchronous IRDA mode and the synchronous mode of IR communication, involves Non-Return-to-Zero-Inverted (NRZI) and Flash pulse encoding in conjunction with zero-bit stuffing. A digital data stream has a zero-bit inserted therein, before NRZI format encoding, whenever five consecutive one's are detected in the stream to enable the controller to distinguish the data from flags, which are exempt from the zero-bit insertion, and to provide enough transitions in the data so that the demodulator's digital phase lock loop can stay locked independent of the data contents. A Flash pulse (of from 3/16 to 8/16 of bit cell width, depending on the data rate) is generated whenever a transition is detected in the NRZI formatted data. The result, in keeping with IRDA modulation, is that a Flash pulse is generated whenever a zero occurs in the data stream.

Abstract: A totally D.C. balanced and bit-rate independent digital clock encoding technique is applicable to a variety of digital signalling systems, including fiber optic digital signalling. Each of successive event cells of the clock signal is demarcated by clock transitions of opposite polarity, so that each clock cycle contains two event cells, one of which is redundant. For a first binary data value, such as a `0`, a pair of unmodified successive event cells of the clock signal are provided as an output. Namely, the clock signal is unaffected, so that both halves of a complete, unmodified clock cycle are reproduced `as is` as the encoded clock output. For a second binary data value, such as a `1`, an event cell is modified by inserting a pulse, of finite duration, less than the duration of the event cell, the pulse being delayed with respect to a leading clock transition of the pair of alternating, opposite clock transitions of the event cell.

Abstract: Binary signals that are transmitted by Manchester coding and frequency modulation are demodulated based on the behavior of the phase or complex vector value of the received signal. The polarities of the information bits may be determined by measuring the phase excursions in the middles of the Manchester symbols. A phase reference is established from a plurality of candidate phase references as a basis for comparison of the mid-symbol phase. The phase can be measured at the start-points and end-points of the symbols and averaged, or measured a plurality of times during each symbol period to generate a reference phase.