Abstract: An electronic calculating device (100) arranged to convert an input number (y) represented ((y1, y2, . . . , yk)) m a residue number system (RNS) to an output number represented in a radix representation ((e0, e1, . . . es?1)), the calculating device comprising an input interface (110) arranged to receive the input number (y) represented in the residue number system, and a processor circuit (120) configured to iteratively update an intermediate number (?) represented in the residue number system, wherein iterations produce the digits (e0, e1, . . . es?1) in the radix representation with respect to the bases (b0, b1, . . . , bs?1), at least one iteration comprises computing the intermediate number modulo a base (bt) of the radix representation to obtain a digit (et=(?)bt) of the radix representation, updating the intermediate number (??(??et+F)/bt) by subtracting the digit from the intermediate number, adding an obfuscating number (F; Ft), and dividing by the base (bt).

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M?1 modulo units of the logarithmic tree provide x[0:m]mod d for all m?{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ?log 2M?; and more than M?2u of the subset of modulo units are arranged at the maximal delay of ?log 2M?, where 2u is the power of 2 immediately smaller than M.

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b] mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M?1 modulo units of the logarithmic tree provide x[0: m] mod d for all m?{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ?log2 M?; and more than M?2u of the subset of modulo units are arranged at the maximal delay of ?log2 M?, where 2u is the power of 2 immediately smaller than M.

Abstract: A computer-implemented method includes: receiving, using a processor, a decimal floating point number; and using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.

Abstract: Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.

Abstract: Arithmetic circuits and methods that perform efficient conversion of fractional RNS representations to fractional binary representations is disclosed herein.

Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations.

Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. In one or more embodiments, an RNS ALU or processor comprises a plurality of digit slices configured to perform modular arithmetic functions. Operation of the digit slices may be controlled by a controller. Residue numbers may be converted to and from fixed or mixed radix number systems for internal use and for use in various computing systems.

Abstract: Methods and systems for conversion of binary data to residue data, and for conversion of residue data to binary data, allow fully extensible operation with related methods and systems for residue number based ALUs, processors and other hardware. In one or more embodiments, a residue to binary data converter apparatus comprises a mixed radix to fixed radix conversion apparatus. In one or more embodiments, a mixed radix converter apparatus assists internal processing of a related residue number based ALU, processor or other hardware.

Abstract: In a communication system, a transmitting unit divides each of latitude data and longitude data of a current location transmitted from a GPS receiver, at a predetermined digit position, into high order data and low order data. The transmitting unit makes a high order frame containing the high order data of each of the latitude data and the longitude data, and a low order frame containing the low order data of each of the latitude data and the longitude data, and transmits the high order frame and the low order frame, independently to a CAN bus. A receiving unit combines the high and low order data regarding the latitude data together, and further combines the high and low order data regarding the longitude data, extracted from the received high and low order frames in order to reconstruct the latitude data and the longitude data of the current location.

Abstract: Mechanisms are provided for the compact storage of geographical geometries as a collection of points, where individual points are encoded as binary/ternary strings (with the property that points closer to each other share a longer binary/ternary prefix) and the geometry is encoded by compressing the binary/ternary representation of common-prefix points. Mechanisms are also provided for the representation of a geometry using a ternary string that allows efficient storage of arbitrary shapes (e.g., long line segments, oblong polygons) as opposed to binary representations that are more efficient when the geometries are square or nearly square shaped.

Abstract: In a first embodiment of the present invention, a method for automated creation of a mashup is provided, the method comprising: receiving data needs of a user; identifying sources of data to satisfy the data needs by comparing the data needs to available data sources; retrieving metadata relating to the identified sources of data from a source metadata store; identifying services to satisfy the data needs by comparing the retrieved metadata to available services; retrieving metadata related to the identified services from a service metadata store; and generating a plan for supplying data from the identified sources of data to the identified services based on the retrieved metadata from the source metadata source and the retrieved metadata from the service metadata source.

Abstract: An improved transmission protocol is used to transmit a signal between two components of an electronic device. The improved transmission protocol is configured to reduce the number of simultaneous channel transitions that occur when multiple signal channels are transmitted in parallel. Reducing the number of simultaneous channel transitions is beneficial because a signal that is subject to skew, distortion, or electromagnetic interference during transmission may have a shorter settling time when fewer channels undergo a transition simultaneously. When the protocol is used to transmit a signal from a controller to an optical pickup unit in an optical data storage system, the reduced settling times allow for a higher data transmission rate.

Abstract: It is an object of the present invention to provide a technology that a microcomputer is capable of detecting the states of a large number of switches with a small number of ports. In a microcomputer system according to the present invention, any one of (2N?1) kinds of the combination patterns with respect to the combination of N input ports (IP1 to IP4) of a microcomputer (1) is allocated to each of M push-down switches (SW12, SW13, SW14, SW23, SW24, and SW34) with the different combination from each push-down switch. Each push-down switch inverts the input levels of the input ports in the combination pattern allocated thereto when pushed down. The microcomputer (1) detects the state of each push-down switch on the basis of the input levels of the N input ports.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for identifying misrepresented characters in strings of text. A computer system receives text that includes characters identified as being encoded in UTF-8. The characters are represented as code point values, each code point value representing one character in the text. The computer system makes a determination that the text likely includes characters incorrectly converted from Win-1252 to UTF-8 by comparing the code point values that represent the text with test values. Based on the comparison, the computer system identifies sequences of characters in the text that was likely incorrectly converted.

Abstract: Circuitry separates a modulation signal into digital sign and magnitude signal components. The digital magnitude signal is converted to an analog magnitude signal. The analog magnitude signal is the mixed with an in-phase or quadrature carrier signal under the influence of the digital sign signal and routed to a driver output stage.

Abstract: A system and method of compression is disclosed that includes the generation of position codes based on positions of individual codes. Individual codes having the same value are adjacent in the position code and are separated by a spacer code. The position codes can be generated from individual codes in increasing value or decreasing value of the individual codes. The position code can be prefixed by a maximum value of the individual codes or prefixed by a total number of the individual codes. The individual codes can be representative of an audio or a video data stream.

Abstract: In described embodiments, a method of generating an identifier for a disk includes the steps of requesting an ASCII identification string for the disk and generating a padded string by processing the ASCII identification string into a predetermined number of bytes. The padded string is divided into portions and an encoded value is generated for each portion. The two or more encoded values for the portions are combined into a candidate value compatible with a World-Wide Name (“WWN”). The candidate value is compared to a list of previously generated candidate values and if the candidate value differs from the values in the list, the candidate value is included in the list of generated values and the candidate value is provided as the system-wide name for the disk.

Abstract: Method and system for representing a strong of alpha characters, numeral characters and/or delimiters that allows uniform searching procedures, whether or not numerals and/or delimiters are present in the string. Numerical sub strings, containing only numerals and delimiters, are re characterized in binary format and are separated from, and later recombined with, sub strings containing only alpha characters and delimiters, to provide a modified searchable string in binary format Floating point numbers are easily handled in this approach. Delimiters may be any subset of ASCII characters, as distinguished from numerals and from alpha characters. A numeral character, to be transmitted as a sequence of bits, is optimized by expression in a base (power of 2) requiring the smallest bit count.

Abstract: A method of transforming a geographic coordinate to a geographic location code includes the steps of: retrieving a latitude value and a longitude value of the geographic coordinate; quantizing the latitude value to a first integer value; quantizing the longitude value to a second integer value; converting the first integer value to a first code string, said first code string including a first digit representing a non-numeric character, a second digit representing a non-numeric character, and a third digit representing a numeric character; converting the second integer value to a second code string, said second code string including a fourth digit representing a non-numeric character, a fifth digit representing a non-numeric character, and a sixth digit representing a numeric character; and combining the first code string and the second code string to obtain the geographic location code having a fixed pattern of radix in a mixed radix notation system representation.

Abstract: Briefly, in accordance with one embodiment, a method of data compression is disclosed.

Abstract: A method includes receiving, at a decoding device, first contents of a buffer, where the first contents of the buffer include at least a first data symbol. The first data symbol is coded into the first contents of the buffer based at least in part on a first radix of the first data symbol. The first data symbol is decoded from the first contents of the buffer. Based at least in part on the first radix of the first data symbol, it is determined whether the first contents of the buffer include a second data symbol. The second data symbol is decoded from the first contents of the buffer if the first contents include the second data symbol.

Abstract: A method of transforming a geographic coordinate to a geographic location code includes the steps of: retrieving a latitude value and a longitude value of the geographic coordinate; quantizing the latitude value to a first integer value; quantizing the longitude value to a second integer value; converting the first integer value to a first code string, said first code string including a first digit representing a non-numeric character, a second digit representing a non-numeric character, and a third digit representing a numeric character; converting the second integer value to a second code string, said second code string including a fourth digit representing a non-numeric character, a fifth digit representing a non-numeric character, and a sixth digit representing a numeric character; and combining the first code string and the second code string to obtain the geographic location code having a fixed pattern of radix in a mixed radix notation system representation.

Abstract: Coding efficiently in non-power-of-two ranges. Coding is performed in an N-bit system, where certain codes are represented with N bits and other codes are represented with (N+1) bits. An example is where the other codes may have an N-bit representation used to represent multiple values, with the additional bit being disambiguation information provided to distinguish the codes having multiple values. Thus, N bits are used to represent most codes, and an extra bit is used to represent other codes. The number of bits per element used for representing a sequence is, on average, close to a theoretical minimum for N-bits.

Abstract: In one of many possible embodiments, a system for optimizing bit utilization in data encoding is provided. The exemplary system includes a data processing subsystem configured to identify a total number of unique characters within a set of data, which number represents an original base of representation of the set of data. The data processing subsystem is further configured to convert the set of data to a base of representation that is higher than the original base of representation and then encode the base-converted data with a fixed-length encoding scheme.

Abstract: Techniques are provided for reducing error propagation in encoded data using Fibonacci modulation codes. The Fibonacci modulation codes have a Fibonacci base with a variable span that limits error propagation. Some of the elements in the Fibonacci base have a larger span than limited span elements in the base. Errors occurring in bit positions of an encoded sequence that correspond to the limited span elements do not propagate to adjacent bytes in the decoded sequence. The Fibonacci modulation codes can also have a relatively high code rate.

Abstract: Embodiments described herein may include example embodiments of a method, article and/or apparatus for coding data which may be used for communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system, and/or for communication between computing platforms via a network or other interconnection medium.

Abstract: Circuitry separates a modulation signal into digital sign and magnitude signal components. The digital magnitude signal is converted to an analog magnitude signal. The analog magnitude signal is the mixed with an in-phase or quadrature carrier signal under the influence of the digital sign signal and routed to a driver output stage.

Abstract: A method includes receiving, at a decoding device, first contents of a buffer, where the first contents of the buffer include at least a first data symbol. The first data symbol is coded into the first contents of the buffer based at least in part on a first radix of the first data symbol. The first data symbol is decoded from the first contents of the buffer. Based at least in part on the first radix of the first data symbol, it is determined whether the first contents of the buffer include a second data symbol. The second data symbol is decoded from the first contents of the buffer if the first contents include the second data symbol.

Abstract: A method and apparatus for data encoding such as 3 to 4 encoding (base64, uuencode etc.) is provided. Bytes of data to be encoded having negative values are made positive while preserving the information to be encoded. The positive values may be manipulated by addition (e.g. to a common store) and bit shifting to efficiently obtain encoded data such as by indexing an encoding alphabet.

Abstract: A method of buffering includes determining, based at least in part on a radix of a data symbol, a number of discrete values resulting from coding the data symbol into a buffer. The number of discrete values is compared with a buffer capacity of the buffer. The buffer is scaled based at least in part on the radix of the data symbol if the number of discrete values does not exceed the buffer capacity of the buffer. The data symbol is coded into the scaled buffer if the number of discrete values does not exceed the buffer capacity of the buffer.

Abstract: A system and method for providing low latency constrained coding for parallel busses. The method includes receiving a value for a number of transfers and a number of possible constrained patterns between adjacent transfer rows. Data to be encoded is received. The data is converted into indices of constrained patterns, the converting including a number base change into a new base. The new base is chosen so as to optimize the number of operations required to perform the converting subject to the new base being at least as large as the number of possible constrained patterns between adjacent transfer rows. The indices of the constrained pattern are converted into encoded data. The encoded data is then output.

Abstract: A data output apparatus converts input data into data that changes less than the input data, and outputs the converted data to a memory.

Abstract: A first PDU conversion unit converts a data string before conversion to a data string in a first data structure. A second PDU conversion unit converts a data string before conversion to a data string in a second data structure different from the first data structure. A selection unit selects one of the first PDU conversion unit and the second PDU conversion unit. A transmission unit transmits a data string obtained by the conversion by the unit selected by the selection unit, and an identification signal output from a transmission control unit as selection information indicating a selection result by the selection unit.

Abstract: Signal samples X in a floating-point format, each of which is composed of 1 bit of sign S, 8 bits of exponent E and 23 bits of mantissa M, are converted through truncation by an integer formatting part 12 into signal samples Y in a 24-bit integer format, the integer-value signal samples Y are coded by a compressing part 13 into a code sequence Ca, and the code sequence Ca is output. According to the number of digits n following the most significant “1” in the integer-value signal sample Y, a difference producing part 14 extracts the least significant (23?n) bits from the mantissa M of the input signal sample X to form a difference signal Z, and a compressing part 17 performs entropy coding of the difference signal Z to produce a code sequence Cb and outputs the code sequence Cb. Alternatively, the difference signal Z may be output as it is, rather than being compressed.

Abstract: Techniques are provided for applying modulation constraints to data by using periodically changing symbol mappings to replace certain prohibited error prone data patterns. Initially, user data in a first base is mapped to integers of a second base using a base conversion technique. The integers in the second base correspond to symbols. Subsequently, periodically changing symbol mappings are performed during which prohibited symbols generated during base conversion are mapped to permitted symbols. The periodically changing symbol mappings occur in multiple phases, and the prohibited symbols are different in each phase. The resulting data is processed by a precoder in some embodiments.

Abstract: A method of encoding data includes representing the data as number(s) in a first base. The method further includes converting the number(s) into a number(s) in a second base. The resultant number in the second base can be viewed as data suitable for encoding using an ECC algorithm. After being ECC encoded, the data may be further modulation encoded. Modulation encoding may include transforming each symbol to a value that constrains run lengths of a binary value (e.g., zero). A decoding method and system checks a received data block for erroneous symbols, maps each received, encoded symbol to an associated ECC-encoded transform pair. The ECC encoded data may be decoded and corrected using the ECC and the locations of identified erroneous symbols. Finally, the corrected data sequence is converted from the second base back to the first base, from which the original data is retrieved.

Abstract: A data conversion apparatus and a data conversion method are disclosed by which, when data of a format used in a processing apparatus is to be written into a memory, it can be written in a compressed form and, when the data is to be read out from the memory, it can be read out in a decompressed form. An address conversion section converts an address from the processing apparatus side from an address of a floating-point data space into an address of a fixed-point data space. A data compression section converts data of a floating-point format from the processing apparatus side into data of a fixed-point format. A data decompression section converts data of the fixed-point format from the memory side into data of the floating-point format. A predetermined portion of the address is utilized, upon the data conversion, as an exponent part of the data of the fixed-point format.

Abstract: A data conversion apparatus and a data conversion method are disclosed by which, when data of a format used in a processing apparatus is to be written into a memory, it can be written in a compressed form and, when the data is to be read out from the memory, it can be read out in a decompressed form. An address conversion section converts an address from the processing apparatus side from an address of a floating-point data space into an address of a fixed-point data space. A data compression section converts data of a floating-point format from the processing apparatus side into data of a fixed-point format. A data decompression section converts data of the fixed-point format from the memory side into data of the floating-point format. A predetermined portion of the address is utilized, upon the data conversion, as an exponent part of the data of the fixed-point format.

Abstract: In the method for coding/decoding a target range from a value range, a recurrence step is repeated in a coding/decoding step for the target range until code bits are found for the target range to be coded, or the target range to be decoded is found using the code bits. In the recurrence step, an interval of the value range within which the target range to be coded/decoded is located is divided into two new intervals, and a single bit is used to indicate in which of the two new intervals the target range to be coded/decoded is located. The new interval indicated with the single bit is used as the interval for the next recurrence step. The code bits for the target range to be coded or the target range to be decoded is found when the interval falls below a minimum quantity. In at least one recurrence step, a probability distribution is used as the basis for the target range in the interval, and the new intervals are selected based on the probability distribution.

Abstract: In order to provide an exponent encoder circuit for obtaining an exponent constituted by a left shift amount for normalizing input data with code bits, there is provided a first logic circuit for inverting data portions other than code bits and shifting the code bits to least significant bit positions when inputted data is a negative number and allowing data portions other than the code bits to pass as is and moving the code bits to least significant bit positions when the inputted data is a positive number, and a second logic circuit for putting a plurality of logic operation equations for obtaining each bit of an exponent from output of the first logic circuit as decided by a truth table for outputs of the first logic circuit and corresponding exponents in a form where common terms are cancelled out.

Abstract: Numeric data is encoded as a variable-length, NULL-terminated string. The first character of the string represents the sign of the numeric data, the second character of the string represents the exponent of the numeric data, the following characters represent the digits of the mantissa of the numeric data and the final character is a termination character.

Abstract: Between digital data signals, which are expressed using a notation system of three digit symmetric binary numbers (named “HEN2”), and analog signals, at least one way, mutual, or other conversions are made. Three digit symmetric binary numbers (HEN2), are a combination of signals in which at least one of two adjacent digits, at any digit position of one or more digits of 2-based three digit redundant binary numbers with one signal of three digits {n, o, p} expressing a value {−1, 0, 1} as a one-digit signal, is a signal “o” expressing zero. Thus three digits {−1, 0, 1} are used instead of the two digit {0, 1} binary system used in conventional A/D or D/A converters.

Abstract: The present invention is for an implementation of a digital decimation filter and/or digital interpolation filter and a method of decimating and/or interpolating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. Scaling and multiplication of data with coefficients is performed using a common DSP architecture. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

Abstract: A method and device for displaying map data and related data and thereby permitting easy enlargement of the scope of the application of map-based data services, wherein additional drawing data for superposing on a map displayed on a screen, and setting data for specifying a map display, are sent and received between different application programs using inter-application exchange in a standard data format. Required map data and related data are displayed on the screen using a first application program having a function for converting received additional drawing data and setting data to the aforesaid data format and transmitting it by inter-application exchange, then using a second application program which displays a map on the display screen according to the setting data transmitted by the first application program and displays additional data on the screen map corresponding to the additional drawing data.

Abstract: A modulation encoder includes a base conversion circuit that converts a partitioned input data stream from a first base representation in accordance with the size of groups of bits in the partitioned stream into a second base representation. The base conversion circuit includes a circuit to produce intermediate values of the partitioned stream in the second base representation and a residual value logic circuit that performs modulo-arithmetic on intermediate values modulo the second base representation, and a one's complement logic network fed by the residual value logic to produce output code words. A modulation decoder includes a one's complement logic circuit fed by modulation code words to produces residual value words; and a base conversion circuit that converts residual value words from a first base representation into a second base representation to provide original user data.

Abstract: HEN2, which is a combination of signals in which at least one of two adjacent digits at any digit position of one or more digits of a 2-based three digit redundant binary number with one signal of three digits {n, o, p} each expressing value {−1, 0, 1} as a one-digit signal is a signal “o” expressing zero, is handled as one set of notation, not as a subset of the three digit redundant binary number.

Abstract: To encode data Y after separating the data Y into a scale factor SF, a word length, and a data value X. For this purpose, X=Y·{2(WL−1)−1}/SF is calculated. Here, a value of {2(WL−1)−1}/SFV with respect to a number of SFV and a number of SL, which are obtained by separating into SF=SF·2SFF, is stored in a ROM in advance. Then, input data Y is separated into a mantissa part Yr and an index part Ye and Ye is added to SFF. Then, the shifter 16 shifts Yr according to an additional result to obtain Ye·2Ye·2SFF. On the other hand, based on SF and WL, which are determined with respect to Y, a value of corresponding {2(WL−1)−1}/SFV is read from the ROM. Then, the shifted result is multiplied by the output from the ROM to obtain a data value X. Also, Y=SF·X/{2(WL−1)−1} is calculated and decoded. Inputted SF is divided into SFV and SFF.

Abstract: A map information server is disposed on the Internet, and when a position on a page is input, the map information server searches latitude information and longitude information corresponding to the position, encodes the latitude information and longitude information to a character string corresponding to a predetermined rule, and displays the resultant character string. When an encoded character string of latitude information and longitude information is input, the map information server searches the position corresponding to the latitude information and longitude information and displays the position on a map. In addition, when latitude information and longitude information are input, the map information server encodes the latitude information and longitude information to a code of a character string corresponding to a predetermined rule.

Abstract: This invention consists of a data communications interface that provides the means for an electronic, binary, data processing apparatus, or digital computer, to encode information in a base four format, and to communicate, with other data processing apparatuses, which utilize this invention, by exchanging base four digits, in a serial manner, via a standard data communications medium, such as a telephone line. This invention is composed of a serial communication device (SCD) and a line driver (LD). The SCD converts parallel, binary data to serial, base four data, and visa versa. The LD converts base four voltage levels to signals that are appropriate for the communications medium, and visa versa. A tone, for example, would be an appropriate signal for a telephone line. This invention enables information to be exchanged much more rapidly than is possible with a state of the art system.