Abstract: Multiple resonant tunneling devices offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. A multivalued logic adder is disclosed, wherein two numbers represented by positive digit base-M range-N words are added by two-input summation circuits 40 which sum corresponding digits, then the digit sums are decomposed into a binary representation by range-7 multivalued to binary converter circuits 42, then three-input summation circuits 44 sum appropriate bits of the binary representations to calculate the digits of a positive digit base-2 range-4 word whose value is the sum of the two numbers. Preferably, the decomposition to binary representation is performed by multi-valued folding circuits 56 which are connected by voltage divider circuitry. Preferably, the multi-valued folding circuits contain multiple-peak resonant tunneling transistors 54. Ripple carries are eliminated and the speed of the adder is independent of input word width.

Abstract: The decimal numbers in ASCII code are converted into base n number codes, where the base n is greater than ten, and then are transmitted between the main control unit and the terminals including servo systems and spindle systems in an automated factory system. The data is thus compressed, and greater number of axes of the numerically controlled devices, etc., can be controlled within a predetermined time length for transmitting the data.

Abstract: A method and related input/output devices for using biased 2 digit "hybrid radix" numeric fields for inputting, generating, storing, processing, and outputting year numbers ranging from 1900 to 2059 in a data processing system. In a hybrid radix 2 digit year number, the higher digit is treated as hexadecimal, but displayed in a decimal-like style with font patterns such as 0-9 and '0-'5, while the lower digit is treated as ordinary decimal, so that the year 1900 is represented and processed as 00 while the year 2000 as '00. For applications written with high level languages such as COBOL and SQL, the method can be embodied solely in the system side (compiler, other system software and/or hardware), and so that no change other than a re-compilation with a new compiler is needed for existing application software. Compatibility with existing data files and databases is automatically maintained.

Abstract: Data are transmitted using multiple carriers modulated by quadrature amplitude modulation. In general, the carriers carry different numbers of bits, to exploit the fact that the properties of a transmission path are more favorable to carriers at some frequencies than to those at others. The bit allocation process is made closer to optimum by permitting allocation of a non-integer number of bits to a carrier. Input bits are grouped for several carriers and this binary representation is converted to a number representation in which the base of each digit corresponds to the number of points in the QAM constellation for a respective carrier (or to this number divided by a power of two).

Abstract: Multiple resonant tunneling devices offer significant advantages for realizing circuits which efficiently convert values represented by multivalued number systems to conventional binary representation. In one form of the invention, a number represented by a range-4 base-2 word is converted into a conventional binary word (range-2 base-2) having the same value. The conversion is accomplished by a series of decomposition stages 53, each decomposition stage 53 producing an interim range-4 base-2 word and a binary digit, which becomes one of the digits of the binary output word. Preferably, the decomposition at each stage is accomplished by a set of range-4 base-2 to binary converters 50, each of which operates on a single digit of the interim word. Preferably, summation circuits 52 sum outputs of adjoining range-4 base-2 converters 50 to form the new interim word. The least significant digit of the output of the decomposition stage becomes a digit of the output binary word.

Abstract: Improved means and methods are provided for transmitting binary data on a communication system, such as E-mail, which restricts the number of acceptable characters that can be transmitted. In a preferred embodiment, the binary data to be transmitted is first subjected to a Welch compression and then converted into base-85 digits for transmission. At the receiving end, the received base-85 digits are converted back into compressed binary and then subjected to Welch decompression to obtain the original binary data.

Abstract: A residue addition overflow detection processor detects overflow resulting from the addition of two residue numbers by extending the base of the two numbers, adding the two extended numbers to each other, and converting the resultant sum into mixed base representation. The digits of the mixed base representation are processed to produce signals indicating whether overflow has occurred. Delay circuits maintain the synchronism of the processing. The detection processor can be used in conjunction with optical information processing systems.

Abstract: In a method and apparatus for encoding and decoding data in the residue number system, input binary data are supplied to an encoder to be divided by moduli m.sub.0, m.sub.1, m.sub.2, . . . m (i.e., positive integers having a mutually prime relation). Residue data corresponding to respective moduli are output from the encoder to a digital filter circuit including a plurality of digital filters, each filter corresponding to a respective modulus. Processing for some specified application is performed by the digital filters based, for example, on the Mixed Radix Conversion Method method to generate output data still in the residue format. The residue data output from the digital filters then are input to a decoder to be converted back into binary data. Encoding is performed by splitting n-bit straight binary data into, for example, upper bit data and lower bit data, received by respective ROM tables. Each ROM table outputs a value to another common ROM table which outputs the converted residue data.

Abstract: An information processor receives a residue number as an input and generates a mixed base number correspopnding to the residue number and a redundant residue digit corresponding to the residue number. The information processor includes a plurality of optical arithmetic and logic units (OALUs) arranged in channels and stages. Each digit of the residue number corresponds to a channel. Each channel produces a mixed base digit associated with the residue input number. The stages are serially arranged to successively generate mixed base digits corresponding to the residue number by performing modular multiplication and modular subtraction. Delay circuits are arranged parallel to the plurality of OALUs such that all of the mixed base digits are transmitted from the information processor at the same time. An additional channel of OALUs calculates the redundant residue digit based on the mixed base digits.

Abstract: A numeric encoding method and apparatus for neural networks, encodes numeric input data into a form applicable to an input of a neural network by partitioning a binary input into N-bit input segments, each of which is replaced with a code having M adjacent logic ones and 2.sup.N -1 logic zeros, the bit position of the least significant of the M logic ones corresponding to the binary value of the input segment it replaces. The codes are concatenated to form an encoded input. A decoding method decodes an output from the neural network into a binary form by partitioning the output into output segments having 2.sup.N +M-1 bits each, each of which is replaced with an N-bit binary segment being a bracketed weighted average of the significances of logic ones present in the output segment. The binary segments are concatenated to form a decoded output.

Abstract: A residue number system to mixed base number system converter includes one or more digit converters arranged in parallel. Each digit converter includes sources, interconnects, detectors, and threshold detectors. The interconnects are arranged and trigger values of the threshold detectors are selected to accomplish conversion from inputted residue digits to outputted mixed base digits. The system may be implemented using electronic or optical technologies.

Abstract: Signal processing techniques are disclosed for applications such as finite impulse response filtering. After initial processing in residue number system (RNS) channels, the signals are converted from residue form to a true external representation of the filter output. The conversion employs a chinese remainder theorem decoder and shift accumulator controlled to utilize adaptive modulo reduction. As a consequence, each modulus function value is reduced during computation when it exceeds the modulus and not at the end of the function evaluation. This reduces hardware requirements by minimizing the arithmetic word length. In implementing the technique, each function value is tested to see if it is within a modulus range and the corresponding modulus value is subtracted if it is not. This is done as many times as is necessary to bring each function value within the range.