Abstract: In accordance with an example embodiment of the present invention, there is provided an apparatus configured to instruct a redundancy encoder to increase a level of redundancy of a media stream, an error rate determination to determine an error rate of a communication path conveying the media stream with increased redundancy, a comparator configured to compare a bandwidth used to convey the encoded media stream at the increased redundancy level with a bandwidth for conveying the encoded media stream at a second quality level greater than the first quality level, the apparatus being further configured to provide a switching signal to a media encoder to start encoding the media stream at the second quality level responsive to the used bandwidth being sufficient for conveying the media stream encoded at the second quality level and the determined error rate being less than a predetermined threshold value.

Abstract: There is provided a compression system configured to compress logical data objects into one or more accommodation blocks with a predefined size, and a method of operating thereof. The compression system comprises a compression engine capable of compressing input data with the help of sequential encoding one or more input strings and a counter operatively coupled to the compression engine. The counter is configured to keep its ongoing value indicative of a number of input bytes in one or more strings successfully encoded into a given accommodation block; and, responsive to unsuccessful compression of a string into the given accommodation block, to provide the compression engine with information indicative of starting point in the input stream for encoding into the next accommodation block, thus giving rise to a “start indication”.

Abstract: In a method for error handling in transmission of a datum over a communications system, at least two data words consisting of bits are generated for the datum in accordance with a predefined coding rule, and one of the generated data words is selected taking into consideration a running digital sum formed over the corresponding data word, and the running digital sum of the selected data word is used for the formation of a first running digital sum. The selected data word is converted into a code data word, and a bit of the data word is in each case assigned a two-bit string with two different single-bit values. The code data word and the first running digital sum are transmitted. The received code data word is examined to ascertain whether an erroneous two-bit string exists, in which case the error is corrected using the first running digital sum.

Abstract: Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein.

Abstract: Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level.

Abstract: A system includes a precoder-aware running digital sum (RDS) encoder that encodes user data as w-bit sub-blocks, to produce an encoded data block that meets block RDS constraints and consists of encoded data sub-blocks that meet sub-block RDS constraints. The sub-block constraints include the data sub-blocks having the same magnitude RDS before and after precoding. The encoder data block is further encoded using an error correction code to produce parity bits, and the parity bits are dispersed, as i-bit parity sub-blocks, between selected data sub-blocks to form a code word. The code word is then precoded to produce a precoded bit sequence for transmission over a channel. Sub-block run length limit (“RLL”) constraints may also be included, such that the encoded data block meets both RLL and RDS, with the encoded data sub-blocks meeting respective RLL and RDS sub-block constraints.

Abstract: Provided is a code conversion device that is capable of converting codes even if an input code sequence is invalid, and is able to reduce the amount of processing. When a first code sequence is input, the code conversion device generates a decoded signal by decoding the codes of normal frames of the first code sequence at Step S1, stores and holds the decoded signal at Step S2, generates a signal corresponding to an invalid frame by interpolation with the decoded signal that is stored and held, at Step S3. Subsequently, the code conversion device generates codes corresponding to the invalid frame by encoding the generated signal at Step S4, and makes the normal frames of the first code sequence without conversion be the frames of the second code sequence while making the generated codes be the frame of the second code sequence, in place of the codes of the invalid frame, at Step S5.

Abstract: A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes.

Abstract: A method of encoding data for transmission from a source to a destination over a communications channel is provided. A plurality of encoded symbols are generated from a set of input symbols including source symbols and redundant symbols, wherein the input symbols are organized such that at least one of the input symbols is not used for a first encoding process, so that it is permanently inactivated for the purposes of scheduling a decoding process. A method of decoding data is also provided, wherein encoded symbols generated from a set of input symbols are used to recover source symbols, wherein the input symbols are organized such that at least one of the input symbols is not used for a first decoding process, so that it is permanently inactivated for the purpose of scheduling the decoding process.

Abstract: A Berger invert code encoding and decoding method is disclosed. The method includes steps: Selecting logic value 0 or 1 to represent the stable and unstable states respectively. Calculating the stable bit count and the unstable-bit count of the codeword. Checking whether the unstable bit count is larger than the stable bit count or not. Setting the Invert Bit to the unstable state for indicating the inversion when the unstable bit count is larger than the stable bit count. Resetting the Invert Bit to the stable state for indicating the non-inversion when the unstable bit count is not larger than the stable bit count. Concatenating the Invert Bit to the codeword as a new codeword.

Abstract: A method for embedded encoding of at least two types of information is described. A first message and a second message are received. The types of a first encoder and a second encoder are determined. The rates of the first encoder and the second encoder are determined. A first codeword and a second codeword are generated. A mapping rule for the second codeword and a coding rule for the first codeword are determined. The second codeword is mapped into a plurality of symbols using the mapping rule. A third codeword is determined using the first codeword, the plurality of symbols, and the coding rule. The third codeword is then transmitted. The third codeword includes at least two types of information.

Abstract: Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein.

Abstract: A semiconductor memory device configured such that the time required for its access test can be reduced comprising a memory cell array, a row decoder, a column decoder, an error correction circuit, and an output circuit. The error correction circuit performs error correction on a code word read through the bit lines selected by the column decoder from ones of memory cells located at places at which the word line selected by the row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating the error position and corrects the information bit in the detected error position to generate error corrected data. The output circuit relays to the outside the error corrected data when a normal operation mode has been designated and the error detection data when a test operation mode has been designated.

Abstract: In a method for error handling in transmission of a datum over a communications system, at least two data words consisting of bits are generated for the datum in accordance with a predefined coding rule, and one of the generated data words is selected taking into consideration a running digital sum formed over the corresponding data word, and the running digital sum of the selected data word is used for the formation of a first running digital sum. The selected data word is converted into a code data word, and a bit of the data word is in each case assigned a two-bit string with two different single-bit values. The code data word and the first running digital sum are transmitted. The received code data word is examined to ascertain whether an erroneous two-bit string exists, in which case the error is corrected using the first running digital sum.

Abstract: A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one.

Abstract: A run-length limited (RLL) encoder includes a block detection module that receives a data block that includes N portions and generates N?1 coding bits indicating whether corresponding ones of N?1 of the N portions of the data block include one of all ones and all zeros, where N is an integer greater than two. A mapping module generates an RLL codeword including N portions comprising bits that are determined by a first mapping table, a second mapping table, bits of the data block and the N?1 coding bits.

Abstract: A transmission device configured to transmit a transmission bit string which is an arrangement of a unit bit string of multiple N bits includes: a conversion unit configured to convert the unit bit string into a converted bit string in accordance with a conversion table obtained by obtaining an error rate wherein a k'th bit out of the N bits is in error; obtaining an error expectancy which is an expectancy that a significant bit of the N bits in the unit bit string will err; and creating a conversion table that correlates the unit bit string and a converted bit string obtained by converting the insignificant bit of the unit bit string to a smallest error expectancy bit pattern which is a bit pattern that minimizes the error expectancy of the multiple bit patterns; and a transmission unit configured to transmit the converted bit string.

Abstract: Provided is a code conversion device that is capable of converting codes even if an input code sequence is invalid, and is able to reduce the amount of processing. When a first code sequence is input, the code conversion device generates a decoded signal by decoding the codes of normal frames of the first code sequence at Step S1, stores and holds the decoded signal at Step S2, generates a signal corresponding to an invalid frame by interpolation with the decoded signal that is stored and held, at Step S3. Subsequently, the code conversion device generates codes corresponding to the invalid frame by encoding the generated signal at Step S4, and makes the normal frames of the first code sequence without conversion be the frames of the second code sequence while making the generated codes be the frame of the second code sequence, in place of the codes of the invalid frame, at Step S5.

Abstract: A method and an apparatus for encoding and decoding a modulation code are provided. The method includes: adding an error detection bit(s) to source information; performing k-constraint coding by inserting an error pattern that can be detected using an error detection code into a data stream that violates a k-constraint for a run length limited (RLL) code in a data stream comprising the error detection bit(s) and the source information, and recording the data stream after being k-constraint coded onto a recording medium; and reading the data stream recorded onto the recording medium and determining whether an error is present in the data stream.

Abstract: Described is a system and method for receiving a signal for transmission and encoding the signal into a plurality of linear projections representing the signal. The encoding includes defining a transform matrix. The transform matrix being defined by processing the signal using a macroseparation matrix, processing the signal using a microseparation matrix and processing the signal using an estimation vector.

Abstract: Systems, methods and data structures are provided for representing robust data transmitted within a control system. The data structure includes at least two data fields identifying sub-modules and sub-modes of the control system, and optionally includes a third field for designating a primary operating mode of the control system and/or a fourth field representing a handshaking bit or value. The operating modes, sub-modes and sub-module designators are represented by values of the bits selected such that no single bit transition results in the selection of another valid operating state of the control system. As a result, single bit errors will not produce erroneous operating results. Similar concepts can be optionally applied to ensure that errors in contiguous sets of four, eight or any other number of bits do not produce valid states represented by the data structure.

Abstract: A semiconductor memory device configured such that the time required for its access test can be reduced comprising a memory cell array, a row decoder, a column decoder, an error correction circuit, and an output circuit. The error correction circuit performs error correction on a code word read through the bit lines selected by the column decoder from ones of memory cells located at places at which the word line selected by the row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating the error position and corrects the information bit in the detected error position to generate error corrected data. The output circuit relays to the outside the error corrected data when a normal operation mode has been designated and the error detection data when a test operation mode has been designated.

Abstract: Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level.

Abstract: A method and apparatus are provided for preserving binary data on an analog archival medium, such as microfilm, in which the binary data is encoded, such as in a barcode symbol, in accordance with a predefined encoding specification. The predefined encoding specification may be stored along with the binary data to facilitate subsequent recovery of the binary data, even if the encoding technique has become obsolete. Error detection and correction code may be generated for the binary data and stored along therewith. By comparing the error correction code associated with the original binary data with an error correction code generated based upon the recovered data, the accuracy of the recovered data may be confirmed. Corresponding methods and apparatus for recovering the binary data are also provided.

Abstract: A fast decoding technique for decoding a position of a bit in a pattern provided on a media surface that can generate large amounts of solution candidates quickly by switching or flipping bits and utilizing a recursion scheme. The fast decoding technique may be employed to simultaneously decode multiple dimensions of a pattern on the media surface.

Abstract: A method of encoding data for transmission from a source to a destination over a communications channel is provided. A plurality of redundant symbols are generated from an ordered set of input symbols to be transmitted. A plurality of output symbols are generated from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of symbols in the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols, and such that the ordered set of input symbols can be regenerated to a desired degree of accuracy from any predetermined number, N, of the output symbols.

Abstract: A method for estimating a relative time difference vector in a group of digitized signals from a time interleaved analog-to-digital module having a plurality of parallel and time interleaved analog-to-digital converters. The method comprises the steps of selecting (S1) one of said digitized signals as a reference signal, calculating (S2-S3) an actual time delay between each of the remaining signals and said reference signal, and subtracting (S4), for each of said remaining signals, an intended interleaving time delay from said time delay. In order for this method to provide the correct estimate, the signal must be bandlimited, not only to the system bandwidth, but to the bandwidth of one ADC. However, given this bandwidth limitation, the estimation is very precise, and therefore enables reconstruction of the digitized signal without feedback.

Abstract: The invention relates to a modulation code system and a corresponding modulation method. Said modulation system comprises an encoder 100 for transforming an original signal s into an encoded signal c satisfying predefined second constraints. Said modulation code system further comprises a decoder 200 for decoding the encoded signal c after restoration back into the original signal s. It is the object of the invention to improve such a known modulation code system and method in the way that the amount of required hardware is reduced. This object is solved according to the invention by designing the encoder 100 such that it comprises a series connection of a modulation code encoder 110 and of a transformer encoder 120 serving for filtering an intermediate signal t output by said modulation code encoder 110 and satisfying predefined first constraints in order to generate said encoder output signal c.

Abstract: A digital data demodulator which can reduce a loss of decodable digital data, and increase capability of reproducing digital data inputted through a transmission line even when an error occurs in the transmission line. In the digital data demodulator, a specific pattern detector (113) detects a specific pattern to be included in a modulation code, from a bit string inputted through a transmission line (104). A modulation code identifying unit (117) generates a demodulation data strobe signal (119) according to a phase of the modulation code including the specific pattern. An error corrector (121) samples demodulation data (109) in response to the demodulation data strobe signal (119) and reproduces the data to the original digital data.

Abstract: A run-length limited (RLL) encoder includes a problematic-block detection module that receives a data block and that generates coding bits that indicate whether at least one of N portions of the data block include one of all ones and all zeros, where N is an integer greater than one. A mapping module generates an RLL codeword based on the data block and the coding bits. The RLL codeword includes N portions. One of the N portions of the RLL codeword is populated with the coding bits. At least another one of the remaining portions of the RLL codeword is populated with at least part of the data from one of the N portions of the data block that corresponds with the one of the N portions of the RLL codeword.

Abstract: A coding/decoding system and method are disclosed. Coding, as used herein, refers assigning values to cells. Information to be coded is processed stepwise in information pieces, with bitwise processing (single information bits as information pieces) as a special case. According to an illustrative embodiment, bitwise coding/decoding is disclosed. A predefined structure called a configuration is known to both the coding and decoding systems. The configuration includes a step configuration for each coding step. A step configuration is: 1) a distinction of two subsets of cells, one called inversion cells, the other called non inversion cells; 2) an assignment of at least one cell tuple consisting of at least one inversion cell and one non inversion cell each, where, for these tuples, for any preceding step configuration the tuple cells are either all inversion cells or all non inversion cells. For coding, in each step, its inversion cells are XORed with the information bit.

Abstract: Automatic test equipment (ATE) includes circuitry configured to pass a signal in a channel of the ATE, and memory configured to store a first look-up table (LUT) and a second LUT. The first LUT is configured to provide a first correction value based on a first version of the signal, where the first correction value are for use in correcting static non-linearity associated with the channel. The second LUT is configured to provide a second correction value based on a second version of the signal, where the second correction value are for use in correcting dynamic non-linearity associated with the channel. Digital signal processing logic is configured to use the first correction value, the second correction value, and the signal in order to compensate for harmonic distortion from the channel.

Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.

Abstract: A method and apparatus for transmitting data frames, and a method and apparatus for data rate matching wherein, via an interleaver, elements to be transmitted are distributed over a plurality of radio frames and repeated, the repetition being carried out in such a way that, when put into its relationship with the original arrangement of the elements before the interleaving, the pattern prevents the spacing between arbitrary consecutive repeated elements from being substantially greater than the mean repetition spacing.

Abstract: Techniques for puncturing symbols in a communications system. S symbols are received for a frame having a capacity of N symbols, with S being greater than N. P symbols need to be punctured so that remaining symbols fit into the frame. A number of puncture distances, D1 through DN, are computed based on S and P. A particular number of symbol punctures is determined for each computed puncture distance. P1 through PN symbol punctures are then performed at the distances of D1 through DN, respectively. For a more even distribution of the symbol punctures, each of the distances D1 through DN can be selected to be greater than or equal to a minimum puncture distance Dmin defined as Dmin=?S/P?, where ? ? denotes a floor operator. The symbol punctures at each computed distance can be performed together or distributed with symbol punctures at other distances.

Abstract: A bubble error rejecter includes a cascade of front and rear voting sections for correcting bubble errors spanning multiple bits from interpolation. The front voting section generates first correction codes from first thermometer codes determined from preamplified signals. The rear voting section generates second correction codes from the first correction codes and second thermometer codes determined from interpolation of the preamplified signals.

Abstract: A scalable audio codec processes, quantizes and encodes audio signals into an embedded audio bitstream of bit-planes each having a data unit. The data unit has a beginning refinement bits partition, a second significance bits partition, a third sign boundary mark bits partition, and a fourth sign bits partition. The second and fourth partitions form a boundary for the third partition. The quantizing uses a variable length coding algorithm. The third partition is an invalid codeword for a predetermined encoding method being used to encode. The codec uses a decoder to decode the embedded audio bitstream of bit-planes using Reversible exponential Golomb (Exp-Golomb) codes in a Reversible Variable Length Code (RVLC) algorithm to produce quantized data of weighted subbands. An inverse quantizer dequantizes the quantized data into audio signals.

Abstract: A method, apparatus, and program for image processing are provided to perform operations for generating an encoded image, detecting image alteration on the encoded image, and regenerating an original image from the encoded image. The encoded image is generated by an encoding apparatus, which inserts a redundant code into an LSB (least significant bit) bit-plane of the original image. The redundant code can be generated based on bit-planes other than the LSB bit-plane, using a CRC (cyclic redundancy check) method. A decoding apparatus recalculates a redundant code from the encoded image, and checks validity of the encoded image based on the extracted redundant code.

Abstract: The present invention relates to an encoding apparatus and a corresponding method for two-dimensionally encoding user data of a user data stream into channel data of a channel data stream along a two-dimensional channel strip of at least two bit rows one-dimensionally evolving along a first direction and being aligned with each other along a second direction, said two directions constituting a two-dimensional lattice of bit positions. According to the invention the apparatus comprises a modulation code encoder for modulation code encoding said user data into said channel data according to a two-dimensional modulation code being adapted to prevent predetermined worst case patterns of channel data in said channel data stream. The worst-case patterns are typical for high-density two-dimensional optical storage channels.

Abstract: The present invention discloses a decoding device. The decoding device includes a scaling unit for adjusting a received signal according to a scaling coefficient to generate a scaled signal; a quantizer coupled to the scaling unit for generating a quantized signal by quantizing the scaled signal; a soft decision decoder coupled to the quantizer for decoding the quantized signal to generate a decoded signal; and a scaling coefficient generating unit coupled to the scaling unit for generating the scaling coefficient according to a system information of the decoding device.

Abstract: A communication system includes an encoder that receives user data and includes running digital sum encoding and turbo encoding. The running digital sum encoding is preserved in an encoder output to a channel. A decoder receives a channel output and comprises running digital sum decoding and turbo decoding to reproduce the user data in a decoder output.

Abstract: A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one.

Abstract: A recording method, wherein, when a certain portion of main data is recorded by being encoded by a first encoding method and the other portions of the main data is recorded by being encoded by a second encoding method, an encoding process is performed by the first encoding method so that, when data which is recorded in such a manner that the data encoded by the first encoding method is decoded by a decoding method corresponding to the first encoding method, and thereafter, is further encoded by the second encoding method, is decoded by a decoding method corresponding to the second encoding method, the sum value of DC components per unit time increases.

Abstract: The invention concerns a method and apparatus for performing packet loss or Frame Erasure Concealment (FEC) for a speech coder that does not have a built-in or standard FEC process. A receiver with a decoder receives encoded frames of compressed speech information transmitted from an encoder. A lost frame detector at the receiver determines if an encoded frame has been lost or corrupted in transmission, or erased. If the encoded frame is not erased, the encoded frame is decoded by a decoder and a temporary memory is updated with the decoder's output. A predetermined delay period is applied and the audio frame is then output. If the lost frame detector determines that the encoded frame is erased, a FEC module applies a frame concealment process to the signal. The FEC processing produces natural sounding synthetic speech for the erased frames.

Abstract: The multimedia data decoder includes a decoding section and a control section. The decoding section for decoding coded data in a bit stream has a function to detect a synchronous word from the bit stream, analyze decoding information following the synchronous word and extract specific option designating information from the decoding information. The control section determines whether or not the option designating information extracted by the decoding section has any out-of-standard value, that is, any value that is not defined by a standard. If the option designating information has any out-of-standard data, the control section controls the decoding section so as to replace the out-of-standard value with a value defined by the standard and conduct a decoding process. For this purpose, the control section applies replacement information to the decoding section. Accordingly, decoded data is obtained even if the decoding information has an out-of-standard value.

Abstract: Flexibly configurable layer one transport channels produce radio blocks in response to communication information and extract communication information from radio blocks. Each transport channel can include an encoder or a decoder coupled to and cooperable with a data puncturer or a data repeater. An information source can produce for each transport channel first configuration information and second configuration information, wherein the first configuration information is indicative of how the associated transport channel is to be configured if a first modulation type is used for a current radio block, and wherein the second configuration information is indicative of how the associated transport channel is to be configured if a second modulation type is used for the current radio block. The physical layer can include a description information source that provides description information from which various configurations of the transport channels can be determined.

Abstract: Provided is a method, system, and program for providing synchronization in a binary data stream. A binary data stream is received. A synchronization mark having at least one isolated peak is generated into at least one point in the data stream. An encoded data stream is formed by concatenating the synchronization mark with the received binary data. During decoding, the synchronization mark is detected based on error propagation occurring adjacent to the at least one isolated peak of the synchronization mark.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.